KR930024143A - 다층 리드프레임 - Google Patents
다층 리드프레임 Download PDFInfo
- Publication number
- KR930024143A KR930024143A KR1019930007732A KR930007732A KR930024143A KR 930024143 A KR930024143 A KR 930024143A KR 1019930007732 A KR1019930007732 A KR 1019930007732A KR 930007732 A KR930007732 A KR 930007732A KR 930024143 A KR930024143 A KR 930024143A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- lead
- ground
- power
- layers
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49527—Additional leads the additional leads being a multilayer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 층간의 접속을 확실하게 행하는 동시에 저항용접에 의하지 않고 층간을 전기적으로 접속가능하고 다층 리드프레임의 제조를 용이하게 함을 목적으로 한다.
그 구성은 층간에 전기적 절연층을 거쳐서 신호층과 전원층 또는 접지층등을 다층으로 적층하여 된 다층 리드프레임에 있어서, 상기 신호층(12)과 상기 전원층(14) 또는 접지층등이 전기적 절연성을 갖는 절연필름에 두께방향으로 연락하는 금속비어(20b)를 형성한 코넥터 테이프(20)에 의해서 일체로 접합하고 상기 신호층(12)의 전원리드 또는 접지리드와 상기 전원층(14) 또는 접지층이 상기 전원리드 또는 접지리드의 배치 위치에 맞추어서 형성한 금속 비어(20b)를 거쳐서 전기적으로 접속한 것을 특징으로 한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 다층 리드프레임의 일실시예의 구성을 나타낸 단면도, 제2도는 코넥터 테이프 및 신호층등의 평면배치를 나타낸 설명도, 제3도는 코넥터 테이프의 사시도, 제4도는 다층 리드프레임의 다른 실시예의 구성을 나타낸 단면도.
Claims (2)
- 층간에 전기적 절연층을 거쳐서 신호층과 전원층 또는 접지층등을 다층으로 적층하여된 다층 리드프레임에 있어서, 상기 신호층과 상기 전원층 또는 접지층등이 전기적 절연성을 갖는 절연필름에 두께방향으로 연락하는 금속비어를 형성한 코넥터 테이프에 의해서 일체로 접합하고 상기 신호층의 전원리드 또는 접지 리드와 상기 전원층 또는 접지층이 상기 전원리드 또는 접지리드의 배치위치에 맞추어서 형성한 금속비어를 거쳐서 전기적으로 접속한 것을 특징으로 하는 다층 리드프레임.
- 신호층의 전원리드 또는 접지리드의 리드폭내에 복수개의 금속비어를 배치한 것을 특징으로 하는 다층 리드프레임.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4163752A JP3051569B2 (ja) | 1992-05-29 | 1992-05-29 | 多層リードフレーム |
JP92-163752 | 1992-05-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930024143A true KR930024143A (ko) | 1993-12-22 |
KR970003911B1 KR970003911B1 (ko) | 1997-03-22 |
Family
ID=15780027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930007732A KR970003911B1 (ko) | 1992-05-29 | 1993-05-06 | 다층 리드프레임 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5399809A (ko) |
EP (1) | EP0572282B1 (ko) |
JP (1) | JP3051569B2 (ko) |
KR (1) | KR970003911B1 (ko) |
DE (1) | DE69322124T2 (ko) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653277A (ja) * | 1992-06-04 | 1994-02-25 | Lsi Logic Corp | 半導体装置アセンブリおよびその組立方法 |
JPH07147365A (ja) * | 1993-10-01 | 1995-06-06 | Electroplating Eng Of Japan Co | リードフレームの変形防止方法 |
GB2293918A (en) * | 1994-10-06 | 1996-04-10 | Ibm | Electronic circuit packaging |
KR100431556B1 (ko) * | 2001-11-20 | 2004-05-12 | 엘지전선 주식회사 | 표면실장형 온도보상 수정발진자 |
TWI250632B (en) * | 2003-05-28 | 2006-03-01 | Siliconware Precision Industries Co Ltd | Ground-enhancing semiconductor package and lead frame |
CN104582239A (zh) * | 2013-10-24 | 2015-04-29 | 鸿富锦精密工业(武汉)有限公司 | 印刷电路板 |
USD863836S1 (en) * | 2017-04-17 | 2019-10-22 | Okamura Corporation | Storage furniture |
USD899253S1 (en) * | 2018-06-29 | 2020-10-20 | Magic Leap, Inc. | Insert for packaging container |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3597834A (en) * | 1968-02-14 | 1971-08-10 | Texas Instruments Inc | Method in forming electrically continuous circuit through insulating layer |
US3848077A (en) * | 1970-10-16 | 1974-11-12 | M Whitman | Package for electronic semiconductor devices |
US4113981A (en) * | 1974-08-14 | 1978-09-12 | Kabushiki Kaisha Seikosha | Electrically conductive adhesive connecting arrays of conductors |
US4925024A (en) * | 1986-02-24 | 1990-05-15 | Hewlett-Packard Company | Hermetic high frequency surface mount microelectronic package |
US5180888A (en) * | 1989-08-10 | 1993-01-19 | Casio Computer Co., Ltd. | Conductive bonding agent and a conductive connecting method |
US5025114A (en) * | 1989-10-30 | 1991-06-18 | Olin Corporation | Multi-layer lead frames for integrated circuit packages |
JP2984064B2 (ja) * | 1989-12-19 | 1999-11-29 | 日東電工株式会社 | 異方導電フィルムの製造方法 |
JP3154713B2 (ja) * | 1990-03-16 | 2001-04-09 | 株式会社リコー | 異方性導電膜およびその製造方法 |
JPH07123179B2 (ja) * | 1990-10-05 | 1995-12-25 | 信越ポリマー株式会社 | 異方導電接着剤による回路基板の接続構造 |
-
1992
- 1992-05-29 JP JP4163752A patent/JP3051569B2/ja not_active Expired - Lifetime
-
1993
- 1993-05-06 KR KR1019930007732A patent/KR970003911B1/ko not_active IP Right Cessation
- 1993-05-26 US US08/067,076 patent/US5399809A/en not_active Expired - Fee Related
- 1993-05-28 EP EP93304199A patent/EP0572282B1/en not_active Expired - Lifetime
- 1993-05-28 DE DE69322124T patent/DE69322124T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69322124D1 (de) | 1998-12-24 |
EP0572282B1 (en) | 1998-11-18 |
JPH05335473A (ja) | 1993-12-17 |
DE69322124T2 (de) | 1999-04-15 |
JP3051569B2 (ja) | 2000-06-12 |
KR970003911B1 (ko) | 1997-03-22 |
EP0572282A1 (en) | 1993-12-01 |
US5399809A (en) | 1995-03-21 |
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Payment date: 20020806 Year of fee payment: 6 |
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