DE69322124D1 - Verfahren zur Herstellung eines Mehrschicht-Leitergitters für eine Halbleiteranordnung - Google Patents
Verfahren zur Herstellung eines Mehrschicht-Leitergitters für eine HalbleiteranordnungInfo
- Publication number
- DE69322124D1 DE69322124D1 DE69322124T DE69322124T DE69322124D1 DE 69322124 D1 DE69322124 D1 DE 69322124D1 DE 69322124 T DE69322124 T DE 69322124T DE 69322124 T DE69322124 T DE 69322124T DE 69322124 D1 DE69322124 D1 DE 69322124D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor arrangement
- multilayer conductor
- conductor grid
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49527—Additional leads the additional leads being a multilayer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4163752A JP3051569B2 (ja) | 1992-05-29 | 1992-05-29 | 多層リードフレーム |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69322124D1 true DE69322124D1 (de) | 1998-12-24 |
DE69322124T2 DE69322124T2 (de) | 1999-04-15 |
Family
ID=15780027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69322124T Expired - Fee Related DE69322124T2 (de) | 1992-05-29 | 1993-05-28 | Verfahren zur Herstellung eines Mehrschicht-Leitergitters für eine Halbleiteranordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5399809A (de) |
EP (1) | EP0572282B1 (de) |
JP (1) | JP3051569B2 (de) |
KR (1) | KR970003911B1 (de) |
DE (1) | DE69322124T2 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653277A (ja) * | 1992-06-04 | 1994-02-25 | Lsi Logic Corp | 半導体装置アセンブリおよびその組立方法 |
JPH07147365A (ja) * | 1993-10-01 | 1995-06-06 | Electroplating Eng Of Japan Co | リードフレームの変形防止方法 |
GB2293918A (en) * | 1994-10-06 | 1996-04-10 | Ibm | Electronic circuit packaging |
KR100431556B1 (ko) * | 2001-11-20 | 2004-05-12 | 엘지전선 주식회사 | 표면실장형 온도보상 수정발진자 |
TWI250632B (en) * | 2003-05-28 | 2006-03-01 | Siliconware Precision Industries Co Ltd | Ground-enhancing semiconductor package and lead frame |
CN104582239A (zh) * | 2013-10-24 | 2015-04-29 | 鸿富锦精密工业(武汉)有限公司 | 印刷电路板 |
USD863836S1 (en) * | 2017-04-17 | 2019-10-22 | Okamura Corporation | Storage furniture |
USD899253S1 (en) * | 2018-06-29 | 2020-10-20 | Magic Leap, Inc. | Insert for packaging container |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3597834A (en) * | 1968-02-14 | 1971-08-10 | Texas Instruments Inc | Method in forming electrically continuous circuit through insulating layer |
US3848077A (en) * | 1970-10-16 | 1974-11-12 | M Whitman | Package for electronic semiconductor devices |
US4113981A (en) * | 1974-08-14 | 1978-09-12 | Kabushiki Kaisha Seikosha | Electrically conductive adhesive connecting arrays of conductors |
US4925024A (en) * | 1986-02-24 | 1990-05-15 | Hewlett-Packard Company | Hermetic high frequency surface mount microelectronic package |
US5180888A (en) * | 1989-08-10 | 1993-01-19 | Casio Computer Co., Ltd. | Conductive bonding agent and a conductive connecting method |
US5025114A (en) * | 1989-10-30 | 1991-06-18 | Olin Corporation | Multi-layer lead frames for integrated circuit packages |
JP2984064B2 (ja) * | 1989-12-19 | 1999-11-29 | 日東電工株式会社 | 異方導電フィルムの製造方法 |
JP3154713B2 (ja) * | 1990-03-16 | 2001-04-09 | 株式会社リコー | 異方性導電膜およびその製造方法 |
JPH07123179B2 (ja) * | 1990-10-05 | 1995-12-25 | 信越ポリマー株式会社 | 異方導電接着剤による回路基板の接続構造 |
-
1992
- 1992-05-29 JP JP4163752A patent/JP3051569B2/ja not_active Expired - Lifetime
-
1993
- 1993-05-06 KR KR1019930007732A patent/KR970003911B1/ko not_active IP Right Cessation
- 1993-05-26 US US08/067,076 patent/US5399809A/en not_active Expired - Fee Related
- 1993-05-28 EP EP93304199A patent/EP0572282B1/de not_active Expired - Lifetime
- 1993-05-28 DE DE69322124T patent/DE69322124T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR970003911B1 (ko) | 1997-03-22 |
EP0572282A1 (de) | 1993-12-01 |
JPH05335473A (ja) | 1993-12-17 |
DE69322124T2 (de) | 1999-04-15 |
EP0572282B1 (de) | 1998-11-18 |
US5399809A (en) | 1995-03-21 |
JP3051569B2 (ja) | 2000-06-12 |
KR930024143A (ko) | 1993-12-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |