KR910020866A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR910020866A
KR910020866A KR1019910007181A KR910007181A KR910020866A KR 910020866 A KR910020866 A KR 910020866A KR 1019910007181 A KR1019910007181 A KR 1019910007181A KR 910007181 A KR910007181 A KR 910007181A KR 910020866 A KR910020866 A KR 910020866A
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KR
South Korea
Prior art keywords
semiconductor
semiconductor chip
chip
device hole
conductive pattern
Prior art date
Application number
KR1019910007181A
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English (en)
Inventor
요시히꼬 가사하라
다쯔로 이또
Original Assignee
야마무라 가쯔미
세이꼬 엡슨 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 야마무라 가쯔미, 세이꼬 엡슨 가부시끼가이샤 filed Critical 야마무라 가쯔미
Publication of KR910020866A publication Critical patent/KR910020866A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 한 실시예의 상태를 밀봉 처리 이전에 도시한 평면도, 제2도는 본 발명의 한 실시예의 상태를 밀봉 처리 이전에 도시한 횡단면도, 제3도는 본 발명의 한 다른 실시예의 상태를 밀봉 처리 이전에 도시한 평면도.

Claims (4)

  1. 막 캐리어의 디바이스 홀 내측에 반도체 칩을 설치하고, 상기 반도체 칩에 제공된 다수의 전극에 상기 막 캐리어 각각에 형성된 디바이스 홀 내측에 돌출된 다수의 전도성 패턴의 내부 리드를 접속시키고, 밀봉 수지로 상기 반도체 칩 혹은 반도체 칩 및 전도성 패턴의 일부를 밀봉하는 반도체 장치에 있어서, 상기 디바이스 홀을 구성하는 개구의 엣지와 디바이스 홀 내측에 설치된 반도체 칩의 외부 주변 엣지에 형성된 간격은 0.4mm 내지 0.8mm로 설정되는 것을 특징으로 하는 반도체 장치.
  2. 막 캐리어의 디바이스 홀 내측에 반도체 칩을 설치하고, 상기 반도체 칩에 제공된 다수의 전극에 상기 막 캐리어 각각에 형성된 디바이스 홀 내측에 돌출된 다수의 전도성 패턴의 내부 리드를 접속시키고, 밀봉 수지로 상기 반도체 칩 혹은 반도체 칩 및 전도성 패턴의 일부를 밀봉하는 반도체 장치에 있어서, 상기 내부 리드상의 거의 중간 위치에 굴곡부를 제공하는 을 특징으로 하는 반도체 장치.
  3. 막 캐리어의 디바이스 홀 내측에 반도체 칩을 설치하고, 상기 반도체 칩에 제공된 다수의 전극에 상기 막 캐리어 각각에 형성된 디바이스 홀 내측에 돌출된 다수의 전도성 패턴의 내부 리드를 접속시키고, 밀봉 수지로 상기 반도체 칩 혹은 반도체 칩 및 전도성 패턴의 일부를 밀봉하는 반도체 장치에 있어서, 상기 막 캐리어의 디바이스 홀을 구성하는 개구의 엣지상에 각각의 전도성 패턴 근처에 절단부를 제공하는 것을 특징으로 하는 반도체 장치.
  4. 제3항에 있어서, 상기 절단부는 길고 좁은 정방형으로 된 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910007181A 1990-05-08 1991-05-03 반도체 장치 KR910020866A (ko)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP126140 1986-08-19
JP11842790 1990-05-08
JP118427 1990-05-08
JP12614090 1990-05-16
JP51113 1990-05-16
JP5111390 1990-05-16
JP80068 1991-04-12
JP3080068A JP3033227B2 (ja) 1990-05-08 1991-04-12 半導体装置

Publications (1)

Publication Number Publication Date
KR910020866A true KR910020866A (ko) 1991-12-20

Family

ID=27462589

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007181A KR910020866A (ko) 1990-05-08 1991-05-03 반도체 장치

Country Status (4)

Country Link
US (1) US5231303A (ko)
EP (1) EP0456066A3 (ko)
JP (1) JP3033227B2 (ko)
KR (1) KR910020866A (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123448A (ja) * 1990-09-14 1992-04-23 Toshiba Corp 半導体実装装置
JP2857492B2 (ja) * 1990-11-28 1999-02-17 シャープ株式会社 Ｔａｂパッケージ
JP3238004B2 (ja) * 1993-07-29 2001-12-10 株式会社東芝 半導体装置の製造方法
US5569956A (en) * 1995-08-31 1996-10-29 National Semiconductor Corporation Interposer connecting leadframe and integrated circuit
US5760465A (en) * 1996-02-01 1998-06-02 International Business Machines Corporation Electronic package with strain relief means
US6277225B1 (en) * 1996-03-13 2001-08-21 Micron Technology, Inc. Stress reduction feature for LOC lead frame
JP2910670B2 (ja) * 1996-04-12 1999-06-23 日本電気株式会社 半導体実装構造
JPH10116862A (ja) * 1996-10-11 1998-05-06 Texas Instr Japan Ltd テープキャリアパッケージ
JP3584470B2 (ja) * 1996-10-22 2004-11-04 セイコーエプソン株式会社 フィルムキャリアテープの製造方法及び半導体装置の製造方法
US5923081A (en) * 1997-05-15 1999-07-13 Micron Technology, Inc. Compression layer on the leadframe to reduce stress defects
US6075286A (en) * 1997-06-02 2000-06-13 International Rectifier Corporation Stress clip design
JP3147071B2 (ja) * 1998-01-19 2001-03-19 日本電気株式会社 半導体装置及びその製造方法
KR100574278B1 (ko) * 1998-11-27 2006-09-22 삼성전자주식회사 테이프 캐리어 패키지 및 이를 이용한 액정표시기모듈
US20050154567A1 (en) * 1999-06-18 2005-07-14 President And Fellows Of Harvard College Three-dimensional microstructures
WO2001051276A2 (en) 2000-01-07 2001-07-19 President And Fellows Of Harvard College Fabrication of metallic microstructures via exposure of photosensitive composition
TWI285523B (en) * 2005-08-19 2007-08-11 Chipmos Technologies Inc Flexible substrate capable of preventing lead thereon from fracturing
KR101259844B1 (ko) * 2011-01-31 2013-05-03 엘지이노텍 주식회사 리드 크랙이 강화된 전자소자용 탭 테이프 및 그의 제조 방법
JP6752981B2 (ja) * 2017-10-26 2020-09-09 新電元工業株式会社 半導体装置の製造方法

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* Cited by examiner, † Cited by third party
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US4736236A (en) * 1984-03-08 1988-04-05 Olin Corporation Tape bonding material and structure for electronic circuit fabrication
US4721993A (en) * 1986-01-31 1988-01-26 Olin Corporation Interconnect tape for use in tape automated bonding
US4743956A (en) * 1986-12-15 1988-05-10 Thomson Components-Moster Corporation Offset bending of curvaceously planar radiating leadframe leads in semiconductor chip packaging
JPS63164331A (ja) * 1986-12-26 1988-07-07 Matsushita Electric Ind Co Ltd フイルムキヤリヤリ−ド
JPS63288039A (ja) * 1987-05-20 1988-11-25 Matsushita Electric Ind Co Ltd フィルムキャリア実装検査方法
JPH0793344B2 (ja) * 1987-05-20 1995-10-09 松下電器産業株式会社 フイルムキヤリア
JPH02292836A (ja) * 1989-05-02 1990-12-04 Nippon Steel Corp Ｉｃチップ実装用フィルムキャリア

Also Published As

Publication number Publication date
EP0456066A2 (en) 1991-11-13
EP0456066A3 (en) 1993-02-03
JPH04218934A (ja) 1992-08-10
JP3033227B2 (ja) 2000-04-17
US5231303A (en) 1993-07-27

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