KR900007066A - 드라이에칭방법 및 드라이에칭 장치 - Google Patents

드라이에칭방법 및 드라이에칭 장치 Download PDF

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KR900007066A
KR900007066A KR1019890014762A KR890014762A KR900007066A KR 900007066 A KR900007066 A KR 900007066A KR 1019890014762 A KR1019890014762 A KR 1019890014762A KR 890014762 A KR890014762 A KR 890014762A KR 900007066 A KR900007066 A KR 900007066A
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gas
etching
dry etching
power
plasma
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KR970000417B1 (ko
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다이라 사다유끼 오꾸
히로시 가와가미
도꾸오 구레
모도 가즈노리 쯔지
싱이찌 다찌
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미다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/913—Diverse treatments performed in unitary chamber

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

내용 없음

Description

드라이에칭방법 및 드라이에칭 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 드라이에칭 장치의 요부의 단면구조의 일예를 나타낸도,
제2도 및 제4도는 본 발명의 일실시예를 설명하기 위한 도,
제3도는 본 발명의 TM에칭의 타임스케줄의 일예를 나타낸 도.

Claims (10)

  1. 에칭가스와 증착가스를 반응 챔버내에 소정의 시간 간격으로 교대로 도입하고 상기 반응 챔버내에 도입된 상기 에칭가스와 증착가스에 각각 전력을 인가하여 발생시킨 플타즈마를, 상기 반응 챔버내에 놓여진 피처리 시료에 접촉시켜 상기 피처리 시료의 노출된 표면의 에칭과 그 표면상에의 막의 증착을 교대로 행하고, 그에 의하여 상기 표면을 에칭하는 드라이 에칭방법에 있어서, 상기 전력은, 상기 증착가스의 도입 개시로부터 소정의 시간이 경과한 후이고, 상기 에칭가스가 도입되기 전의 시각에 두입되고, 상기 에칭가스의 도입이 정지됐을 때 차단되는 드라이 에칭방법.
  2. 제1항에 있어서, 상기 에칭가스의 도입개시와 함께 상기 피에칭 시료 또는 그 근방에는 RF파워가 인가되고, 상기 에칭 가스의 도입이 정지하기 전에 차단되는 것을 특징으로 하는 드라이 에칭방법.
  3. 제1항에 있어서, 상기 증착가스가 도입이 개시된 후 상기 전력이 투입되기까지의 시간 t는, 상기 반응 챔버내의 잔류 에칭가스의 압력(VE)에 대한 전가스 압력(VE+VD)의 비가
    단 VD:증착가스압력을 만족시키도록 선택되는 것을 특징으로 하는 드라이 에칭방법.
  4. 제1항에 있어서, 상기 파워는 μ웨이브 파워인 것을 특징으로 하는 드라이 에칭방법.
  5. 제1항에 있어서, 상기 에칭가스는 SF6인 것을 특징으로 하는 드라이 에칭방법.
  6. 제1항에 있어서, 상기 증착가스는, CCl4, C2Cl3F3, C2ClF5, SiH3Cl, CHCl3, CH3Cl, CBrF3및 C2Br2F4의 군으로부터 선택되는 것을 특징으로 하는 드라이 에칭방법.
  7. 제1항에 있어서, 상기 파워는, 상기 반응 챔버내에 설치된 평행 평판행 전극에 인가되는 것을 특징으로 하는 드라이 에칭방법.
  8. 피처리 시료를 지지하는 수단을 내장한 반응챔버와, 상기 챔버내에 플라즈마를 발생시키기 위한 전력 투입 수단과, 상기 챔버 내에 적어도 에칭가스와 증착가스를 교대로 시간적으로 절환하여 주기적으로 공급할 수 있는 적어도 2계통의 가스 도입 수단을 구비한 드라이 에칭장치로서, 상기 가스 도입 수단에는 각각의 가스 유량에 맞추어 순차 소정시간의 주기로 교대로 절환할 수 있는 가스 절환 제어기를 접속함과 동시에 상기 가스 절환 제어기의 가스 절환 주기에 연동시켜 상기 플라즈마를 발생시키는 전력 투입수단을 주기적으로 온-오프 동작시키는 전력 투입 제어기를 구비한 것을 특징으로 하는 드라이 에칭 처리 장치.
  9. 제8항에 있어서, 상기 피처리 시료 또는 그 주변에 고주파 바이어스 전력을 주기적으로 투입하는 수단을 설치함과 동시에, 상기 주기적 고주파 전력 투입의 온-오프 제어를 상기 가스 절환 제어기에 있어서의 에칭 가스 주기와 연동시켜 상기 전력투입 제어기에서 동작시키는 구성으로한 것을 특징으로 하는 플라즈마 에칭 처리장치.
  10. 제8항에 있어서, 상기 플라즈마를 발생시키는 전력 투입 수단은 마이크로파 전력 투입 수단인 것을 특징으로 하는 플라즈마 에칭 처리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890014762A 1988-10-14 1989-10-14 드라이 에칭방법 및 드라이 에칭장치 KR970000417B1 (ko)

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JP63-256953 1988-10-14
JP63256953A JP2918892B2 (ja) 1988-10-14 1988-10-14 プラズマエッチング処理方法

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KR900007066A true KR900007066A (ko) 1990-05-09
KR970000417B1 KR970000417B1 (ko) 1997-01-09

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US (1) US4985114A (ko)
EP (1) EP0363982B1 (ko)
JP (1) JP2918892B2 (ko)
KR (1) KR970000417B1 (ko)
DE (1) DE68927699T2 (ko)

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