JPH06103692B2 - 集積回路素子の製造方法 - Google Patents
集積回路素子の製造方法Info
- Publication number
- JPH06103692B2 JPH06103692B2 JP2199367A JP19936790A JPH06103692B2 JP H06103692 B2 JPH06103692 B2 JP H06103692B2 JP 2199367 A JP2199367 A JP 2199367A JP 19936790 A JP19936790 A JP 19936790A JP H06103692 B2 JPH06103692 B2 JP H06103692B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- silicon dioxide
- manufacturing
- substrate
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 141
- 235000012239 silicon dioxide Nutrition 0.000 claims description 71
- 239000000377 silicon dioxide Substances 0.000 claims description 70
- 239000004020 conductor Substances 0.000 claims description 49
- 238000000151 deposition Methods 0.000 claims description 38
- 239000007789 gas Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 28
- 230000008021 deposition Effects 0.000 claims description 27
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 13
- 238000007740 vapor deposition Methods 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 230000002401 inhibitory effect Effects 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 230000002452 interceptive effect Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims 1
- 230000001737 promoting effect Effects 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000003112 inhibitor Substances 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000002835 absorbance Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- GVGCUCJTUSOZKP-UHFFFAOYSA-N nitrogen trifluoride Chemical compound FN(F)F GVGCUCJTUSOZKP-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/118—Oxide films
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
Description
細には、本発明は集積回路の製造中における二酸化シリ
コンの蒸着に関する。
たは基板に形成できる密度を増大させ続けることであ
る。このようなチップ内の高密度素子の相互接続は、極
めて小さく、しかも、互いに極めて接近した導体のその
表面上に形成しなければならない。従って、多くの場
合、重複する導体パターンは別の導体層と垂直的に間隔
を設けて分離されている。当然、2層以上の導体層を使
用する場合、導体の下層側の上面に高信頼性の絶縁層を
被着しなければならない。こうすることにより、重複す
る上部側の導体層は不慮の短絡またはその他の導電異常
を起こす危険なしに形成することができる。
は一般的に、二酸化シリコンにより集積回路の半導体ウ
エハまたはチップ部分から絶縁されている。この二酸化
シリコンは例えば、化学的気相成長法(CVD)によりシ
リコンウエハ上に容易に形成される。二酸化シリコンは
熱特性および電気特性の点で優れており、また、選択的
なマスキングおよびエッチングにより容易にパターン形
成されるので、導体の絶縁材料として絶好である。しか
し、運悪く、CVDに通常必要な高温度はアルミニウムの
ような金属からなる導体を溶融または損傷する可能性が
あるので、一般的に、第1の導体層上に二酸化シリコン
を蒸着するのにCVDは使用できない。
り二酸化シリコンを蒸着する方法が広く行われるように
なってきた。このようなプラズマは対向する平行平板電
極を有する反応装置内で発生される。前記電極のうち、
一方の電極は接地され、他方の電極は高周波源により励
起される。プラズマは、CVDに必要な温度よりも低い温
度で二酸化シリコンを生成し、そして、蒸着させるのに
必要な反応を高めるためのエネルギーを供給する。この
ため、この蒸着はプラズマ増強化学的気相成長法(PECV
D)と呼ばれることがある。酸化シリコン(SiO)のよう
なその他の酸化物もこの方法により蒸着できるが、主た
る蒸着物質は二酸化シリコン(SiO2)である。また、蒸
着は半導体の部品としての“基板”、金属導体また既に
蒸着された、もしくは、成長された二酸化シリコン上に
行われる。
スまたはその他のシリコン含有ガスの何れであってもよ
い。1988年3月31日に出願されたディーンらの米国継続
出願第175567号明細書には、プラズマ蒸着雰囲気とし
て、酸素と一緒にテトラエトキシシラン(TEOS)を使用
することの利点が開示されている。この明細書には、全
ての導体について信頼性の高い絶縁層を形成することの
ような、互いに極めて接近した導体を有する集積回路上
に二酸化シリコン蒸着膜を形成することの困難性が開示
されている。この問題に対する一般的な解決手段は、出
来るだけ相似形の蒸着膜を形成してみること、すなわ
ち、導体の外面形状に出来るだけ近い相似形の二酸化シ
リコン被膜を形成することである。特に注意すべきこと
は、導体パターンを画成するための通常のマスク方法お
よびエッチング方法により不可避的に生じる導体の鋭い
角部に高信頼性の被覆を形成することである。
合、相似形被膜であっても様々な問題が生じることが確
認された。特に、互いに接近して隣接する導体の相似形
被膜は、蒸着二酸化シリコン内にボイドまたはその他の
特徴的な欠陥を形成するような方向に向かって一緒に成
長しがちである。蒸着後、二酸化シリコンの上面は通
常、エッチングまたは研磨され、該上面を平坦し、そし
て、引き続き、導体パターンを蒸着二酸化シリコン膜上
に形成する。蒸着二酸化シリコン膜中のポイドまたは重
大な欠陥はしばしば、被膜の構造的特性および絶縁性の
予測不可能な変動を生じる。
2の導体層に信頼性の高い絶縁層および支持層をもたら
す、互いに接近した金属導体上に二酸化シリコンを蒸着
する方法を提供することである。
法により、互いに接近した導体を有する基板上に安定な
比較的欠陥の少ない蒸着二酸化シリコン膜を形成できる
ことが発見された。特に、このようなプラズマ蒸着は、
基板にたやすく吸着し、かつ、二酸化シリコンが基板に
蒸着するのを阻害するガス状物質と共に、シリコン源と
してテトラエトキシシラン(TEOS)を使用することから
なる。基板が配置される高周波プラズマは高出力プラズ
マである。例えば、高周波出力は100W以上である。高出
力プラズマは基板に対して垂直な電界線に沿ってイオン
を加速する。これにより、基板の垂直面における衝突の
エネルギーおよび密度よりも著しく高い運動エネルギー
で基板の水平面にイオンを衝突させる。その結果、阻害
ガスの分子は衝突イオンにより水平面から優先的に除去
される。TEOSは高い表面拡散性または高い表面易動性を
有する。この特性によりTEOSは水平面の反応部位で利用
され易くなる。この反応部位では阻害ガス分子が事前に
除去されているので、TEOSは該部位で蒸着二酸化シリコ
ン膜を形成することができる。従って、二酸化シリコン
は水平面に優先的に蒸着し、そして、主に垂直方向に向
かって成長する。垂直面には比較的少ししか蒸着せず、
また、水平方向には比較的少ししか成長しないので、2
つの互いに接近した垂直壁が“一緒に成長する”ことに
より欠陥が発生する可能性は低くなる。本発明による最
終の二酸化シリコン膜は、従来の“相似形”蒸着を行う
のに細心の注意が必要な互いに接近した導体上に蒸着し
た二酸化シリコン膜に比べて、一層均質であり、また、
欠陥が少ないことが確認された。
る。
シリコンを蒸着するのに使用されるプラズマ蒸着反応装
置10が示されている。反応装置は互いに対向する概ね平
行な電極11および12を有する。この平行平板電極間で高
周波プラズマが発生される。反応装置10は米国のカリフ
ォルニア州、サンタクララに所在のアップライドマテリ
アル社から市販されている“プレシジョン5000システ
ム”と呼ばれる。一般的なタイプのものを使用できる。
電極12は高周波電源13から一般的に、13.56MHzの高周波
エネルギーで励起される。図示されているように、電極
11は接地されており、シリコンウエハ15を支持する。こ
のシリコンウエハ15は表面に二酸化シリコン(SiO2)蒸
着を行うべき基板となる。プラズマから蒸着するための
SiO2のシリコン成分は加熱液源16から供給されるガス状
のテトラエトキシシラン(TEOS)から得られる。一般的
に、TEOSは液体の形で市販されており、気化された形の
TEOSは供給源17から液体TEOS中にヘリウムを吹き込み、
そして、図示されているように、TEOS容器から気化分子
を給送する。また、プラズマ雰囲気中に酸素ガスを含有
させることが好ましい。この酸素ガスは供給源18から得
られる。本発明によれば、供給源19から得られるアンモ
ニアガスまたはNH3も使用される。しかし、下記におい
て説明するように、NH3の代わりにNF3も使用できる。所
望のガスを所定量だけ注入するための各種の流量計およ
びその他の装置は当業者に公知なので、簡略化のために
図示もしないし、説明もしない。
り、矢線で示されるように注入ガスが流下できるように
するための複数個の開口部20を有する。従って、ガスは
シリコンウエハの表面上を放射状に流れ、そして、プレ
ート22の開口部21から環状真空溝23に誘導され、ガスは
この環状真空溝23から排気ダクト24を経て反応装置外に
排出される。下側電極11は複数個のランプ26で加熱され
る。光は石英窓27から入射され、電極11の酸化アルミニ
ウム層28に当射される。これにより、ウエハ15の表面に
存在する全ての金属導体の融点よりも低い温度にまで雰
囲気を加熱する。高周波プラズマの目的は雰囲気中の分
子をイオン化し、これにより、該分子に十分な追加エネ
ルギーを与え、雰囲気中のシリコンおよび酸素成分から
ウエハ15の表面に二酸化シリコンの化学的気相成長(CV
D)を可能にする。
り二酸化シリコン絶縁層で被覆され、この絶縁層の上に
第1の導体層が形成される。導体および蒸着二酸化シリ
コンは第2図および第3図に示されるように形成できる
ことが知られている。第1の導体層は断面図で示されて
いるように、導体30からなる。この第1の導体層はCVD
蒸着二酸化シリコン31の層上に形成されている。TEOSを
用いたプラズマ蒸着によれば、基板上に蒸着二酸化シリ
コンの相似形被膜32を形成できることが知られている。
このような被膜の特徴は、角部がプラズマ分子に若干過
度に暴露されるために、図示されているように導体の角
部に僅かなふくらみが生じることである。第2図に示さ
れるように、所望の厚さを有していれば、蒸着被膜32
は、特に導体30の高信頼性角部被覆を形成するので、全
く申し分のないものである。しかし、導体が互いに極め
て接近しているような場合、第2の導体層を形成するの
に十分な厚さの二酸化シリコンを蒸着するときに深刻な
問題が起こる。導体の高さとその間隙との比(構造体の
アスペクト比と呼ばれる)は第2図では、概ね同等に図
示されている。蒸着SiO2層の膜厚およびアスペクト比の
両方が大きくなる場合はいつも、隣接する垂直壁から蒸
着二酸化シリコンは、第3図に示すように、一緒に成長
しがちである。構造体に二酸化シリコンが多量に蒸着さ
れるにつれて、導体間の空隙中に完全に蒸着される前
に、角部同士が接触を起こし易い。第3図に示されるよ
うに、このような現象が起こると、ボイド29が形成され
ることがある。ボイド29が形成されなかったとしても、
対向する垂直壁からの蒸着二酸化シリコンの合併によ
り、不連続部分または“シーム"34が必ず存在する。第
3図の蒸着二酸化シリコン33のこのような欠陥は二酸化
シリコンの絶縁特性に“むら”を生じ、更に、二酸化シ
リコン層の不均一エッチング部分を構成する。集積回路
の仕上げ処理中に、このような欠陥部分に望ましからざ
る破壊が起こることがある。この問題は蒸着二酸化シリ
コンの膜厚が隣接する導体間の分離間隔の1/2よりも大
きい場合に起こりやすいことが認められる。
の水平面の蒸着に有利なプラズマ蒸着法を工夫すること
により解決される。第4図に示されるように、この蒸着
法によれば、対向する垂直側壁36および37が全く接触す
ることなく、極めて厚い二酸化シリコン層35を蒸着する
ことができる。水平面に優先的に蒸着する場合、層は、
水平方向の蒸着膜厚は殆ど増大することなく、垂直方向
に向かって段々に厚くなる。漸進的蒸着は一方向に向か
って優先的に起こるので、通常の相似形または“等方
性”二酸化シリコン蒸着を特徴とするような全方向に概
ね均等に蒸着する形態と異なり、本発明の蒸着形態を二
酸化シリコンの“異方性”蒸着と呼ぶ。
囲気中に二酸化シリコン蒸着を阻害するガスを供給し、
(2)基板の水平面から前記阻害ガスを優先的に除去す
るのに十分に高い高周波出力をプラズマ中で使用するこ
とにより達成される。また、雰囲気中のシリコン源は分
子であることが好ましい。この分子は高表面易動度また
は高表面拡散性を有し、これにより、阻害ガス分子の衝
撃除去により利用可能な水平面上の表面部位に即座に拡
散することができる。この目的にとって、シリコン源と
してのTEOSは申し分のない挙動を示すことが発見され
た。アンモニア(NH3)またはフッ化窒素(NF3)は阻害
ガスとして機能することが発見された。しかし、その他
の阻害ガスも同様に機能するものと思われる。また、NH
3およびNF3は蒸着表面に強力に吸着し、その結果、垂直
面に“粘着”し、該垂直面にSiO2の蒸着量を減少させる
ので好ましい。NF3は反応性が高すぎるという欠点を有
するので、取り扱いにくい。TEOSはシリコン源であるば
かりか、酸素源としても使用できるが、高品質のSiO2を
得るには、別の酸素源を使用することが好ましい。
コン層42はCVDによりシリコンウエハ43上の蒸着され
る。SiO2蒸着が行われた後の基板の水平面は、金属導体
40の水平面39とCVD二酸化シリコン42の水平面41であ
る。二酸化シリコン35の蒸着中、NH3分子は二酸化シリ
コン蒸着を起こす反応を阻害するのに役立つ。しかし、
100W以上の高RF出力の場合、垂直面44よりも水平面39お
よび41においてプラズマからの分子の一層活発な衝突が
起こる。これは、基板から延びる電界線が概ね垂直方向
に延びるためである。比較的高いRF電力の場合、衝突イ
オンおよび分子の数およびエネルギーの両方に関して、
垂直面よりも水平面で一層活発な衝突が起こる。その結
果、垂直面よりも水平面でNH3分子の低表面密度が生じ
る。TEOS分子は迅速に移動し、水平面上の有効部位を占
め、そして、反応し、SiO2を形成する。
が、2対1よりも大きな蒸着比が極めて容易に得られる
ことが発見された。第4図に示される蒸着の後、蒸着二
酸化シリコンの上面は、点線45で示される水平レベルま
でエッチングするか、または研磨することもできる。こ
のようにした場合、垂直端面44の付近にも拘らず、残り
の二酸化シリコンにはボイドおよびシームが全く存在し
ない。その結果、新たなSiO2面は第2の導体層のための
絶縁および支持層となることができる。
明で使用する現に好ましい方法は、導体を研磨処理の
“停止層”として使用することにより、蒸着層35を導体
の最上面と同じ水平レベルにまで研磨することである。
その後、第2の蒸着二酸化シリコン層47を導体40および
二酸化シリコン層35の平坦上面上に形成し、そして、層
47の形成完了後、第2の導体層を形成する。公知なよう
に、エッチングを使用し、蒸着層35の上面を平坦化また
は平面化することもできる。
テリアル社の“プレシジョン5000システム”と呼ばれる
公知の一般的なタイプの第1図で示されるような反応装
置10を使用した。反応装置中の圧力は9Torrであり、電
極11と電極12との間の間隔は200ミルであり、ウエハは
第1図に示されるように、接地電極上に配置し、そし
て、390℃にまで加熱した。TEOSは、34℃の液状TEOSを
有するTEOSバブラー16からヘリウム300sccmを流すこと
により導入した。酸素は300sccmの流量で導入した。電
極12は図示されているように、350WのRF出力で13.56MHz
で駆動した。各ウエハ15のサイズは直径5インチであっ
た。
平面上の蒸着二酸化シリコンの膜厚(“b")対垂直面上
の蒸着二酸化シリコンの膜厚(“s")の比は2.336(す
なわち、b/s=2.336)であった。NH3を100sccmで流入し
た場合、b/s比は2.336あった。このことは、アンモニア
濃度の増大は膜厚の比を殆ど変化させないことを意味す
る。NF320sccmの場合、b/s比は2.476であった。形成さ
れたSiO2膜の吸光度および屈折率などについて様々なテ
ストを行い、本発明により形成された蒸着SiO2膜の品質
は集積回路用として中し分のないことが確認された。し
かし、このようなテストはNH3により形成された膜のほ
うが、NF3により形成された膜よりも優れていることを
示唆した。NF3は比較的有害な物質であるという点から
すれば、NF3が若干大きなb/s比を与えたとしても、殆ど
の場合について、NH3のほうが優れた阻害ガスであるこ
とを前記テストは示唆している。
る、NF3またはNH3以外の物質も発見できるであろう。
ために説明されたものである。当業者に明らかなよう
に、その他の高周波プラズマ蒸着装置も使用できるであ
ろう。その他、本発明にもとることなく本発明に対して
様々な実施態様または改変が為し得ることは当業者に明
らかである。
び酸素源を含む雰囲気中で基板を高周波プラズマに暴露
することにより基板上に二酸化シリコンを蒸着する際
に、基板表面に二酸化シリコンが蒸着するのを阻害する
阻害ガスを雰囲気中に導入する。この阻害ガスの存在に
より、二酸化シリコンは水平面に優先的に蒸着し、そし
て、主に垂直方向に向かって成長する。垂直面には比較
的少ししか蒸着せず、また、水平方向には比較的少しし
か成長しないので、2つの互いに近接した垂直壁が“一
緒に成長する”ことによりボイドまたはシームのような
欠陥が発生する可能性は低くなる。
使用することができるプラズマ蒸着反応装置の模式的断
面図である。 第2図および第3図は従来技術により形成された二酸化
シリコン膜の模式的断面図である。 第4図および第5図は本発明の一実施例において本発明
により形成された二酸化シリコン膜の模式的断面図であ
る。
Claims (16)
- 【請求項1】シリコン源および酸素源を含む雰囲気中で
基板を高周波プラズマに暴露することにより水平面およ
び垂直面を有する基板上に二酸化シリコンを蒸着するこ
とからなる集積回路素子の製造方法において、 基板表面に二酸化シリコンが蒸着するのを阻害する阻害
ガスを雰囲気中に導入し、 雰囲気に100W以上の高周波出力をかけることにより高周
波プラズマを発生させ、これにより、基板の垂直面より
も基板の水平面における阻害ガスの密度を低下させ、斯
くして、水平面における優先的な二酸化シリコン蒸着を
促進することを特徴とする集積回路素子の製造方法。 - 【請求項2】シリコン源はテトラエトキシシランからな
ることを特徴とする請求項1の集積回路素子の製造方
法。 - 【請求項3】阻害ガスはNH3からなることを特徴とする
請求項1の集積回路素子の製造方法。 - 【請求項4】阻害ガスはNF3からなることを特徴とする
請求項1の集積回路素子の製造方法。 - 【請求項5】雰囲気は酸素と不活性ガスを含むことを特
徴とする請求項2の集積回路素子の製造方法。 - 【請求項6】高周波プラズマは平行な第1の電極と第2
の電極により発生され、第1の電極は高周波電源に接続
されており、第2の電極は接地されており、そして、基
板は電極のうちの一方に支持されており、 阻害ガスは基板に強力に吸着するガスであることを特徴
とする請求項2の集積回路素子の製造方法。 - 【請求項7】阻害ガスはNH3からなることを特徴とする
請求項6の集積回路素子の製造方法。 - 【請求項8】阻害ガスはNF3からなることを特徴とする
請求項6の集積回路素子の製造方法。 - 【請求項9】半導体基板上に第1の金属導体パターンを
形成し、該基板を2個の電極を有する高周波反応装置の
一方の電極上に配置し、該反応装置内にテトラエトキシ
シラン含有雰囲気を導入し、反応装置の一方の電極を高
周波電力で励起し、基板上に二酸化シリコンを蒸着させ
ることからなる集積回路の製造方法において、 励起電極は100W以上の高周波電力で励起され、 雰囲気は基板上に二酸化シリコンが蒸着するのを阻害す
るガスを含有していることを特徴とする集積回路の製造
方法。 - 【請求項10】阻害ガスはNF3およびNH3からなる群から
選択されることを特徴とする請求項9の集積回路の製造
方法。 - 【請求項11】雰囲気は更に酸素を含有していることを
特徴とする請求項10の集積回路の製造方法。 - 【請求項12】2個の高周波電極のうちの一方の電極は
高周波エネルギーにより励起され、2個の高周波電極の
うちの他方の電極は接地され、そして、基板は第2の電
極上に載置されることを特徴とする請求項11の集積回路
の製造方法。 - 【請求項13】二酸化シリコンは、第1の金属導体パタ
ーンの2個の互いに隣接する導体の分離間隔の半分を超
える厚さにまで蒸着されることを特徴とする請求項9の
集積回路の製造方法。 - 【請求項14】第2の金属導体パターンは蒸着二酸化シ
リコン上に形成されることを特徴とする請求項12の集積
回路の製造方法。 - 【請求項15】二酸化シリコンの上面を平坦化し、そし
て、その後、第2の金属導体パターンを前記平坦化二酸
化シリコン表面上に形成することを特徴とする請求項13
の集積回路の製造方法。 - 【請求項16】平坦化後、二酸化シリコンの第2の被膜
を該平坦化二酸化シリコン上に蒸着し、そして、その
後、第2の金属導体パターンを二酸化シリコンの第2の
被膜上に形成することを特徴とする請求項15の集積回路
の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/386,650 US5013691A (en) | 1989-07-31 | 1989-07-31 | Anisotropic deposition of silicon dioxide |
US386650 | 1989-07-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0376224A JPH0376224A (ja) | 1991-04-02 |
JPH06103692B2 true JPH06103692B2 (ja) | 1994-12-14 |
Family
ID=23526482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2199367A Expired - Lifetime JPH06103692B2 (ja) | 1989-07-31 | 1990-07-30 | 集積回路素子の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5013691A (ja) |
EP (1) | EP0411795B1 (ja) |
JP (1) | JPH06103692B2 (ja) |
KR (1) | KR0160958B1 (ja) |
DE (1) | DE69022667T2 (ja) |
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JPS57211734A (en) * | 1981-06-24 | 1982-12-25 | Toshiba Corp | Manufacture of semiconductor device |
JPS6163020A (ja) * | 1984-09-04 | 1986-04-01 | Agency Of Ind Science & Technol | 薄膜形成方法 |
US4845054A (en) * | 1985-06-14 | 1989-07-04 | Focus Semiconductor Systems, Inc. | Low temperature chemical vapor deposition of silicon dioxide films |
EP0208459B1 (en) * | 1985-06-24 | 1992-03-18 | Silicon Valley Group, Inc. | Process for the chemical vapour deposition of a thin film of oxide on a silicon wafer |
US4690746A (en) * | 1986-02-24 | 1987-09-01 | Genus, Inc. | Interlayer dielectric process |
EP0244848A1 (de) * | 1986-05-07 | 1987-11-11 | Siemens Aktiengesellschaft | Verfahren zum Planarisieren von anorganischen, als Zwischenschichten bei Mehrlagenmetallisierung verwendbaren Isolationsschichten |
JPS6362238A (ja) * | 1986-09-02 | 1988-03-18 | Toshiba Corp | 薄膜堆積方法 |
JPS6350318Y2 (ja) * | 1987-10-20 | 1988-12-23 | ||
JPH01152631A (ja) * | 1987-12-09 | 1989-06-15 | Nec Corp | S1xOyNz絶縁膜の形成方法 |
JP2654790B2 (ja) * | 1988-02-26 | 1997-09-17 | 富士通株式会社 | 気相成長法 |
JPH01243553A (ja) * | 1988-03-25 | 1989-09-28 | Seiko Epson Corp | 半導体装置の製造方法 |
US4894352A (en) * | 1988-10-26 | 1990-01-16 | Texas Instruments Inc. | Deposition of silicon-containing films using organosilicon compounds and nitrogen trifluoride |
EP0366013A3 (en) * | 1988-10-27 | 1990-06-27 | Texas Instruments Incorporated | Selective dielectric deposition on horizontal features of an integrated circuit subassembly |
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- 1989-07-31 US US07/386,650 patent/US5013691A/en not_active Expired - Lifetime
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- 1990-07-20 EP EP90307969A patent/EP0411795B1/en not_active Expired - Lifetime
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- 1990-07-25 KR KR1019900011297A patent/KR0160958B1/ko not_active IP Right Cessation
- 1990-07-30 JP JP2199367A patent/JPH06103692B2/ja not_active Expired - Lifetime
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EP0411795B1 (en) | 1995-09-27 |
KR0160958B1 (ko) | 1999-10-01 |
EP0411795A1 (en) | 1991-02-06 |
DE69022667T2 (de) | 1996-05-09 |
KR910003753A (ko) | 1991-02-28 |
DE69022667D1 (de) | 1995-11-02 |
JPH0376224A (ja) | 1991-04-02 |
US5013691A (en) | 1991-05-07 |
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