JP2013243381A - 金属ゲートとストレッサーを有するゲルマニウムフィンｆｅｔ - Google Patents

金属ゲートとストレッサーを有するゲルマニウムフィンｆｅｔ Download PDF

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JP2013243381A
JP2013243381A JP2013144426A JP2013144426A JP2013243381A JP 2013243381 A JP2013243381 A JP 2013243381A JP 2013144426 A JP2013144426 A JP 2013144426A JP 2013144426 A JP2013144426 A JP 2013144426A JP 2013243381 A JP2013243381 A JP 2013243381A
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germanium
fin
gate electrode
fins
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Chih-Chieh Yeh
致▲かい▼ 葉
Chih-Sheng Chang
智勝 張
Hsingjen Wann
幸仁 萬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

【課題】金属ゲートとストレッサーを有するゲルマニウムフィンFETを提供する。
【解決手段】半導体基板上に直接設けられた複数の第一ゲルマニウムフィンであって、第一ゲルマニウムフィン１２４の上面と側壁上の第一ゲート誘電体１３２、及び、第一ゲート誘電体上の第一ゲート電極１３４からなるn型フィンFET１５０と、半導体基板上に直接設けられた複数の第二ゲルマニウムフィンであって、第二ゲルマニウムフィン２２４は互いに物理的に分離し、かつ、互いに電気的に接続すること、第二ゲルマニウムフィンの上面と側壁上の第二ゲート誘電体２３２、及び、第二ゲート誘電体上の第二ゲート電極２３４からなるp型FinFET２５０とを備え、第一ゲート電極と第二ゲート電極は、4.25eVと4.4eV間の仕事関数を有する同一材料で形成される。
【選択図】図１０

Description

本発明は、集積回路に関するものであって、特に、フィン電界効果トランジスタ(FinFET)の構造とその形成方法に関するものである。
金属酸化膜半導体(MOS)トランジスタの速度は、MOSトランジスタの駆動電流と密接な関係があり、駆動電流は、更に、電荷の移動度とも関係がある。例えば、チャネル領域中の電子移動度（electron mobility）が高い時、NMOSトランジスタは高い駆動電流を有し、チャネル領域中の正孔移動度（hole mobility）が高い時、PMOSトランジスタは高い駆動電流を有する。
ゲルマニウムは、一般的に知られた半導体材料である。ゲルマニウムの電子移動度と正孔移動度は、集積回路の形成に常用される半導体材料であるシリコンより高い(それぞれ、２．６倍と４倍)。よって、ゲルマニウムは集積回路を形成するための優れた材料である。ゲルマニウムの付加された有利な特徴は、ゲルマニウムの正孔移動度と電子移動度は、シリコンの応力感度（stress sensitivity）より大きいことである。例えば、図1は、ゲルマニウムとシリコンの正孔移動度を一軸圧縮応力（uni-axial compressive stresses）の関数として示す。注意すべきことは、圧縮応力の増加に伴い、ゲルマニウムの正孔移動度は、シリコンより速く増加することで、これは、ゲルマニウムベースのPMOS装置が、シリコンベースのPMOS装置よりも高い駆動電流を有する可能性が高いことを示す。同様に、図２は、ゲルマニウムとシリコンの電子移動度を一軸引張応力（tensile stresses）の関数として示す。注意すべきことは、引張応力の増加に伴い、ゲルマニウムの電子移動度は、シリコンより速く増加することで、これは、ゲルマニウムベースのNMOS装置が、シリコンベースのNMOS装置より高い駆動電流を有する可能性が高いことを示すことである。
しかしながら、ゲルマニウムは又、欠点を受ける。ゲルマニウムのバンドギャップは0.66 eVで、シリコンのバンドギャップ(1.12 eV)より小さい。これは、ゲルマニウムベースのMOS装置の基板電流漏れが高いことを意味する。加えて、ゲルマニウムの誘電率（dielectric constant）は16で、シリコンの誘電率(11.9)より大きい。従って、ゲルマニウムベースのMOS装置のドレイン誘導バリア低下（drain-induced barrier lowering(DIBL)）も、シリコンベースのMOS装置より高い。
本発明は、フィン電界効果トランジスタ(FinFET)の構造とその形成方法を提供し、上述の問題を改善することを目的とする。
実施例の一態様によれば、集積回路構造は、半導体基板上に直接設けられた複数の第一ゲルマニウムフィンであって、第一ゲルマニウムフィンは互いに物理的に分離し(separate)、かつ、互いに電気的に接続すること、第一ゲルマニウムフィンの上面と側壁上の第一ゲート誘電体、及び、第一ゲート誘電体上の第一ゲート電極からなることを備えたn型フィン電界効果トランジスタ（FinFET)と、半導体基板上に直接設けられた複数の第二ゲルマニウムフィンであって、第二ゲルマニウムフィンは互いに物理的に分離し、かつ、互いに電気的に接続すること、第二ゲルマニウムフィンの上面と側壁上の第二ゲート誘電体、及び、第二ゲート誘電体上の第二ゲート電極からなるp型FinFETであって、第一ゲート電極と第二ゲート電極は、4.25eVと4.4eV間の仕事関数（work function）を有する同一材料で形成され、かつ、第一ゲルマニウムフィンと第二ゲルマニウムフィンのゲルマニウム原子百分率は、50パーセントより大きいことと、半導体基板上に直接設けられた複数のダミーフィンからなるダミーフィン構造とを備えた。
他の実施例も開示される。
公知の問題が改善され、また、n型FinFETとp型FinFETの駆動電流が改善され、電流漏れも減少する。
ゲルマニウムとシリコンの正孔移動度を一軸圧縮応力の関数として示す。 ゲルマニウムとシリコンの電子移動度を一軸引張応力の関数として示す。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 実施例によるゲルマニウムベースのFinFET製造の中間段階の斜視図と断面図である。 マルチフィンFinFETの斜視図と断面図である。 マルチフィンFinFETの斜視図と断面図である。 マルチフィンFinFETの斜視図と断面図である。 ゲルマニウムのエネルギー帯を示す図である。
新規のフィン電界効果トランジスタ(FinFET)の実施例とその形成方法が提供される。実施例を形成する中間段階が説明される。実施例の変化も討論される。様々な図式と実施例で、同じ参照符号は同じ要素を示す。
図３を参照して、集積回路構造が形成される。集積回路構造は、基板20を含み、シリコン基板、ゲルマニウム基板、或いは、他の半導体材料からなる基板であってもよい。基板20はp型、或いは、n型不純物がドープされる。分離領域、例えば、シャロートレンチアイソレーション（浅溝）（shallow trench isolation、STI)領域22は、基板の20の中か上方に形成される。ゲルマニウムフィン124と224が、STI領域22の上面の上に形成される。代表的実施例において、隣接するSTI領域22間の基板20の上部分を凹陥させ(recess)、凹部を形成し、凹部にゲルマニウムを再成長することにより、ゲルマニウムフィン124と224が形成される。その後、STI領域22の上部分は除去してもよいが、STI領域22の下部分は除去されず、隣接するSTI領域22間の再成長ゲルマニウムの上部分がゲルマニウムフィンになる。ゲルマニウムフィン124と224は、例えば、約50パーセントより大きいゲルマニウム原子百分率を有してもよい。実施例において、フィン124と224は、純ゲルマニウムで形成される。別の実施例において、フィン124と224は、シリコンゲルマニウムで形成される。
ゲルマニウムフィン124と224はチャネルドーピング（channel doping）を有してもよい。ゲルマニウムフィン124はp型不純物、例えば、ボロン（boron）がドープされ、ゲルマニウムフィン224はn型不純物、例えば、リンがドープされてもよい。ゲルマニウムフィン124と224のチャネルドーピングは、約5E17/cm3より小さいか、或いは、約1E17/cm3と同じくらい低くてよい。代表的実施例において、ゲルマニウムフィン124と224のアスペクト比(高さH対幅Wの比率)は、約1より大きいか、さらに約5以上であってもよい。基板20は、NMOS装置領域100中の一部とPMOS装置領域200中の一部を含む。ゲルマニウムフィン124と224は、それぞれ、NMOS装置領域100とPMOS装置領域200中にある。
図４を参照して、ゲート誘電体層32とゲート電極層34が、NMOS装置領域100とPMOS装置領域200中の双方と、ゲルマニウムフィン124と224上に蒸着される。実施例において、ゲート誘電体層32は、高k誘電材料で形成される。高k誘電材料は、約4.0より大きいか、さらに約7.0以上のk値を有してもよく、アルミニウム含有の誘電材料（Al2O3、HfAlO、HfAlON、AlZrO等）、Hf含有の材料（HfO2、HfSiOx、HfAlOx、HfZrSiOx、HfSiON等）、及び/又は、LaAlO3とZrO2等の他の材料を含んでもよい。
ゲート電極層34はゲート誘電体層32上に形成され、金属を含んでもよい。ゲート電極層34は、ゲルマニウムの伝導バンド（conduction band）(4 eV)と価電子帯（valance band）(4.66 eV)の固有レベル(中間レベル、約4.33 eV)に近い仕事関数を有することができる。実施例において、ゲート電極層34の仕事関数は、約4.15 eV〜4.5 eVか、或いは、さらに約4.25 eV〜約4.4 eVである。ゲート電極層34の代表的材料の例として、TixNy、TaxNy、Al、TaxCy、Pt、その複合層、及び、その組み合わせがあり、xとyは正値である。
ゲート電極層34とゲート誘電体層32は、その後、パターン化されて、図５で示されるように、ゲートスタックを形成する。NMOS装置領域100のゲートスタックは、ゲート電極134とゲート誘電体132を含む。PMOS装置領域200のゲートスタックは、ゲート電極234とゲート誘電体232を含む。よって、ゲルマニウムフィン124と224は、それぞれ、ゲートスタックにより被覆されない部分を有する。
図６を参照して、ゲートスペーサ136と236が形成されてもよい。ゲート誘電体132と232、ゲート電極134と234、及び、ゲートスペーサ136と236により被覆されないゲルマニウムフィン124と224の露出部分は、その後、除去され(凹陥する)るが、ゲルマニウムフィン124と224の被覆部分は除去されない。除去はドライエッチングにより実行してもよい。フィン124と224の除去部分により残された空間は、それぞれ、凹部140と240と称する。凹部140と240は、STI領域22の上面と同じ高さの底面を有してもよい。あるいは又、凹部140と240の底面は、図６で示されるように、STI領域22の上面35より低くてもよい。
図７(及び、後続の図８と９)は、図６に示される構造の断面図を示し、図６の線7-7と交差する垂直平面で、NMOS装置領域100の断面図が得られ、線7'−7' と交差する垂直平面で、PMOS装置領域200の断面図が得られる。注意すべきことは、図７と後続の図８、図９は、NMOS装置領域100とPMOS装置200断面図は同一平面にあるが、実際は、異なる平面にあってもよいことである。
次に、図８で示されるように、PMOS領域200が、例えば、フォトレジスト241により被覆され、選択的エピタキシャル成長（selective epitaxial growth、SEG)により、凹部140にエピタキシャル成長され、ソースとドレイン(以下、ソース/ドレインと称す)領域142を得る。ソース/ドレイン領域142は、ソース/ドレインストレッサー142とも称され、ゲルマニウムフィン124より小さい格子定数（lattice constant）を有してもよい。代表的実施例において、ソース/ドレイン領域142はSiGeからなり、プラズマ化学気相成長法（plasma enhanced chemical vapor deposition、PECVD)、或いは、他の常用の方法を用いて形成される。前駆体（precursor）は、SiH4等のSi含有ガスとGeH4等のGe含有ガス、からなってもよく、Si含有ガスとGe含有ガスの分圧（partial pressures）が調整されて、ゲルマニウム対シリコンの原子比率を変更することができる。実施例において、得られたソース/ドレインストレッサー142は、約20〜60％の原子百分率のシリコンを有する。別の実施例において、ソース/ドレインストレッサー142は、シリコン炭素（silicon carbon、SiC)、或いは、炭素を含まないシリコン、及び/又は、ゲルマニウムを加えたシリコンからなってもよい。エピタキシャル成長進行時、リン、及び/又は、砒素（arsenic）等のN型不純物がその場でドープ（in-situ doped）される。ソース/ドレイン領域142の格子定数がゲルマニウムフィン124の格子定数より小さいので、ソース/ドレイン領域142は、ゲルマニウムフィン124に対し引張圧力を加え、n型FinFET150のチャネル領域を形成する。ソース/ドレイン領域142のエピタキシャル成長後、フォトレジスト241が除去される。
図９に示されるように、NMOS 装置領域100は、例えば、フォトレジスト141により被覆される。ソース/ドレインストレッサー242とも称されるソース/ドレイン領域242が、凹部240でエピタキシャル成長する。ソース/ドレイン領域242は、ゲルマニウムフィン224より大きい格子定数を有してもよい。再度、ソース/ドレイン領域242はPECVDを用いて形成してもよい。実施例において、ソース/ドレイン領域242はGeSnからなる。別の実施例において、ソース/ドレイン領域242は、III族とV族材料からなる化合物半導体材料(以下、III-V族半導体材料と称す)、例えば、InGaAs、InP、GaSb、InAs、AlSb、InSb等からなる。ソース/ドレイン領域242の格子定数がゲルマニウムフィン224より高いので、ソース/ドレイン領域242は、ゲルマニウムフィン224に圧縮応力を加え、結果として生じるPMOS FinFET 250のチャネル領域を形成する。ソース/ドレイン領域242のエピタキシャル成長後、フォトレジスト141が除去される。
ソース/ドレイン領域142と242を形成するエピタキシャルプロセスの間、進行中のエピタキシャルプロセスに伴って、それぞれ、n型不純物(リン等)とp型不純物(ボロン等)がドープされてもよい。不純物濃度は、約5x1020/cm3〜1x1021/cm3である。別の実施例において、p型とn型不純物がドープされず、ソース/ドレイン領域142と242のドーピングは、ソース/ドレイン領域142と242の形成後に実行される。
次に、ソース/ドレイン領域142と242と金属を反応させることにより、シリサイド/ゲルマニウム（silicide/germanide）領域（図示しない）が、ソース/ドレイン領域142と242上に形成され、接触抵抗を減少させることができる。シリサイド/ゲルマニウム領域の形成の詳細は当分野にて既知であり、ここでは繰り返さない。上述のプロセスによって、n型FinFET150とPMOS FinFET 250が形成される。
上記に論じられた実施例において、単一のフィンFinFETが論じられた。あるいは又、本発明の概念は、マルチ（多数）フィンのFinFETに適用される。図１０〜１２は、マルチフィンFinFETの断面図と斜視図を示す。特に定めのない限り、同じ参照符号は同じ要素を示すのに用いられる。よって、図１０〜１２で示される要素の材料はここで繰り返さない。10は、n型FinFET150、PMOS FinFET250、ダミーフィン324を含むダミーフィン構造350の集積回路の断面図を示し、基板320上に形成される。基板320は、ゲルマニウム基板かシリコン基板とすることができる。N型FinFET150はpウェルに形成され、マルチゲルマニウムフィン124を含む。ゲート電極134はマルチゲルマニウムフィン124上に形成され、よって、マルチゲルマニウムフィン124は、単一のn型FinFET150のフィンになる。ゲート誘電体132は、ゲルマニウムフィン124とゲート電極134間に形成される。同様に、PMOSFinFET250はnウェルに形成され、マルチゲルマニウムフィン224を含む。ゲート電極234はマルチゲルマニウムフィン224上に形成され、よって、マルチゲルマニウムフィン224は、単一PMOS FinFET250のフィンになる。ゲート誘電体232は、ゲルマニウムフィン124とゲート電極134間に形成される。加えて、ダミーフィンは又、いかなるFinFETの形成にも用いられないが、ゲルマニウムフィン124と224の形成において、パターンローディング効果を減少させるために形成される。
マルチフィンが単一FinFETに用いられる時、FinFETの駆動電流は更に増加する。ゲルマニウムとシリコン間には格子不整合（lattice mismatch）があるので、より大きいフィン幅のフィンからよりも、より小さいフィン幅のフィンから成長されたゲルマニウムエピタキシー層のほうが、（より低い欠陥密度の）高い品質を達成することがより容易である。
図１１と１２はFinFETの斜視図である。図１１中の同じ要素は、図１０に見つけることができる。FinFETは、n型FinFET150かPMOS FinFET250かのどちらかであってよく、よって、150/250で示される。図１１において、ソース/ドレイン領域(ストレッサー)142/242は、ゲルマニウムフィン124/224から成長して得られ、且つ、不連続部位（discrete regions）である。図１２において、ゲルマニウムフィン124/224から成長して得られたソース/ドレイン領域(ストレッサー)142/242は互いに合併（一体化）する。
図１３は、ゲルマニウムのエネルギー帯（energy bands）を示す。注意すべきことは、ゲルマニウムは、4 eVに等しい伝導バンドEc、4.66 eVに等しい価電子帯（valence band）Ev、及び、4.33 eVに等しい固有レベル（intrinsic level）Ei((Ec+Ev)/2)を有することである。これにより、固有レベルEiと伝導バンドEcは、約330 mVに等しいエネルギー差を有し、固有レベルEiと価電子帯Evは、約330 mVに等しいエネルギー差を有する。330 mVのエネルギー差が用いられて、n型ゲルマニウムフィンFETとp型ゲルマニウムフィンFETの金属ゲートの形成を単純化することができる。ゲルマニウムフィンFETにおいて、完全に空乏化したチャネルは、スレショルド（しきい値）電圧Vtの減少をもたらすので、バンド端（band-edge）の仕事関数はもはや必要とされない。代わりに、中間バンドギャップ付近の（near-mid-bandgap）の仕事関数が、スレショルド電圧Vtを目標値に正確にシフトするため必要となる。よって、ゲルマニウムベースのFinFETは、n型ゲルマニウムフィンFETとp型ゲルマニウムフィンFET両者の金属ゲートの仕事関数が、約4.33 eVの固有レベルに近づく時、たとえ同じ金属材料が、n型FinFETとp型FinFETのゲートを形成するため用いられたとしても、n型FinFETとp型FinFETの仕事関数を最適化する要件はそれらいずれをも満たすことができる。
討論された有利な特徴に加え、本発明の実施例は、数個の他の有利な特徴がある。ゲルマニウムベースのFinFETの形成によって、ゲルマニウムの電子移動度と正孔移動度が高いので、n型FinFETとp型FinFETの駆動電流を改善することができる。平面MOS装置と比較すると、FinFETの接合面積の減少により、電流漏れも減少することができる。
本発明では好ましい実施例を前述の通り開示したが、これらは決して本発明に限定するものではなく、当該技術を熟知する者なら誰でも、本発明の精神と領域を脱しない範囲内で各種の変動や潤色を加えることができ、従って本発明の保護範囲は、特許請求の範囲で指定した内容を基準とする。
20 〜 基板
22 〜 シャロートレンチアイソレーション(STI)
32 〜 ゲート誘電層
34 〜 ゲート電極層
35 〜 STI22の上面
100 〜 NMOS素子
124、224 〜 ゲルマニウムフィン
132、232 〜 ゲート誘電層
134、234 〜 ゲート電極層
136、236 〜 ゲートスペーサ
140、240 〜 凹部
141、241 〜 フォトレジスト
142、242 〜 ソース/ドレイン領域
150 〜 NMOS FinFET
200 〜 PMOS素子
250 〜 PMOS FinFET
320 〜 基板
324 〜 ダミーフィン
350 〜 ダミーフィン構造
W 〜 ゲルマニウムフィンの幅
H 〜 ゲルマニウムフィンの高さ

Claims (7)

  1. 半導体基板と、
    前記半導体基板上に直接設けられた複数の第一ゲルマニウムフィンであって、前記第一ゲルマニウムフィンは互いに物理的に分離し(separate)、かつ、互いに電気的に接続することを特徴とすること、前記第一ゲルマニウムフィンの上面と側壁上の第一ゲート誘電体、及び、前記第一ゲート誘電体上の第一ゲート電極からなるn型フィン電界効果トランジスタ（FinFET)と、
    前記半導体基板上に直接設けられた複数の第二ゲルマニウムフィンであって、前記第二ゲルマニウムフィンは互いに物理的に分離し、かつ、互いに電気的に接続することを特徴とすること、前記第二ゲルマニウムフィンの上面と側壁上の第二ゲート誘電体、及び、前記第二ゲート誘電体上の第二ゲート電極からなるp型FinFETであって、前記第一ゲート電極と前記第二ゲート電極は、4.25eVと4.4eV間の仕事関数（work function）を有する同一材料で形成され、かつ、前記第一ゲルマニウムフィンと前記第二ゲルマニウムフィンのゲルマニウム原子百分率は、50パーセントより大きいことを特徴とすることと、
    前記半導体基板上に直接設けられた複数のダミーフィンからなるダミーフィン構造と、
    を備えた集積回路構造。
  2. 前記第一ゲート電極と前記第二ゲート電極は、金属ゲート電極であることを特徴とする請求項１に記載の集積回路構造。
  3. 前記n型FinFETは、更に、シリコン炭素からなるソース/ドレイン領域を有することを特徴とする請求項１に記載の集積回路構造。
  4. 前記n型FinFETは、更に、ソース/ドレイン領域を有し、前記ソース/ドレイン領域中のゲルマニウム原子百分率は、前記第一ゲルマニウムフィン中のゲルマニウム原子百分率より低いことを特徴とする請求項１に記載の集積回路構造。
  5. 前記p型FinFETは、更に、ゲルマニウム錫（GeSn）からなるソース/ドレイン領域を有することを特徴とする請求項１に記載の集積回路構造。
  6. 前記p型FinFETは、更に、III族とV族材料からなる化合物半導体材料(III-V族半導体材料)からなるソース/ドレイン領域を有し、前記III-V族半導体材料の格子定数は、前記第二ゲルマニウムフィンより大きいことを特徴とする請求項１に記載の集積回路構造。
  7. 半導体基板と、
    前記半導体基板上に直接設けられた複数の第一ゲルマニウムフィンであって、前記第一ゲルマニウムフィンは互いに物理的に分離し、かつ、互いに電気的に接続することを特徴とすること、前記第一ゲルマニウムフィンの上面と側壁上の第一ゲート誘電体、及び、前記第一ゲート誘電体上の第一ゲート電極、及び、前記第一ゲート電極に隣接する第一ソース/ドレイン領域であって、この第一ソース/ドレイン領域は前記第一ゲルマニウムフィンの格子定数よりも小さい第一格子定数を有する第一エピタキシャル領域からなることを特徴とすること、を備えたn型フィン電界効果トランジスタ（FinFET)と、
    前記半導体基板上に直接設けられた複数の第二ゲルマニウムフィンであって、前記第二ゲルマニウムフィンは互いに物理的に分離し、かつ、互いに電気的に接続することを特徴とすること、前記第二ゲルマニウムフィンの上面と側壁上の第二ゲート誘電体、前記第二ゲート誘電体上の第二ゲート電極であって、前記第一ゲート電極と前記第二ゲート電極は、4.25eVと4.4eV間の仕事関数（work function）を有することを特徴とすること、及び、前記第二ゲート電極に隣接する第二ソース/ドレイン領域からなるp型FinFETであって、この第二ソース/ドレイン領域は、前記第二ゲルマニウムフィンの格子定数よりも大きい第二格子定数を有する第二エピタキシャル領域を備え、かつ、前記第一ゲルマニウムフィンと前記第二ゲルマニウムフィンのゲルマニウム原子百分率は、50パーセントより大きいことを特徴とすることと、
    前記半導体基板上に直接設けられた複数のダミーフィンからなるダミーフィン構造と、
    を備えた集積回路構造。
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KR102158961B1 (ko) * 2014-05-13 2020-09-24 삼성전자 주식회사 반도체 장치 및 그 제조 방법
WO2016064765A1 (en) * 2014-10-20 2016-04-28 Applied Materials, Inc. Methods and apparatus for forming horizontal gate all around device structures
JP2020521319A (ja) * 2017-05-23 2020-07-16 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Ｖｆｅｔアーキテクチャ内の超長チャネル・デバイス
JP7018963B2 (ja) 2017-05-23 2022-02-14 インターナショナル・ビジネス・マシーンズ・コーポレーション Ｖｆｅｔアーキテクチャ内の超長チャネル・デバイス

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CN102034866A (zh) 2011-04-27
US20110068407A1 (en) 2011-03-24
CN102034866B (zh) 2012-12-19
US9698060B2 (en) 2017-07-04
JP2011071517A (ja) 2011-04-07
TW201133793A (en) 2011-10-01
KR20110033033A (ko) 2011-03-30
US9245805B2 (en) 2016-01-26
TWI485842B (zh) 2015-05-21
US20160155668A1 (en) 2016-06-02

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