JP2020521319A - Vfetアーキテクチャ内の超長チャネル・デバイス - Google Patents
Vfetアーキテクチャ内の超長チャネル・デバイス Download PDFInfo
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- JP2020521319A JP2020521319A JP2019563201A JP2019563201A JP2020521319A JP 2020521319 A JP2020521319 A JP 2020521319A JP 2019563201 A JP2019563201 A JP 2019563201A JP 2019563201 A JP2019563201 A JP 2019563201A JP 2020521319 A JP2020521319 A JP 2020521319A
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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Abstract
Description
Claims (23)
- 半導体デバイスを形成する方法であって、
基板上に1対の半導体フィンを形成することと、
前記基板上の前記半導体フィンの間に半導体ピラーを形成することと、
前記半導体フィンの全部の下と前記半導体ピラーの一部の下とに延びる下部ドープ領域を形成することと、
前記半導体フィンと前記半導体ピラーとのチャネル領域の上に導電ゲートを形成することと
を含む方法。 - 前記半導体ピラーをドープすることをさらに含む、請求項1に記載の方法。
- 前記導電ゲートと前記半導体フィンおよび前記半導体ピラーとの間に厚い酸化物層を形成することをさらに含む、請求項1または2に記載の方法。
- 前記半導体ピラーを前記半導体フィンの表面より下方に陥凹化することをさらに含む、請求項1ないし3のいずれか一項に記載の方法。
- 前記導電ゲートと前記下部ドープ領域との間に下部スペーサを形成することをさらに含む、請求項1ないし4のいずれか一項に記載の方法。
- 前記導電ゲート上に上部スペーサを形成することをさらに含む、請求項1ないし5のいずれか一項に記載の方法。
- 前記半導体フィンの露出表面上に上部ドープ領域を形成することをさらに含む、請求項1ないし6のいずれか一項に記載の方法。
- 前記上部ドープ領域上に導電接点を形成することをさらに含む、請求項7に記載の方法。
- 前記導電ゲート上および前記半導体ピラーの上にゲート接点を形成することをさらに含む、請求項8に記載の方法。
- 前記半導体フィンの露出表面上にソース領域とドレイン領域とを形成することと、
前記導電ゲート上と前記半導体ピラーの上とに共用ゲート接点を形成することと
をさらに含む、請求項1ないし9のいずれか一項に記載の方法。 - 前記半導体ピラーの厚さが前記半導体フィンの厚さよりも厚い、請求項1ないし10のいずれか一項に記載の方法。
- 半導体デバイスを動作させる方法であって、
基板上の第2の半導体フィンに隣接した第1の半導体フィンと、
前記基板上の前記第1の半導体フィンと前記第2の半導体フィンとの間に形成された半導体ピラーと、
前記第1の半導体フィンと第2の半導体フィンと前記半導体ピラーとのチャネル領域の上に形成された導電ゲートと、
前記第1の半導体フィンの表面上に形成されたソース領域と、
前記第2の半導体フィンの表面上に形成されたドレイン領域と、を含む半導体デバイスを設けることと、
前記半導体ピラーの一部を経由して前記ソース領域から前記ドレイン領域まで電流を流すことと
を含む方法。 - 前記半導体ピラーは前記第1および第2の半導体フィンの表面より下方に陥凹化されている、請求項12に記載の方法。
- 前記半導体デバイスは、前記導電ゲート上と前記半導体ピラーの上とに形成された共用ゲート接点をさらに含む、請求項12または13に記載の方法。
- 前記半導体ピラーの厚さが前記第1および第2の半導体フィンの厚さよりも厚い、請求項12ないし14のいずれか一項に記載の方法。
- 半導体デバイスであって、
基板上に形成された1対の半導体フィンと、
前記基板上の前記半導体フィンの間に形成された半導体ピラーと、
前記半導体フィンの全部の下と前記半導体ピラーの一部の下とに延びる下部ドープ領域と、
前記半導体フィンと前記半導体ピラーとのチャネル領域の上に形成された導電ゲートと
を含む、半導体デバイス。 - 前記導電ゲートと前記半導体フィンとの間に形成された厚い酸化物層をさらに含む、請求項16に記載の半導体デバイス。
- 前記半導体ピラーは、前記半導体フィンの表面より下方に陥凹化されている、請求項16または17に記載の半導体デバイス。
- 前記導電ゲートと前記下部ドープ領域との間に下部スペーサをさらに含む、請求項16ないし18のいずれか一項に記載の半導体デバイス。
- 前記導電ゲート上の上部スペーサをさらに含む、請求項16ないし19のいずれか一項に記載の半導体デバイス。
- 前記1対の半導体フィンが第1の半導体フィンと第2の半導体フィンとを含み、
前記第1の半導体フィンの表面上に形成されたソース領域と、
前記第2の半導体フィンの表面上に形成されたドレイン領域と
をさらに含み、前記第2の半導体フィンが前記第1の半導体フィンに隣接している、請求項16ないし20のいずれか一項に記載の半導体デバイス。 - 前記厚い酸化物層は前記導電ゲートと前記半導体ピラーとの間にも形成されている、請求項17ないし21のいずれか一項に記載の半導体デバイス。
- 前記半導体ピラーの厚さは前記半導体フィンの厚さよりも厚い、請求項16ないし22のいずれか一項に記載の半導体デバイス。
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US15/813,523 US10424663B2 (en) | 2017-05-23 | 2017-11-15 | Super long channel device within VFET architecture |
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US10818753B2 (en) * | 2019-03-18 | 2020-10-27 | International Business Machines Corporation | VTFET having a V-shaped groove at the top junction region |
US11069784B2 (en) * | 2019-05-17 | 2021-07-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
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CN110637367B (zh) | 2023-04-04 |
US20180342615A1 (en) | 2018-11-29 |
US10833190B2 (en) | 2020-11-10 |
DE112018001590B4 (de) | 2022-04-21 |
US20190341490A1 (en) | 2019-11-07 |
JP7018963B2 (ja) | 2022-02-14 |
US10424663B2 (en) | 2019-09-24 |
GB2577417A (en) | 2020-03-25 |
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