CN105097806A - 一种半导体器件和电子装置 - Google Patents

一种半导体器件和电子装置 Download PDF

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CN105097806A
CN105097806A CN201410167025.0A CN201410167025A CN105097806A CN 105097806 A CN105097806 A CN 105097806A CN 201410167025 A CN201410167025 A CN 201410167025A CN 105097806 A CN105097806 A CN 105097806A
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semiconductor device
stressor layers
virtual device
core devices
semiconductor
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丁士成
傅丰华
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明提供一种半导体器件和电子装置，涉及半导体技术领域。本发明的半导体器件，包括半导体衬底以及位于半导体衬底上的核心器件和虚拟器件；其中，所述核心器件包括位于半导体衬底上的栅极以及位于所述栅极两侧的应力层，所述虚拟器件包括位于半导体衬底上的栅极以及位于所述栅极两侧的应力层，并且，当所述虚拟器件与所述核心器件的类型相同时，所述虚拟器件的应力层与所述核心器件的应力层的材料相同。本发明的半导体器件由于所包括的虚拟器件与核心器件一样具有应力层，因此可以保证位于应力层之上的膜层具有良好的交叠表现，可以提高半导体器件的良率和可靠性。本发明的电子装置，由于使用了上述半导体器件，因而同样具有上述优点。

Description

一种半导体器件和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件和电子装置。
背景技术
在半导体技术领域中，在制造半导体器件的过程中，往往需要在半导体器件上制作虚拟(dummy)器件，以使需要匹配的器件周围环境保持一致，从而降低失配。
通过嵌入式锗硅(e-SiGe)实现迁移率提升的技术在PMOS器件中被广泛应用将近10年左右。当工艺节点从28nm发展到22nm以下，在高k金属栅极的技术方案中，嵌入式碳硅技术(SiC)在NMOS中得到了较为广泛的应用。
关于应力层分布的虚拟图案(Dummypattern)的设计在22nm及以下工艺节点中至关重要。不恰当的虚拟应力层的设计，将导致在后续工艺中出现差的交叠表现、不友好的集成工艺以及不可靠的SPICE模型(即，电路仿真模型)。
然而，在现有技术中，虚拟器件的结构如图1所示，包括有源区100和位于有源区100上的栅极101。该虚拟器件与具有抬升的应力层的晶体管(PMOS具有抬升的锗硅层，NMOS具有抬升的碳硅层)相比，外在形貌存在很大的差异，造成在半导体器件的制造过程中，在后续工艺中出现交叠现象以及其他相关问题，严重制约了半导体器件的良率和可靠性。
因此，为了解决现有技术中的上述技术问题，有必要提出一种新的半导体器件。
发明内容
针对现有技术的不足，本发明提出一种新的半导体器件和使用该半导体器件的电子装置，该半导体器件具有更高的良率和可靠性。
本发明实施例一提供一种半导体器件，包括半导体衬底以及位于所述半导体衬底上的核心器件和虚拟器件；其中，所述核心器件包括位于所述半导体衬底上的栅极以及位于所述栅极两侧的应力层，所述虚拟器件包括位于所述半导体衬底上的栅极以及位于所述栅极两侧的应力层，并且，当所述虚拟器件与所述核心器件的类型相同时，所述虚拟器件的应力层与所述核心器件的应力层的材料相同。
可选地，所述核心器件为NMOS，所述虚拟器件为NMOS，所述核心器件的应力层与所述虚拟器件的应力层均为嵌入式碳硅层。
可选地，所述核心器件为PMOS，所述虚拟器件为PMOS，所述核心器件的应力层与所述虚拟器件的应力层均为嵌入式锗硅层。
可选地，所述核心器件包括NMOS和PMOS，所述虚拟器件包括NMOS和PMOS，所述核心器件中NMOS的应力层与所述虚拟器件中NMOS的应力层相同且均为嵌入式碳硅层，所述核心器件中PMOS的应力层与所述虚拟器件中PMOS的应力层相同且均为嵌入式锗硅层。
可选地，在所述半导体器件中，所述虚拟器件的应力层形成抬升的源漏极。
可选地，所述核心器件的栅极为金属栅极。
可选地，所述虚拟器件的栅极为金属栅极。
可选地，在所述半导体器件中，所述虚拟器件被成对设置。
可选地，在所述半导体器件中，被成对设置的两个所述虚拟器件包括1个NMOS与1个PMOS。
本发明实施例二提供一种电子装置，其包括如上所述的半导体器件。
本发明的半导体器件，由于所包括的虚拟器件与核心器件一样具有应力层，因此可以保证在整个半导体器件中，位于应力层之上的膜层具有良好的交叠表现，可以提高半导体器件的良率和可靠性。本发明的电子装置，由于使用了上述半导体器件，因而同样具有上述优点。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1为现有技术中的半导体器件中的虚拟器件的结构的示意图；
图2为本发明实施例一的半导体器件所包括的虚拟器件的结构的示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
本发明的半导体器件，包含位于半导体衬底上的核心器件和虚拟器件(dummydevice)，其中，核心器件是指实现该半导体器件的功能的器件；虚拟器件，是指在半导体器件的制造过程中，在制作核心器件的同时在半导体衬底上制备的用于使核心器件周围环境保持一致以降低失配但通常不发挥电学功能的器件。本发明实施例的半导体器件，可以为各种半导体器件，例如EEPROM或其他类型的半导体器件。
下面，参照图2来描述本实施例的半导体器件的结构。本实施例的半导体器件，包括半导体衬底200以及位于半导体衬底200上的核心器件和虚拟器件(为了表示简要，图2未示出核心器件)。其中，所述核心器件包括位于所述半导体衬底上的栅极以及位于所述栅极两侧的应力层，其中，应力层为嵌入式锗硅层(当核心器件是PMOS时)或嵌入式碳硅层(当核心器件是NMOS时)。
如图2所示，在本实施例的半导体器件中，该虚拟器件包括位于半导体衬底200上的有源区201以及栅极202，还包括位于半导体衬底200上并位于栅极202两侧的应力层(stressor)203。
其中，应力层203采用与核心器件中的嵌入式锗硅层(对应PMOS)或嵌入式碳硅层(对应NMOS)相同的材料。通常在形成核心器件的嵌入式锗硅层或嵌入式碳硅层的工艺中同时形成虚拟器件的应力层203，应力层203的形貌通常与嵌入式锗硅层或嵌入式碳硅层的形貌保持一致。具体地，当虚拟器件为NMOS时，应力层203与核心器件中的NMOS保持一致，采用嵌入式碳硅层形成；当虚拟器件为PMOS时，应力层203与核心器件中的PMOS保持一致，采用嵌入式锗硅层形成。
在本实施例中，虚拟器件的应力层203可以与核心器件一样，形成抬升的源漏极结构；也就是说，虚拟器件中的N型晶体管(NMOS)与P型晶体管(PMOS)均形成有抬升的源漏极结构。
通常地，在本实施例的半导体器件中，在栅极202的两侧均具有应力层203，也就是说，应力层203在虚拟器件中总是成对出现。当然，应力层203也可以采取其他形式进行设置，例如在一个虚拟器件中只形成一个应力层，本实施例并不进行限定。
在本实施例中，虚拟器件可以与核心器件的结构完全一致。例如：虚拟器件中的NMOS采用与核心器件中的NMOS完全相同的结构，虚拟器件中的PMOS采用与核心器件中的PMOS完全相同的结构。
进一步地，在本实施例的半导体器件中，上述虚拟器件是成对设置的。更进一步地，该成对设置的虚拟器件包括一个NMOS和一个PMOS。
在本实施例中，示例性地，半导体器件为采用高k金属栅极技术制备，核心器件的栅极为金属栅极，并且，所述虚拟器件的栅极为金属栅极。
由于虚拟器件包括应力层203，使得在半导体器件的制造过程中，在形成应力层203的工艺之后，虚拟器件位置处的形貌与核心器件位置处的形貌保持一致，因而可以保证整个半导体衬底的表面上具有均一的环境，有利于后续工艺的实现。
本实施例的半导体器件，由于存在上述虚拟器件，可以保证在形成应力层之后的后续工艺中具有良好的交叠表现、友好的工艺集成以及更可靠的SPICE模型，因而可以提高半导体器件的良率和可靠性。特别地，当虚拟器件在栅极两侧均具有应力层(即，双应力层结构)时，半导体器件将具有更好的交叠表现。进一步地，当虚拟器件中的NMOS和PMOS均具有由应力层形成的抬升的源漏极结构时，有利于半导体器件制造过程的中段制程的工艺集成。
简言之，本发明实施例的半导体器件，由于所包括的虚拟器件与核心器件一样具有应力层，因此可以保证在整个半导体器件中，位于应力层之上的膜层具有良好的交叠表现，可以提高半导体器件的良率和可靠性。
本实施例的半导体器件结构，尤其适用于22nm及以下工艺节点的半导体器件。
实施例二
本发明实施例提供一种电子装置，其包括：实施例一所述的半导体器件。
由于使用的半导体器件具有更高的良率和可靠性，该电子装置同样具有上述优点。
该电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可以是具有上述半导体器件的中间产品，例如：具有该集成电路的手机主板等。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (10)

1.一种半导体器件，其特征在于，包括半导体衬底以及位于所述半导体衬底上的核心器件和虚拟器件；其中，所述核心器件包括位于所述半导体衬底上的栅极以及位于所述栅极两侧的应力层，所述虚拟器件包括位于所述半导体衬底上的栅极以及位于所述栅极两侧的应力层，并且，当所述虚拟器件与所述核心器件的类型相同时，所述虚拟器件的应力层与所述核心器件的应力层的材料相同。
2.如权利要求1所述的半导体器件，其特征在于，所述核心器件为NMOS，所述虚拟器件为NMOS，所述核心器件的应力层与所述虚拟器件的应力层均为嵌入式碳硅层。
3.如权利要求1所述的半导体器件，其特征在于，所述核心器件为PMOS，所述虚拟器件为PMOS，所述核心器件的应力层与所述虚拟器件的应力层均为嵌入式锗硅层。
4.如权利要求1所述的半导体器件，其特征在于，所述核心器件包括NMOS和PMOS，所述虚拟器件包括NMOS和PMOS，所述核心器件中NMOS的应力层与所述虚拟器件中NMOS的应力层相同且均为嵌入式碳硅层，所述核心器件中PMOS的应力层与所述虚拟器件中PMOS的应力层相同且均为嵌入式锗硅层。
5.如权利要求1所述的半导体器件，其特征在于，在所述半导体器件中，所述虚拟器件的应力层形成抬升的源漏极。
6.如权利要求1所述的半导体器件，其特征在于，所述核心器件的栅极为金属栅极。
7.如权利要求1所述的半导体器件，其特征在于，所述虚拟器件的栅极为金属栅极。
8.如权利要求1所述的半导体器件，其特征在于，在所述半导体器件中，所述虚拟器件被成对设置。
9.如权利要求8所述的半导体器件，其特征在于，被成对设置的两个所述虚拟器件包括1个NMOS与1个PMOS。
10.一种电子装置，其特征在于，包括权利要求1所述的半导体器件。
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