CN104851911A - 一种半导体器件及其制造方法和电子装置 - Google Patents
一种半导体器件及其制造方法和电子装置 Download PDFInfo
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052796 boron Inorganic materials 0.000 claims abstract description 37
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims abstract description 21
- 229910052732 germanium Inorganic materials 0.000 claims description 22
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 22
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Abstract
本发明提供一种半导体器件及其制造方法和电子装置,涉及半导体技术领域。本发明的半导体器件的制造方法,通过形成位于嵌入式锗硅层之上的掺杂有硼的盖帽层,可以提高PMOS的源极和漏极区域的载流子浓度,因此可以省略现有技术中对PMOS的源极和漏极区域进行离子注入和退火工艺处理的步骤,即简化了半导体器件制造的工艺流程。本发明的半导体器件,由于在位于嵌入式锗硅层之上的盖帽层中掺杂有硼,因此可以提高PMOS的性能进而提高整个半导体器件的性能。本发明的电子装置,使用了上述半导体器件,同样具有上述优点。
Description
技术领域
本发明涉及半导体技术领域,具体而言涉及一种半导体器件及其制造方法和电子装置。
背景技术
在半导体技术领域中,对于先进的CMOS逻辑器件,应力工程是改善器件性能的最重要的因素之一。对于PMOS而言,主要通过形成外延锗硅源漏提高对沟道的压应力,以提高载流子迁移率。
现有技术中的半导体器件的制造方法,在对PMOS采用应力工程技术时,如图1A至1D所示,主要包括如下步骤:
步骤E1:在半导体衬底100位于PMOS的栅极两侧的区域形成用于容置锗硅层的沟槽1001,如图1A所示。
其中,沟槽1001可以为碗状、∑型或其他合适的形状。
步骤E2:在沟槽1001内形成嵌入式锗硅层101,如图1B所示。
其中,嵌入式锗硅层101内可以掺杂有硼(B)。形成嵌入式锗硅层101的方法,通常称作选择性外延生长法(selective epitaxy)。
步骤E3:在嵌入式锗硅层101上形成硅盖帽层102,如图1C所示。
其中,硅盖帽层102就是材料为硅的盖帽层,在现有技术中其不掺杂任何其他元素。
步骤E4:对PMOS的源极和漏极区域进行离子注入和退火工艺,如图1D所示。
在图1D中,“向下的箭头”用于示意离子注入工艺。图1D并未示出在离子注入工艺之后的退火工艺。
其中,离子注入工艺用于调节PMOS的源极和漏极区域的载流子浓度。退火工艺,则主要用于激活注入的离子。
然而,在现有技术中,步骤E4中的离子注入工艺往往会破坏嵌入式锗硅层102的晶格排列,导致嵌入式锗硅层102对沟道施加的压应力在很大程度上被释放。压应力被释放,将导致PMOS器件的性能下降。
为解决现有技术中的上述技术问题,有必要提出一种新的半导体器件的制造方法。
发明内容
针对现有技术的不足,本发明提出一种新的半导体器件及其制造方法和电子装置。
本发明实施例一提供一种半导体器件的制造方法,所述方法包括:
步骤S101:在半导体衬底的位于PMOS的栅极两侧的区域形成用于容置锗硅层的沟槽;
步骤S102:在所述沟槽内形成掺杂有硼的嵌入式锗硅层;
步骤S103:在所述嵌入式锗硅层之上形成掺杂有硼的盖帽层。
可选地,在所述嵌入式锗硅层中,锗的原子百分比为30%~50%。
进一步地,在所述嵌入式锗硅层中,硼的含量为5E19~3E20。
其中,在所述步骤S102中,形成所述嵌入式锗硅层的方法为选择性外延生长法,其中,工艺的温度为500~800℃,压力为1~100托。
其中,在所述步骤S102中,在形成所述嵌入式锗硅层的过程中所采用的反应气体包括SiH4、HCl、B2H6、GeH4和H2,其中,SiH4、HCl、B2H6和GeH4的流速为1~1000sccm,H2的流速为0.1~50slm;
或者,在形成所述嵌入式锗硅层的过程中所采用的反应气体包括DCS:SiH2Cl2、HCl、B2H6、GeH4和H2;其中,DCS、HCl、B2H6和GeH4的流速为1~1000sccm,H2的流速为0.1~50slm。
其中,在所述步骤S103中形成的所述盖帽层中还掺杂有锗。
进一步地,在所述盖帽层中锗的原子百分比为1%~10%。
可选地,在所述盖帽层中,硼的含量为5E19~2E20。
本发明实施例二提供一种半导体器件,包括半导体衬底和位于所述半导体衬底上的PMOS,还包括形成于所述半导体衬底位于所述PMOS的栅极两侧的区域内的嵌入式锗硅层以及位于所述嵌入式锗硅层之上的盖帽层,其中所述嵌入式锗硅层与所述盖帽层掺杂有硼。
可选地,在所述嵌入式锗硅层中,锗的原子百分比为30%~50%。
进一步地,在所述嵌入式锗硅层中,硼的含量为5E19~3E20。
其中,所述盖帽层中还掺杂有锗。进一步地,在所述盖帽层(202)中,锗的原子百分比为1%~10%。
其中,在所述盖帽层中硼的含量为5E19~2E20。
本发明实施例三提供一种电子装置,其包括如上所述的半导体器件。
本发明的半导体器件的制造方法,通过形成位于嵌入式锗硅层之上的掺杂有硼的盖帽层,可以提高PMOS的源极和漏极区域的载流子浓度,因此可以省略现有技术中对PMOS的源极和漏极区域进行离子注入和退火工艺处理的步骤,即简化了半导体器件制造的工艺流程。本发明的半导体器件,由于在位于嵌入式锗硅层之上的盖帽层中掺杂有硼,因此可以提高PMOS的性能进而提高整个半导体器件的性能。本发明的电子装置,使用了上述半导体器件,同样具有上述优点。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述,用来解释本发明的原理。
附图中:
图1A至图1D为现有技术中的一种半导体器件的制造方法的相关步骤形成的结构的示意性剖视图;
图2A至图2C为本发明实施例一的半导体器件的制造方法的相关步骤形成的结构的示意性剖视图;
图3为本发明实施例一的半导体器件的制造方法的一种示意性流程图;
图4为本发明实施例二的半导体器件的示意性剖视图。
具体实施方式
在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。
应当理解的是,本发明能够以不同形式实施,而不应当解释为局限于这里提出的实施例。相反地,提供这些实施例将使公开彻底和完全,并且将本发明的范围完全地传递给本领域技术人员。在附图中,为了清楚,层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样,可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此,本发明的实施例不应当局限于在此所示的区的特定形状,而是包括由于例如制造导致的形状偏差。例如,显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度,而不是从注入区到非注入区的二元改变。同样,通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此,图中显示的区实质上是示意性的,它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明,将在下列的描述中提出详细的步骤以及详细的结构,以便阐释本发明的技术方案。本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。
实施例一
下面,参照图2A至图2C和图3来描述本发明实施例提出的半导体器件的制造方法。其中,图2A至图2C为本发明实施例的半导体器件的制造方法的相关步骤形成的结构的示意性剖视图;图3为本发明实施例的半导体器件的制造方法的一种示意性流程图。
本实施例的半导体器件的制造方法,包括如下步骤:
步骤A1:在半导体衬底200的位于PMOS的栅极两侧的区域形成用于容置锗硅层的沟槽2001,如图2A所示。
其中,沟槽2001可以为碗状、∑型或其他合适的形状。形成沟槽2001的方法,可以为干法刻蚀、湿法刻蚀、先干法刻蚀再湿法刻蚀等各种可行的方法。在进行步骤A1前,半导体衬底200上已经形成伪栅极结构或栅极结构以及其他在嵌入式锗硅工艺前形成的组件。
步骤A2:在沟槽2001内形成掺杂有硼(B)的嵌入式锗硅层201,如图2B所示。
其中,在嵌入式锗硅层201中,锗(Ge)的原子百分比高于现有技术,可选地,锗(Ge)的原子百分比为30%~50%。并且,硼(B)的含量也很高,可选地,硼的含量为5E19~3E20。
在本实施例中,形成嵌入式锗硅层101的方法,可以为选择性外延生长法(selective epitaxy)或其他合适的方法。
可选地,形成嵌入式锗硅层201的方法为选择性外延生长法。其中,工艺的温度控制在500~800℃,压力控制在1~100托(Torr)。进一步地,反应气体包括SiH4(或DCS:SiH2Cl2)、HCl、B2H6、GeH4和H2;其中,SiH4、DCS、HCl、B2H6和GeH4的流速为1~1000sccm;H2的流速为0.1~50slm。其中,slm(Standard Liter per Minute)表示每分钟标准升;sccm(Standard Cubic Centimeter per Minute)表示每分钟标准毫升。
步骤A3:在嵌入式锗硅层201之上形成掺杂有硼的盖帽层202,如图2C所示。
其中,盖帽层102可以为原位掺杂硼的硅盖帽层。显然,本实施例的盖帽层202与现有技术中的盖帽层101不同,在现有技术中盖帽层101不掺杂其他元素。
进一步地,为了保证盖帽层202(包含Si和B)的良好形成,可以在盖帽层202内掺杂少量的锗(Ge)。由于Si和B的晶格结构存在很大的不同,如果单纯进行锗掺杂,形成的硅盖帽层的表面往往比较粗糙。本实施例通过在盖帽层202内掺杂少量的锗(Ge),利用锗原子补偿Si和B的晶格差异,可以形成表面光滑的盖帽层。
其中,在盖帽层202中,锗(Ge)的原子百分比为1%~10%,硼的含量为5E19~2E20。
本实施例的半导体器件的制造方法,由于位于嵌入式锗硅层201上的盖帽层202掺杂有硼,因此可以提高PMOS的源极和漏极区域的载流子浓度,因而可以省略现有技术中的对PMOS的源极和漏极区域进行离子注入和退火工艺处理的步骤。也就是说,在本实施例中,嵌入式锗硅层201与位于其上盖帽层202直接作为PMOS的源极和漏极,省略了进行离子注入和退火处理的步骤。
至此,完成了本发明实施例的半导体器件的制造方法的相关步骤的介绍。在上述步骤A3之后,本实施例的方法不需再对PMOS的源极和漏极区域进行离子注入和退火工艺处理,可以直接进行其他后续步骤,例如形成层间介电层的步骤、形成互连结构的步骤等,这些步骤均可以通过现有技术中的各种工艺来实现,此处不再赘述。
本实施例的半导体器件的制造方法,由于在位于嵌入式锗硅层201上的盖帽层202掺杂有硼,可以提高PMOS的源极和漏极区域的载流子浓度,因此可以省略现有技术中的对PMOS的源极和漏极区域进行离子注入和退火工艺处理的步骤,即简化了半导体器件制造的工艺流程。进一步地,由于嵌入式锗硅层201中锗的百分比高于现有技术,并且盖帽层202掺杂有硼,因此可以提高PMOS的源极和漏极区域的载流子浓度,保证PMOS器件具有更好的性能。
图3示出了本发明实施例提出的半导体器件的制造方法的一种示意性流程图,用于简要示出上述方法的典型流程。具体包括:
步骤S101:在半导体衬底的位于PMOS的栅极两侧的区域形成用于容置锗硅层的沟槽;
步骤S102:在所述沟槽内形成掺杂有硼的嵌入式锗硅层;
步骤S103:在所述嵌入式锗硅层之上形成掺杂有硼的盖帽层。
实施例二
本实施例提供一种半导体器件,其可以采用实施例一所述的半导体器件的制造方法制得。
如图4所示,本实施例的半导体器件,包括半导体衬底200和位于半导体衬底200上的PMOS,还包括形成于半导体衬底200位于该PMOS的栅极两侧的区域内的嵌入式锗硅层201以及位于嵌入式锗硅层201上的盖帽层202,其中嵌入式锗硅层201和盖帽层202中掺杂有硼(B)。
其中,在嵌入式锗硅层201中,锗的原子百分比为30%~50%;硼的含量为5E19~3E20。
进一步地,所述盖帽层202中还掺杂有锗。其中,锗的原子百分比为1%~10%。
其中,在所述盖帽层202中,硼的含量为5E19~2E20。
本实施例的半导体器件,由于在位于嵌入式锗硅层201之上的盖帽层202中掺杂有硼,因此可以提高PMOS的源极和漏极区域的载流子浓度,使得器件具有更好的性能。
实施例三
本发明实施例提供一种电子装置,其包括实施例二所述的半导体器件,或根据实施例一所述的半导体器件的制造方法制得的半导体器件。
由于使用的半导体器件在位于嵌入式锗硅层上方的盖帽层中掺杂有硼,可以提高PMOS的源极和漏极区域的载流子浓度,使得器件具有更好的性能,因此该电子装置同样具有上述优点,具有更好的性能。
该电子装置,可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备,也可以是具有上述集成电路的中间产品,例如:具有该集成电路的手机主板等。
本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。
Claims (15)
1.一种半导体器件的制造方法,其特征在于,所述方法包括:
步骤S101:在半导体衬底的位于PMOS的栅极两侧的区域形成用于容置锗硅层的沟槽;
步骤S102:在所述沟槽内形成掺杂有硼的嵌入式锗硅层;
步骤S103:在所述嵌入式锗硅层之上形成掺杂有硼的盖帽层。
2.如权利要求1所述的半导体器件的制造方法,其特征在于,在所述嵌入式锗硅层中,锗的原子百分比为30%~50%。
3.如权利要求1所述的半导体器件的制造方法,其特征在于,在所述嵌入式锗硅层中,硼的含量为5E19~3E20。
4.如权利要求1所述的半导体器件的制造方法,其特征在于,在所述步骤S102中,形成所述嵌入式锗硅层的方法为选择性外延生长法,其中,工艺的温度为500~800℃,压力为1~100托。
5.如权利要求4所述的半导体器件的制造方法,其特征在于,在所述步骤S102中,在形成所述嵌入式锗硅层的过程中所采用的反应气体包括SiH4、HCl、B2H6、GeH4和H2,其中,SiH4、HCl、B2H6和GeH4的流速为1~1000sccm,H2的流速为0.1~50slm;
或者,在形成所述嵌入式锗硅层的过程中所采用的反应气体包括DCS:SiH2Cl2、HCl、B2H6、GeH4和H2;其中,DCS、HCl、B2H6和GeH4的流速为1~1000sccm,H2的流速为0.1~50slm。
6.如权利要求1所述的半导体器件的制造方法,其特征在于,在所述步骤S103中,形成的所述盖帽层中还掺杂有锗。
7.如权利要求6所述的半导体器件的制造方法,其特征在于,在所述盖帽层中,锗的原子百分比为1%~10%。
8.如权利要求1所述的半导体器件的制造方法,其特征在于,在所述盖帽层中,硼的含量为5E19~2E20。
9.一种半导体器件,其特征在于,包括半导体衬底和位于所述半导体衬底上的PMOS,还包括形成于所述半导体衬底位于所述PMOS的栅极两侧的区域内的嵌入式锗硅层以及位于所述嵌入式锗硅层上的盖帽层,其中所述嵌入式锗硅层和所述盖帽层中掺杂有硼。
10.如权利要求9所述的半导体器件,其特征在于,在所述嵌入式锗硅层中,锗的原子百分比为30%~50%。
11.如权利要求9所述的半导体器件,其特征在于,在所述嵌入式锗硅层中,硼的含量为5E19~3E20。
12.如权利要求9所述的半导体器件,其特征在于,所述盖帽层中还掺杂有锗。
13.如权利要求12所述的半导体器件,其特征在于,在所述盖帽层中,锗的原子百分比为1%~10%。
14.如权利要求9所述的半导体器件,其特征在于,在所述盖帽层中,硼的含量为5E19~2E20。
15.一种电子装置,其特征在于,包括权利要求9所述的半导体器件。
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