CN102034866B - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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CN102034866B
CN102034866B CN2010102822708A CN201010282270A CN102034866B CN 102034866 B CN102034866 B CN 102034866B CN 2010102822708 A CN2010102822708 A CN 2010102822708A CN 201010282270 A CN201010282270 A CN 201010282270A CN 102034866 B CN102034866 B CN 102034866B
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germanium
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source
effect transistor
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CN102034866A (zh
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叶致锴
张智胜
万幸仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种包括n型鳍式场效晶体管与p型鳍式场效晶体管的集成电路结构。n型鳍式场效晶体管包括：第一锗鳍(first germanium fin)位于一基板之上；一第一栅极介电层，位于第一锗鳍的顶表面与侧壁上；以及一第一栅极电极，位于第一栅极介电层之上。p型鳍式场效晶体管包括：一第二锗鳍，位于基板之上；一第二栅极介电层，位于第二锗鳍的顶表面与侧壁上；以及一第二栅极电极，位于第二栅极介电层之上。第一栅极电极与第二栅极电极由相同材料所组成，此材料具有一功函数接近锗的本征能级(intrinsic energy level)。本发明可同时达到n型FinFETs与p型FinFETs的功函数最佳化。

Description

集成电路结构
技术领域
本发明涉及一种集成电路结构，且特别涉及一种鳍式场效晶体管(finfield effect transistor，FinFET)的结构与其形成方法。
背景技术
金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管的速度与MOS的驱动电流(drive current)息息相关，其中驱动电流又与电荷迁移率(mobility of charges)息息相关。举例而言，当电子于其沟道内具有较高的电子迁移率时，n型金属氧化物半导体(NMOS)晶体管具有较大的驱动电流，当空穴于其沟道内具有较高的空穴迁移率时，p型金属氧化物半导体(PMOS)晶体管具有较大的驱动电流。
锗(Germanium，Ge)是一种已知的半导体材料。锗的电子与空穴迁移率皆高于硅(分别为2.6倍与4倍)，且锗是一种常用于形成集成电路的半导体材料。因此，对于形成集成电路，锗为一优异的材料。锗的另一项优点在于，相较于硅，锗的电子/空穴迁移率具有较大的应力灵敏度(stress sensitivity)。举例而言，图1显示锗与硅的空穴迁移率与单轴压缩应力(uni-axialcompressive stresses)的关系图。须注意的是，随着压缩应力的增加，锗的空穴迁移率增加速度高于硅，这表示以锗为主的p型金属氧化物半导体(PMOS)晶体管元件，比起以硅为主的PMOS元件有可能具有较大的驱动电流。同样的，图2显示锗与硅的电子迁移率与单轴压缩应力(uni-axial compressivestresses)的关系图。须注意的是，随着压缩应力的增加，锗的电子迁移率增加速度高于硅，这样表示以锗为主的N型金属氧化物半导体(NMOS)晶体管元件，比起以硅为主的NMOS元件有可能具有较大的驱动电流。
然而，锗却有下述缺点。锗的能带隙(bandgap)为0.66eV，小于硅的能带隙(1.12eV)。如此一来，以锗为主的MOS元件的基板漏电流(leakage current)会非常高。此外，锗的介电常数值为16，大于硅的介电常数值(11.9)。因此，以锗为主的MOS元件的漏极引致能障下降(drain-induced barrier lowering，DIBL)也会高于以硅为主的MOS元件。
发明内容
为克服上述现有技术的缺陷，本发明提供一种集成电路结构，包括：一基板；一n型鳍式场效晶体管(n-type fin field effect transistor，n-type FinFET)，其中该n型鳍式场效晶体管包括：一第一锗鳍(first germanium fin)，位于该基板之上；一第一栅极介电层，位于该第一锗鳍的顶表面与侧壁上；以及一第一栅极电极，位于该第一栅极介电层之上；以及一p型鳍式场效晶体管(p-type fin field effect transistor，p-type FinFET)，其中该p型鳍式场效晶体管包括：一第二锗鳍，位于该基板之上；一第二栅极介电层，位于该第二锗鳍的顶表面与侧壁上；以及一第二栅极电极，位于该第二栅极介电层之上，其中该第一栅极电极与第二栅极电极由相同材料所组成，此材料具有一功函数接近锗的本征能级(intrinsic energy level)。
本发明另提供一种集成电路结构，包括：一基板；一n型鳍式场效晶体管(n-type fin field effect transistor，FinFET)，其中该n型鳍式场效晶体管包括：一第一锗鳍(first germanium fin)，位于该基板之上；一第一栅极介电层，位于该第一锗鳍的顶表面与侧壁上；以及一第一栅极电极，位于该第一栅极介电层之上；一第一源极/漏极区域，相邻于该第一栅极电极，其中该第一源极/漏极区域包括一第一外延区，且该第一外延区的晶格常数小于该第一锗鳍的晶格常数；以及一p型鳍式场效晶体管，其中该p型鳍式场效晶体管包括：一第二锗鳍，位于该基板之上；一第二栅极介电层，位于该第二锗鳍的顶表面与侧壁上；以及一第二栅极电极，位于该第二栅极介电层之上，其中该第一栅极电极与第二栅极电极皆具有一功函数接近锗的本征能级(intrinsicenergy level)；以及一第二源极/漏极区域，相邻于该第一栅极电极，其中该第二源极/漏极区域包括一第二外延区，且该第二外延区的晶格常数小于该第二锗鳍的晶格常数。
本发明也提供一种集成电路结构，包括：一基板；以及一第一鳍式场效晶体管(n-type fin field effect transistor，FinFET)，其中该第一鳍式场效晶体管包括：一第一锗鳍(first germanium fin)，位于该基板之上，其中该第一锗鳍的锗含量大于50％原子百分比；一第一栅极介电层，位于该第一锗鳍的顶表面与侧壁上；一第一金属栅极，位于该第一栅极介电层之上；以及一第一源极/漏极区域，相邻于该第一金属栅极，其中该第一源极/漏极区域包括一第一外延区，且该第一外延区由一与第一锗鳍不同的半导体材料所组成。
本发明可同时达到n型FinFETs与p型FinFETs的功函数最佳化，甚至是使用相同金属材料作为n型FinFETs与p型FinFETs的栅极。除了上述的优点外，本发明的实施例还包括下述优点。借由形成以锗为主的FinFETs，由于锗具有高电子与空穴的迁移率，因此，可同时增进n型FinFETs与p型FinFETs的驱动电流。比起传统的平面MOS元件，由于FinFETs的结面积降低，因此，也可降低漏电流。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，作详细说明如下：
附图说明
图1为一关系图，用以说明锗与硅的空穴迁移率与单轴压缩应力(uni-axial compressive stresses)的关系图。
图2为一关系图，用以说明锗与硅的电子迁移率与单轴压缩应力(uni-axial compressive stresses)的关系图。
图3～图9为一系列透视图与剖面图，用以说明本发明的一实施例制作以锗为主的FinFET的中间工艺阶段。
图10～图12为一系列透视图与剖面图，用以说明本发明的一实施例的多个鳍的FinFET。
图13显示锗的能级图。
其中，附图标记说明如下：
20～基板
22～浅沟隔离区(STI)
32～栅极介电层
34～栅极电极层
35～浅沟隔离区域(STI)22的顶表面
100～NMOS元件
124、224～锗鳍
132、232～栅极介电层
134、234～栅极电极层
136、236～栅极间隙壁
140、240～凹口
141、241～光致抗蚀剂
142、242～源极/漏极区域
150～NMOS鳍式场效晶体管(NMOS FinFET)
200～PMOS元件
250～PMOS鳍式场效晶体管(PMOS FinFET)
320～基板
324～虚设鳍
350～虚设鳍结构
W～锗鳍的宽度
H～锗鳍的高度
具体实施方式
以下特举出本发明的实施例，并配合附图作详细说明。以下实施例的元件和设计是为了简化所揭示的发明，并非用以限定本发明。
本发明提出一种新颖的鳍式场效晶体管的实施例与其形成方法，并说明制作此实施例的中间制作步骤，也讨论实施例的各种变化所显示的实施例与附图，类似的元件使用类似的附图标记标示。
请参见图3，形成一集成电路。此集成电路结构包括基板20，基板20可以是硅基板、锗基板、或由其他半导体材料所形成的基板。基板20可掺杂p型或n型杂质。隔离区域，例如浅沟隔离区域(shallow trench isolationregion，STI region)22可形成于基板20之中或之上。锗鳍124与224形成于浅沟隔离区域(STI region)22的顶表面上。于一示范实施例中，借由挖凿(recess)介于相邻浅沟隔离区域(STI region)22之间的基板20的上部分，以形成凹口(recesses)，且经由再成长锗(re-growing germanium)以形成锗鳍124与224。浅沟隔离区域(STI region)22的上部分可以被移除，而浅沟隔离区域(STIregion)22的下部分未被移除，使得介于相邻浅沟隔离区域(STI region)22之间的再成长锗的顶部分变成锗鳍。举例而言，锗鳍124与224可具有锗含量大于50％原子百分比。于一实施例中，锗鳍124与224可由纯锗所组成。于另一实施例中，锗鳍124与224可由硅锗所组成。
锗鳍124与224可具有沟道掺杂(channel doping)。锗鳍124可掺杂p型杂质，例如硼，而锗鳍224可掺杂n型杂质，例如磷。锗鳍124与224的沟道掺杂可低于5×1017/cm3，或低于约1×1017/cm3。于一示范实施例中，锗鳍124与224的深宽比(aspect ratio)(高度H对宽度W的比率)可大于1，或甚至大于5。基板20包括一部分位于NMOS元件区100与一部分位于PMOS元件区200。锗鳍124与224分别位于NMOS元件区100与PMOS元件区200。
请参见图4，栅极介电层32与栅极电极层34设置于NMOS元件100与PMOS元件200中，且位于锗鳍124与224之上。于一实施例中，栅极介电层32由高介电常数(high-k)介电材料所组成。示范的高介电常数介电材料具有介电常数值(k)为4.0，或甚至大于7.0，且其可包括含铝的介电材料(例如氧化铝(Al2O3)、氧化铝铪(HfAlO)、氮氧化铝铪(HfAlON)、氧化锆铝(AlZrO))、含铪的材料(例如氧化铪(HfO2)、氧硅化铪(HfSiOx)、氧化铝铪(HfAlOx)、氧硅化锆铪(HfZrSiOx)、氮氧硅化铪(HfSiON))、及/或其他材料(例如氧化铝镧(LaAlO3)与氧化锆(ZrO2))。
栅极电极层34形成于栅极介电层32之上，且可包括金属。栅极电极层34可具有一功函数接近锗的本征能级(intrinsic level)，此本征能级为锗的导电带(conduction band)(4eV)与价带(valance band)(4.66eV)的中间能级(为约4.33eV)。于一实施例中，栅极电极层34的功函数介于约4.15eV～4.5eV，或甚至介于约4.25eV～4.4eV。栅极电极层34的示范材料包括氮化钛(TixNy)、氮化钽(TaxNy)、铝(Al)、碳化钽(TaxCy)、铂(Pt)，上述的多层，及上述的组合，其中x与y为正值。
如图5所示，栅极电极层34与栅极介电层32被图案化以形成栅极堆叠。位于NMOS元件区100的栅极堆叠包括栅极电极134与栅极介电层132。位于PMOS元件区200的栅极堆叠包括栅极电极234与栅极介电层232。每一个锗鳍因此具有一部分未被栅极堆叠所覆盖。
请参见图6，形成栅极间隙壁136与236。锗鳍124与234中未被栅极介电层132与232、栅极电极134与234，以及栅极间隙壁136与236所覆盖的曝露部分接着被移除(凹凿)，而锗鳍124与224中被覆盖的部分则未被移除。可借由干式蚀刻进行移除。锗鳍124与224被移除的部分中所残留的空间在此被分别称为凹口140与240。凹口140与240的底部可与浅沟隔离区域222的顶表面35等高。另外，凹口140与240的底部可低于浅沟隔离区域222的顶表面35，如图6所示。
图7(与后续的图8与图9)显示图6结构中的剖面图，在图6中沿着穿过线7-7的垂直平面可得到NMOS元件100的剖面图；沿着穿过线7’-7’的垂直平面可得到PMOS元件200的剖面图。须注意的是，虽然图7与后续的图8与图9显示NMOS元件100与PMOS元件200的剖面图处于相同平面，然而实际上，其可以处于不同平面。
接着，请参见图8，PMOS元件200被光致抗蚀剂241覆盖，以及借由选择性外延成长(selective epitaxial growth，SEG)对凹口140进行外延成长，以得到源极与漏极(之后称为源极/漏极)区域142。源极/漏极区域142也称为源极/漏极应力区域142，且其晶格常数小于锗鳍124的晶格常数。于一示范的实施例中，借由等离子体增强型化学气相沉积法(plasma enhanced chemicalvapor deposition，PECVD)或其他常用方法形成包含硅锗(SiGe)的源极/漏极区域142。前驱物可包括含硅气体(例如硅甲烷(SiH4))与含锗气体(例如锗甲烷(GeH4))，且可调整含硅气体与含锗气体的分压(partial pressure)，以变更硅对锗的原子比例。于一实施例中，所得的源极/漏极区142包括介于约20-60％原子百分比的硅。于另一实施例中，源极/漏极区域142可由碳化硅(siliconcarbon，SiC)，或不含碳的硅及/或添加锗的硅所组成。当进行外延成长工艺时，可于原位(in-situ)进行掺杂N型杂质，例如磷及/或砷。由于源极/漏极区域142的晶格常数小于锗鳍124的晶格常数，源极/漏极区域142会对硅锗124施加一伸张应力(tensile stress)，因而形成n型FinFET 150的沟道区域。进行源极/漏极区域142的外延成长工艺之后，移除光致抗蚀剂241。
请参见图9，NMOS元件100被光致抗蚀剂141覆盖，以及于凹口240中进行外延成长(epitaxial growth)，以得到源极与漏极区域242，也可称为源极/漏极应力区域242。源极/漏极区域242的晶格常数大于锗鳍224的晶格常数。同样的，可借由等离子体增强型化学气相沉积法(plasma enhancedchemical vapor deposition，PECVD)形成源极/漏极区域242。于一实施例中，源极/漏极区域242包括锗锡(GeSn)。于另一实施例中，源极/漏极区域242可由包含IIIA族与VA族的化合物半导体材料所组成(此处称为III-V族半导体材料)，例如砷化镓铟(InGaAs)、磷化铟(InP)、锑化镓(GaSb)、砷化铟(InAs)、锑化铝(AlSb)、锑化铟(InSb)，与类似的材料。由于源极/漏极区域242的晶格常数大于锗鳍224的晶格常数，源极/漏极区域242会对硅锗224施加一压缩应力(compressive stress)，因而形成PMOS FinFET 250的沟道区域。进行源极/漏极区域242的外延成长工艺之后，移除光致抗蚀剂141。
于形成源极/漏极区域142与242的外延工艺时，可伴随外延工艺，各自对源极/漏极区域142与242掺杂n型杂质(例如磷)或p型杂质(例如硼)。杂质的浓度可介于5×1020/cm3～1×1021/cm3。于另一实施例中，也可不先掺杂n型杂质或p型杂质，于形成源极/漏极区域142与242之后，可进行注入(implantation)步骤，以达成对源极/漏极区域142与242的掺杂。
接着，源极/漏极区域142与242借由与金属反应，以形成硅化物/锗化物(silicide/germanide)于源极/漏极区域142与242之上，用以降低接触电阻(contact resistances)。形成硅化物/锗化物(silicide/germanide)的详细步骤，已为本领域技术人员所熟知，在此不再赘述。经由上述讨论的工艺步骤，以形成n型FinFET 150与PMOS FinFET 250。
于上述讨论的实施例中，已讨论单一鳍FinFET。另外地，本发明的概念也可应用于多鳍(multi-fin)FinFET。图10-图12显示多鳍FinFET的剖面图与透视图。除非特别指明，相同的元件用相同的附图标记表示。显示于图10-图12中相同元件的材料在此不再赘述。图10显示一集成电路的剖面图，其中集成电路包括n型FinFET 150、PMOS FinFET 250以及虚设鳍结构(dummyfin structures)350，其中虚设鳍结构350包括虚设鳍324形成于基板320上。基板320可以是一锗基板或一硅基板。n型FinFET 150形成于p型阱之上且包括多个锗鳍124。栅极电极134形成于多个锗鳍124之上，因此，多个锗鳍124变成单一n型FinFET 150的多个鳍。栅极介电层132形成于锗鳍124与栅极电极134之间。PMOS FinFET 250形成于n型阱之上且包括多个锗鳍224。栅极电极234形成于多个锗鳍224之上，因此，多个锗鳍224变成单一PMOS FinFET 250的多个鳍。栅极介电层232形成于锗鳍124与栅极电极134之间。此外，于形成锗鳍124与224时，虚设鳍并未用于形成任何的FinFET，其仅用以减少图案负载效应(pattern-loading effect)。
将多个鳍应用于单一FinFET时，可进一步增加FinFET的驱动电流(drivecurrent)。由于锗与硅之间存在着晶格常数不匹配的问题，因此，从较小的鳍间距中形成锗外延层会比从较大的鳍间距中形成锗外延层更加容易，所以可得到较高品质(较低缺陷密度)的锗外延层。
图11与图12显示多个鳍FinFET的透视图。图11中类似的元件已出现于图10中。此FinFET可以是n型FinFET 150或PMOS FinFET250，在此简称为150/250。于图11中，源极/漏极区域(应力区域)142/242由锗鳍124/224成长而得，且为不连续的(discrete)区域。于图12中，由锗鳍124/224成长而得的源极/漏极区域(应力区域)142/242彼此合并在一起(merge with eachother)。
图13显示锗的能级图(energy bands)。须注意的是，锗的导电带(conduction band)Ec为4eV，价带(valence band)Ev为4.66eV，且本征能级Ei(由(Ec+Ev)/2而得)为4.33eV。因此，本征能级Ei与导电带Ec的能带隙为约330mV，且本征能级Ei与价带Ev的能带隙为约330mV。可利用330mV的能带隙，以简化n型锗FinFETs与p型锗FinFETs的金属栅极的形成。由于在锗FinFET中，完全耗尽的沟道(fully depleted channel)会造成阈值电压(threshold voltage，Vt)的降低，因此不再需要能带边缘的功函数(band-edgework function)。取而代之的是需要靠近中间能带的功函数(near-mid-bandgapwork functions)，以使阈值电压(threshold voltage，Vt)准确地偏移至所需数值。因此，对于以锗为主的FinFET，n型FinFETs与p型FinFETs两者的金属栅极的功函数接近4.33eV的本征能级，可同时达到n型FinFETs与p型FinFETs的功函数最佳化，甚至是使用相同金属材料作为n型FinFETs与p型FinFETs的栅极。
除了上述的优点外，本发明的实施例还包括下述优点。借由形成以锗为主的FinFETs，由于锗具有高电子与空穴的迁移率，因此，可同时增进n型FinFETs与p型FinFETs的驱动电流。比起传统的平面MOS元件，由于FinFETs的接面面积(junction areas)降低，因此，也可降低漏电流。
虽然本发明已以数个优选实施例揭示如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (9)

1.一种集成电路结构，包括：
一基板；
一n型鳍式场效晶体管，其中该n型鳍式场效晶体管包括：
一第一锗鳍，位于该基板之上；
一第一栅极介电层，位于该第一锗鳍的顶表面与侧壁上；以及
一第一栅极电极，位于该第一栅极介电层之上；
一源极/漏极区域，其中该源极/漏极区域的晶格常数小于该第一锗鳍的晶格常数；以及
一p型鳍式场效晶体管，其中该p型鳍式场效晶体管包括：
一第二锗鳍，位于该基板之上；
一第二栅极介电层，位于该第二锗鳍的项表面与侧壁上；以及
一第二栅极电极，位于该第二栅极介电层之上，其中该第一栅极电极与第二栅极电极由相同材料所组成，此材料具有一功函数介于4.25eV～4.4eV。
2.如权利要求1所述的集成电路结构，其中该第一栅极电极与第二栅极电极皆为金属栅极电极。
3.如权利要求1所述的集成电路结构，其中该n型鳍式场效晶体管还包括一含有碳化硅的源极/漏极区域。
4.如权利要求1所述的集成电路结构，其中该n型鳍式场效晶体管还包括一源极/漏极区域，其中该源极/漏极区域的锗原子百分比低于该第一锗鳍的锗原子百分比。
5.如权利要求1所述的集成电路结构，其中该p型鳍式场效晶体管包括一含有锗锡的源极/漏极区域。
6.如权利要求1所述的集成电路结构，其中该p型鳍式场效晶体管还包括一包含IIIA族元素与VA族元素的化合物半导体材料的源极/漏极区域，即III-V半导体材料的源极/漏极区域，其中该III-V半导体材料的晶格常数大于第二锗鳍的晶格常数。
7.如权利要求1所述的集成电路结构，其中该第一锗鳍与该第二锗鳍的锗含量大于50％原子百分比。
8.如权利要求1所述的集成电路结构，还包括：
一第三锗鳍，位于该第一栅极电极之下，其中该第三锗鳍与该第一锗鳍物理性地分隔且电性连接该第一锗鳍；以及
一第四锗鳍，位于该第二栅极电极之下，其中该第四锗鳍与该第二锗鳍物理性地分隔且电性连接该第二锗鳍。
9.一种集成电路结构，包括：
一基板；
一n型鳍式场效晶体管，其中该n型鳍式场效晶体管包括：
一第一锗鳍，位于该基板之上；
一第一栅极介电层，位于该第一锗鳍的顶表面与侧壁上；以及
一第一栅极电极，位于该第一栅极介电层之上；
一第一源极/漏极区域，相邻于该第一栅极电极，其中该第一源极/漏极区域包括一第一外延区，且该第一外延区的晶格常数小于该第一锗鳍的晶格常数；以及
一p型鳍式场效晶体管，其中该p型鳍式场效晶体管包括：
一第二锗鳍，位于该基板之上；
一第二栅极介电层，位于该第二锗鳍的顶表面与侧壁上；以及
一第二栅极电极，位于该第二栅极介电层之上，其中该第一栅极电极与第二栅极电极皆具有一功函数介于4.25eV～4.4eV；以及
一第二源极/漏极区域，相邻于该第一栅极电极，其中该第二源极/漏极区域包括一第二外延区，且该第二外延区的晶格常数大于该第二锗鳍的晶格常数。
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