JP2007123797A - 半導体ic内蔵基板及びその製造方法 - Google Patents
半導体ic内蔵基板及びその製造方法 Download PDFInfo
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- JP2007123797A JP2007123797A JP2006050475A JP2006050475A JP2007123797A JP 2007123797 A JP2007123797 A JP 2007123797A JP 2006050475 A JP2006050475 A JP 2006050475A JP 2006050475 A JP2006050475 A JP 2006050475A JP 2007123797 A JP2007123797 A JP 2007123797A
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Abstract
【解決手段】 主面120aにスタッドバンプ121が設けられた半導体IC120と、半導体IC120の主面120aを覆う第1の樹脂層111と、半導体IC120の裏面120bを覆う第2の樹脂層112とを備える。半導体IC120のスタッドバンプ121は、第1の樹脂層111の表面から突出している。スタッドバンプ121を第1の樹脂層111の表面から突出させる方法としては、ウエットブラスト法などを用いて第1の樹脂層111の厚さを全体的に減少させればよい。これにより、半導体IC120の電極ピッチが狭い場合であっても、正しくスタッドバンプ121の頭出しを行うことができる。
【選択図】 図1
Description
A<B、又は
A=B
であると、図13に示すように、ドライフィルム101のパターニング時に大きなずれが生じた場合、一つの領域150a内に2つのスタッドバンプ121が含まれてしまうことになる。このようなずれが生じた場合、最終的にこれら2つのスタッドバンプ121は配線パターン150によって短絡されるため、ショート不良となってしまう。
A>B
に設定することにより解決できる。これによれば、ドライフィルム101のパターニング時に多少のずれが生じたとしても、一つの領域150a内に2つのスタッドバンプ121が含まれてしまう可能性を低減することができる。具体的には、
A=B
である場合と比べ、
A−B
で与えられる距離だけマージンが拡大する。したがって、実現可能なマージンをXとすると、
B<A−X
を満たすように領域150aの幅Bを設定すれば、隣り合うスタッドバンプ121のショートを確実に防止することが可能となる。
A>B
に設定することは必須でなく、図12に示す例のように、
A<B、又は
A=B
であっても構わない。
A>B
に設定することが好ましい。
101,102,201,202 ドライフィルム
111〜114,211〜214 樹脂層
112a,113a,114a,114b,211a,213a,213b,214a 貫通孔
120,220 半導体IC
120a,220a 半導体ICの主面
120b,220b 半導体ICの裏面
120c,220c 半導体ICの側面
121,221 スタッドバンプ
121a パッド電極
122,222 金属層
130,230 アライメントマーク
130a 凹部
140,150,161,162,250,261,262 配線パターン
140a,171,172,230a,271,261,262,270,271,272 導体層
150a,250a 導体層を形成すべき領域
151,160,251,260 下地導体層
152,163〜165,252,263〜265 貫通電極
181,182,281 支持基板
229 ダイアタッチフィルム
301 金型
302 突起
Claims (18)
- 主面に導電性突起物が設けられた半導体ICと、前記半導体ICの前記主面を覆う第1の樹脂層と、前記半導体ICの裏面を覆う第2の樹脂層とを備え、前記半導体ICの前記導電性突起物は、前記第1の樹脂層の表面から突出していることを特徴とする半導体IC内蔵基板。
- 前記第1及び第2の樹脂層の少なくとも一方は、前記半導体ICの側面に接触していることを特徴とする請求項1に記載の半導体IC内蔵基板。
- 前記第1の樹脂層は前記半導体ICの前記主面に接触しており、前記第2の樹脂層は前記半導体ICの前記裏面に接触していることを特徴とする請求項1又は2に記載の半導体IC内蔵基板。
- 前記半導体ICの前記主面及び前記裏面のいずれか一方にはダイアタッチフィルムが設けられており、前記半導体ICの前記主面及び前記裏面の前記一方は、前記ダイアタッチフィルムを介して前記第1及び第2の樹脂層のいずれか一方に覆われていることを特徴とする請求項1又は2に記載の半導体IC内蔵基板。
- 前記第1及び第2の樹脂層を貫通して設けられた貫通電極をさらに備えることを特徴とする請求項1乃至4のいずれか一項に記載の半導体IC内蔵基板。
- 前記第1の樹脂層の前記表面に形成され、前記導電性突起物に接続された配線パターンをさらに備え、前記配線パターンの前記導電性突起物上における幅が、前記導電性突起物の突出部分の径よりも小さいことを特徴とする請求項1乃至5のいずれか一項に記載の半導体IC内蔵基板。
- 前記半導体ICが薄型化されていることを特徴とする請求項1乃至6のいずれか1項に記載の半導体IC内蔵基板。
- 主面に導電性突起物が設けられた半導体ICを第1及び第2の樹脂層によって挟み込む第1の工程と、
前記第1の樹脂層の厚さを減少させることにより、前記半導体ICの前記導電性突起物を前記第1の樹脂層の一方の表面から突出させる第2の工程と、
前記第1の樹脂層の前記一方の表面に配線パターンを形成する第3の工程とを備えることを特徴とする半導体IC内蔵基板の製造方法。 - 前記第2の工程は、前記第1の樹脂層の前記一方の面をウエットブラスト処理することによって厚さを減少させることを特徴とする請求項8に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程は、前記第1の樹脂層の他方の面と前記半導体ICの前記主面とが向き合うようこれらを重ねる工程と、前記第2の樹脂層の一方の面と前記半導体ICの裏面とが向き合うようこれらを重ねる工程とを含むことを特徴とする請求項8又は9に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程においては、前記第1の樹脂層の前記一方又は他方の面に形成されたアライメントマークを基準として、前記半導体ICを前記第1の樹脂層の前記他方の面に搭載することを特徴とする請求項10に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程は、前記第1の樹脂層の前記一方の面側に支持基板を貼り付けた状態で行うことを特徴とする請求項10又は11に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程を行った後、前記第2の工程を行う前に、前記第2の樹脂層の他方の面側に他の支持基板を貼り付ける工程と、前記第1の樹脂層の前記一方の面側から前記支持基板を剥離する工程を行うことを特徴とする請求項12に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程は、前記第2の樹脂層の一方の面と前記半導体ICの裏面とが向き合うようこれらを重ねる工程と、前記第1の樹脂層の他方の面と前記半導体ICの前記主面とが向き合うようこれらを重ねる工程とを含むことを特徴とする請求項8又は9に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程においては、前記第2の樹脂層前記一方又はの他方の面に形成されたアライメントマークを基準として、前記半導体ICを前記第2の樹脂層の前記一方の面に搭載することを特徴とする請求項14に記載の半導体IC内蔵基板の製造方法。
- 前記第1の工程は、前記第2の樹脂層の他方の面側に支持基板を貼り付けた状態で行うことを特徴とする請求項14又は15に記載の半導体IC内蔵基板の製造方法。
- 前記第3の工程においては、前記配線パターンの前記導電性突起物上における幅を、前記導電性突起物の突出部分の径よりも小さく設定することを特徴とする請求項8乃至16のいずれか一項に記載の半導体IC内蔵基板の製造方法。
- 前記第1及び第2の樹脂層を貫通する貫通電極を形成する第4の工程をさらに備えることを特徴とする請求項8乃至17のいずれか一項に記載の半導体IC内蔵基板の製造方法。
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JP4535002B2 (ja) | 2010-09-01 |
US7544537B2 (en) | 2009-06-09 |
KR20070036007A (ko) | 2007-04-02 |
KR101176814B1 (ko) | 2012-08-24 |
CN1941339B (zh) | 2011-09-14 |
EP1770776B1 (en) | 2015-08-12 |
US20070069363A1 (en) | 2007-03-29 |
US20090218678A1 (en) | 2009-09-03 |
CN1941339A (zh) | 2007-04-04 |
TW200721419A (en) | 2007-06-01 |
US8026614B2 (en) | 2011-09-27 |
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EP1770776A3 (en) | 2007-12-05 |
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