JP6033872B2 - 部品内蔵基板の製造方法 - Google Patents
部品内蔵基板の製造方法 Download PDFInfo
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- JP6033872B2 JP6033872B2 JP2014535251A JP2014535251A JP6033872B2 JP 6033872 B2 JP6033872 B2 JP 6033872B2 JP 2014535251 A JP2014535251 A JP 2014535251A JP 2014535251 A JP2014535251 A JP 2014535251A JP 6033872 B2 JP6033872 B2 JP 6033872B2
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- H—ELECTRICITY
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- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/06—Wires; Strips; Foils
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Description
本発明においては、まず、出発素材上に銅製の柱状体からなる位置決め用のマークを形成する(マーク形成工程)。ここで、出発素材は、例えば、次のようにして準備される。
まず、図5に示すように、銅層4上における搭載予定領域Sに接着剤16が供給される。接着剤16は、少なくとも搭載予定領域Sの全体を覆っていればよく、接着剤16の位置決め精度は、比較的低くてもよい。ここで、接着剤16の位置決めを行う際、マーク12を基準にして搭載予定領域Sを特定し、特定された位置に接着剤16を塗布すると接着剤16の位置決め精度は向上するので好ましい。なお、基板内部品14の端子が存在する位置に対応する所定位置に接着剤16が適切に配設されるならば、接着剤16は、搭載予定領域Sの一部を覆う態様でも構わない。
まずは、図7に示すように、第1及び第2の絶縁基材22,24を用意する。これら絶縁基材22,24は、樹脂製である。ここで、絶縁基材22,24は、ガラス繊維に未硬化状態の熱硬化性樹脂を含浸させたシート状をなすいわゆるプリプレグである。この第1の絶縁基材22は、貫通孔30を有している。貫通孔30は、その開口部が基板内部品14を挿通可能な大きさに形成されているとともに、その高さ(絶縁基材22の厚さに相当)が基板内部品14の高さよりも高く設定されている。一方、第2の絶縁基材24は、図7に示すように、貫通孔が設けられていない平板状をなしている。
まずは、図10に示すように、両銅層4,28の表面にマスク層39,41を形成する。このマスク層39,41は、例えば、所定厚みのドライフィルムからなるエッチングレジストであり、所定位置に開口43が設けられている。開口43からは銅層4の第1面3が露出している。開口43は、マーク12,12が存在する部分及び基板内部品14の端子20,20が存在する部分(以下、端子存在部という)T,Tにそれぞれ設けられている。ここで、これら開口43は、例えば、絶縁基板34の端部を基準にして、マーク12,12が存在する部分及びを端子存在部T,Tを特定し、その特定した位置において、マーク12,12及び端子20,20よりも大きめに形成されている。この開口43は、マーク12や端子20よりも大きめに形成されるので、その位置を特定する際の精度は、比較的低くても構わない。
まず、露出したマーク12,12を光学系位置決め装置(図示せず)の光学系センサーで認識する。そして、マーク12,12の位置を基準として接着層18で隠れている基板内部品14の端子20の位置を特定する。その後、特定した端子位置の接着層18にレーザー、例えば、炭酸ガスレーザーを照射して接着層18を除去し、図12に示すように、端子20まで到達するレーザービアホール(以下、LVHという)46を形成する。これにより、基板内部品14の端子20が露出する。ここで、各ウィンドウW1、W2をマーク12,12及び端子20,20よりも大きめに形成しているので、第1ウィンドウW1では、マーク12,12の全体を認識することができ、第2ウィンドウW2では、銅層4により反射されることなく効率良く目標箇所にレーザーを照射することができる。
両銅層4,28の一部の除去は、通常のエッチング法が用いられる。これにより、図14に示すように、絶縁基板34の表面に所定の配線パターン50が形成される。
第2の実施形態は、第1の実施形態のマーク形成工程において、ニッケル−金めっき層によりマーク12を形成する点のみで第1の実施形態と相違する。
第3の実施形態は、第1の実施形態のマーク形成工程において、銀めっき層によりマーク12を形成する点のみで第1の実施形態と相違する。
第4の実施形態は、第1の実施形態のマーク形成工程において、銀ペーストを用いてマーク12を形成する点のみで第1の実施形態と相違する。
第5の実施形態は、第1の実施形態において、部品実装用ランドを形成する際に、銅のめっき層48の上にニッケルめっき層64を形成し、更に、このニッケルめっき層64の上に金めっき層66を形成する点のみで第1の実施形態と相違する。
第5の実施形態においては、図17に示すように、部品実装用ランド61における銅めっき層48がエッチング耐性を備えたニッケルめっき層64及び金めっき層66により覆われているので、部品実装用ランド61の耐食性向上が図れる。
上記したように、第1〜第5の実施形態におけるマーク12は、ニッケル、ニッケル−金、銀又は銀ペーストからなり、いずれも、硫酸−過酸化水素系エッチング剤、塩化第2銅水溶液、塩化第2鉄水溶液等の銅エッチング剤に対し、銅よりも腐食され難いエッチング耐性を備えている。このため、銅の粗面化及び銅のエッチングに際し、マーク12が一緒に腐食されることはない。つまり、マーク12は、当初の形状を維持することができるので、部品の位置決め精度及び端子位置の特定の精度の向上に寄与する。
2 支持板
3 第1面
4 第1の銅層
5 第2面
6 銅張り鋼板
8 マスク層
12 マーク
14 電子部品(基板内部品)
16 接着剤
18 接着層
20 端子
34 絶縁基板
40 中間製品
46 レーザービアホール(LVH)
47 導通ビア
50 配線パターン
S 搭載予定領域
T 端子存在部
Claims (6)
- 表面に配線パターンを有する絶縁基板内に、前記配線パターンと電気的に接続された端子を有する電気又は電子的な部品が内蔵されている部品内蔵基板の製造方法であって、
支持板上に前記配線パターンとなるべき銅層を形成し、この銅層の前記支持板に接する第1面とは反対側の第2面にマークを形成するマーク形成工程と、
前記マークを基準にして前記部品を位置決めし、絶縁性の接着層を介在させて前記銅層の第2面上に前記部品を搭載する部品搭載工程と、
前記部品を搭載した前記銅層の第2面上に、前記部品及び前記マークを埋設させる前記絶縁基板としての埋設層を形成する埋設層形成工程と、
前記銅層から前記支持板を剥離させた後、この剥離により露出した前記銅層の第1面側から前記銅層の一部を銅のエッチングに用いられる銅エッチング剤によりエッチング除去し、前記マークにおける前記銅層の第2面に接していた基端面の全体とともに前記埋設層を部分的に露出させるウィンドウを形成するウィンドウ形成工程と、
前記ウィンドウから露出した前記マークを基準にして前記部品の端子の位置を特定し、前記端子まで到達するビアホールを形成した後、前記ビアホールに導電性材料を充填し、前記端子と前記銅層とを電気的に接続する導通ビアを形成する導通ビア形成工程と、
前記導通ビアを介して前記端子と電気的に接続された前記銅層を前記配線パターンに形成するパターン形成工程とを備えており、
前記マーク形成工程は、前記銅エッチング剤に対して、銅よりもエッチングされ難いエッチング耐性を有しているエッチング耐性材料を用いて前記マークを形成することを特徴とする部品内蔵基板の製造方法。 - 前記部品搭載工程の前に、前記銅層の第2面に対し前記銅エッチング剤を用いて粗面化処理を施す粗面化工程を更に備えていることを特徴とする請求項1に記載の部品内蔵基板の製造方法。
- 前記マーク形成工程は、前記エッチング耐性材料としてのニッケルのめっき層からなる前記マークを無電解めっき法及び電解めっき法のうちの少なくとも一方により形成することを特徴とする請求項1又は2に記載の部品内蔵基板の製造方法。
- 前記ニッケルのめっき層の上に、無電解めっき法及び電解めっき法のうちの少なくとも一方により、前記エッチング耐性材料としての金のめっき層を更に設け、前記マークをニッケル−金めっき層により形成することを特徴とする請求項3に記載の部品内蔵基板の製造方法。
- 前記マーク形成工程は、前記エッチング耐性材料としての銀のめっき層からなる前記マークを無電解めっき法及び電解めっき法のうちの少なくとも一方により形成することを特徴とする請求項1又は2に記載の部品内蔵基板の製造方法。
- 前記マーク形成工程は、前記エッチング耐性材料としての銀ペーストを前記銅層上に供給することにより前記マークを形成することを特徴とする請求項1又は2に記載の部品内蔵基板の製造方法。
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CN102204418B (zh) | 2008-10-30 | 2016-05-18 | At&S奥地利科技及系统技术股份公司 | 用于将电子部件集成到印制电路板中的方法 |
JP5603600B2 (ja) * | 2010-01-13 | 2014-10-08 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体パッケージ |
JP5659234B2 (ja) | 2010-09-10 | 2015-01-28 | 株式会社メイコー | 部品内蔵基板 |
EP2624672A4 (en) * | 2010-10-01 | 2014-11-26 | Meiko Electronics Co Ltd | METHOD FOR PRODUCING A SUBSTRATE WITH INTEGRATED COMPONENT AND SUBSTRATE PRODUCED BY THIS PROCESS WITH INTEGRATED COMPONENT |
KR20140089386A (ko) * | 2011-11-08 | 2014-07-14 | 메이코 일렉트로닉스 컴파니 리미티드 | 부품내장기판의 제조방법 및 이 방법을 이용하여 제조한 부품내장기판 |
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2012
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- 2012-09-11 WO PCT/JP2012/073204 patent/WO2014041601A1/ja active Application Filing
- 2012-09-11 US US14/426,364 patent/US9596765B2/en not_active Expired - Fee Related
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TW201419969A (zh) | 2014-05-16 |
WO2014041601A1 (ja) | 2014-03-20 |
JPWO2014041601A1 (ja) | 2016-08-12 |
EP2897447A1 (en) | 2015-07-22 |
EP2897447A4 (en) | 2016-05-25 |
US9596765B2 (en) | 2017-03-14 |
TWI549582B (zh) | 2016-09-11 |
US20150223343A1 (en) | 2015-08-06 |
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