JP2015536046A - コアレス基板内に埋め込みrfダイを有するシステムインパッケージ - Google Patents
コアレス基板内に埋め込みrfダイを有するシステムインパッケージ Download PDFInfo
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Abstract
Description
Claims (24)
- 複数の誘電体層及び複数の導電性パスを含むコアレス基板であって、第1面及び前記第1面の反対側の第2面を含むコアレス基板と、
前記コアレス基板内に埋め込まれた第1のダイであって、RFダイを含み、前記コアレス基板の前記第1面に延びる誘電体層内に位置する第1のダイと、
前記第1面上に位置する第2のダイであって、前記第1のダイ上に位置する前記第2のダイと、
を備えるアセンブリ。 - 前記ダイの面上に位置するモールド材料と、
前記第1面の上方に位置する電気遮蔽層と
をさらに備え、
前記第1のダイ及び前記第2のダイは、前記モールド材料に覆われる請求項1に記載のアセンブリ。 - 前記コアレス基板内に埋め込まれた第3のダイであって、前記第1のダイと同一の誘電体層内に位置する第3のダイと、
前記コアレス基板の前記第1面上の前記第3のダイ上に位置する第4のダイと
をさらに備える請求項1又は2に記載のアセンブリ。 - 前記コアレス基板のランド面上の複数の相互接続パッドとプリント回路基板とをさらに備え、
前記コアレス基板は、前記複数の相互接続パッドを介して前記プリント回路基板に電気的に結合される
請求項1から3のいずれか一項に記載のアセンブリ。 - 前記第1のダイは、アクティブ面と裏面とを含み、前記第1のダイの前記アクティブ面は、前記第1のダイの前記裏面と前記コアレス基板の前記第2面との間に位置する
請求項1から4のいずれか一項に記載のアセンブリ。 - 前記第2のダイを前記コアレス基板に電気的に結合させる複数のワイヤボンドをさらに備える
請求項1から5のいずれか一項に記載のアセンブリ。 - 前記第2のダイは、電力増幅器を備え、前記第2のダイは、前記第1のダイに電気的に結合する
請求項1から6のいずれか一項に記載のアセンブリ。 - 前記第2のダイは、アクティブ面と裏面とを含み、前記第2のダイの前記裏面は、前記第1のダイの前記裏面に対向する
請求項1から7のいずれか一項に記載のアセンブリ。 - 前記第2のダイの少なくとも一部は、前記第1のダイの上方に直接位置する
請求項1から8のいずれか一項に記載のアセンブリ。 - 前記第2のダイは、アクティブ面と裏面とを含み、前記第2のダイの前記アクティブ面は、前記第1のダイの前記裏面に対向する
請求項1から9のいずれか一項に記載のアセンブリ。 - 前記第2のダイと、前記コアレス基板の裏面との間に間隙をさらに備える
請求項1から10のいずれか一項に記載のアセンブリ。 - 前記第1のダイは、その前記裏面上の金属被膜層を含む
請求項5に記載のアセンブリ。 - 第1面と第2面とを含むコアレス基板と、
前記コアレス基板内の誘電体層に埋め込まれた第1のダイであって、RFダイを含む第1のダイと、
前記コアレス基板の前記第1面上に位置する第2のダイであって、前記第1のダイに電気的に結合する第2のダイと、
を備え、
前記第1のダイは、複数の誘電体層によって前記第2面と分離され、
上から見た場合に、前記第2のダイが前記第1のダイの少なくとも一部を覆うように、前記第2のダイが前記第1のダイと位置合わせされるアセンブリ。 - 前記第1面上に位置するモールド材料と、
前記第1面上の前記モールド材料に連結される電気遮蔽構造と
をさらに備え、
前記第1のダイ及び前記第2のダイは、前記モールド材料に覆われる
請求項13に記載のアセンブリ。 - 前記第1のダイは、金属被膜層と、その上にダイ接着フィルムとを含み、
前記第2のダイは、金属被膜層と、その上にダイ接着フィルムとを含み、
前記第2のダイの前記ダイ接着フィルムは、前記第1のダイの前記ダイ接着フィルムと接触して配置される
請求項13又は14に記載のアセンブリ。 - 前記第1のダイは、前記コアレス基板の前記第1面に延びる誘電体層内に位置する
請求項13から15のいずれか一項に記載のアセンブリ。 - 前記誘電体層内に埋め込まれた第3のダイと、
前記コアレス基板の前記ダイの接着面上に位置する第4のダイと
をさらに備える
請求項13から16のいずれか一項に記載のアセンブリ。 - 第1面と前記第1面の反対側の第2面と含むコアレス基板内の誘電体層内に、RFダイを含み、前記第1面に延伸する誘電体層内に位置する第1のダイを埋め込む段階と、
前記コアレス基板の前記第1面上に、前記第1のダイの上方に位置する第2のダイを配置する段階と、
前記基板の前記第1面上に、前記第1のダイ及び前記第2のダイを覆うモールド層を形成する段階と、
前記ダイの面上に、前記モールド層に連結した電気遮蔽層を提供する段階と
を含む方法。 - 前記第1のダイと同一の前記誘電体層内に第3のダイを埋め込む段階と、
前記コアレス基板の前記第1面上に、前記第3のダイ上に位置する第4のダイを配置する段階と
をさらに備える
請求項18に記載の方法。 - 前記第1のダイのアクティブ面が前記コアレス基板の前記第2面に対向し、前記第1のダイの裏面が前記第2のダイに対向するように、前記第1のダイと前記第2のダイを位置決めする段階をさらに備える
請求項18又は19に記載の方法。 - 前記第2のダイの裏面が前記第1のダイの裏面に対向するように、前記第2のダイを位置決めする段階をさらに備える
請求項18から20のいずれか一項に記載の方法。 - 前記第2のダイのアクティブ面が前記第1のダイの裏面に対向するように、前記第2のダイを位置決めする段階をさらに備える
請求項18から21のいずれか一項に記載の方法。 - 前記第1面上に窪み領域をさらに備え、
前記窪み領域内に、前記第2のダイから前記コアレス基板に複数の電気接続が形成される
請求項18から22のいずれか一項に記載の方法。 - 前記第2のダイは、前記コアレス基板の前記第1面から離れて間隔が空けられる
請求項18から23のいずれか一項に記載の方法。
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US13/631,982 US20140091440A1 (en) | 2012-09-29 | 2012-09-29 | System in package with embedded rf die in coreless substrate |
US13/631,982 | 2012-09-29 | ||
PCT/US2013/048780 WO2014051816A1 (en) | 2012-09-29 | 2013-06-28 | System in package with embedded rf die in coreless substrate |
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JP (1) | JP6097837B2 (ja) |
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CN104221146A (zh) | 2014-12-17 |
DE112013000419T5 (de) | 2014-09-18 |
JP6097837B2 (ja) | 2017-03-15 |
KR101629120B1 (ko) | 2016-06-09 |
KR101709579B1 (ko) | 2017-02-23 |
KR20140098828A (ko) | 2014-08-08 |
WO2014051816A1 (en) | 2014-04-03 |
US20140091440A1 (en) | 2014-04-03 |
DE112013000419B4 (de) | 2024-04-11 |
KR20160066012A (ko) | 2016-06-09 |
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