JP2011181861A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】1又は複数の電極12A、12B、22A、22Bを有し、上下に配列された複数の半導体構成体10、20と、上面に最下部の半導体構成体10が固定される絶縁膜30と、絶縁膜30の上面に設けられ、各電極12A、12B、22A、22Bのいずれかにそれぞれ接続される複数の配線41〜44と、を備え、最下部の半導体構成体10は電極12A、12Bを下に向け、かつ電極12A、12Bを接続される配線41、42と上部に重ねて配置され、他の半導体構成体20の電極22A、22Bは、ボンディングワイヤー24、25によりいずれかの配線43、44と接続される。
【選択図】図1
Description
好ましくは、前記最下部及び最上部の半導体構成体を除いた中間部の半導体構成体は電極を、隣接する半導体構成体と重ならないように配置されている。
好ましくは、前記複数の配線は、前記絶縁膜の前記半導体構成体が固定される面に埋め込まれている。
好ましくは、前記複数の半導体構成体、前記複数の配線及び前記ボンディングワイヤーを封止する封止層を備える。
好ましくは、前記絶縁膜及び前記配線は、ビルドアップ法により多層化されている。
絶縁膜及び配線が形成されたキャリアーの前記配線が形成された面に、電極を下に向けて最下部の半導体構成体を接着する第1工程と、
前記最下部の半導体構成体の上部に、電極を上に向けて他の1又は複数の半導体構成体を重ねて接着する第2工程と、
前記いずれかの配線と前記他の1又は複数の半導体構成体の電極とをボンディングワイヤーにより接続する第3工程と、
を含むことを特徴とする半導体装置の製造方法が提供される。
上記半導体装置の製造方法は、
前記複数の半導体構成体、前記複数の配線及び前記ボンディングワイヤーを封止する封止層を前記絶縁膜の上部に形成する第4工程と、
前記キャリアーを除去する第5工程と、
前記絶縁膜の下側から前記配線に向けてレーザーを照射することによって前記配線まで到達する穴を形成する第6工程と、
前記絶縁膜の下面及び前記穴の内部に配線を形成する第7工程と、
を含んでもよい。
図1は、本発明の第1の実施形態に係る半導体装置1Aの断面図である。この半導体装置1Aは、半導体構成体10、20を重ねた状態でパッケージしたものである。半導体構成体10、20は、それぞれ半導体チップ11、21及び複数の電極12A〜12D、22A、22Bを備える。半導体チップ11、21は、シリコン基板の半導体基板に集積回路を設けたものである。複数の電極12A〜12D、22A、22Bは半導体チップ11、21の互いに対向する面の反対側の一方の面に設けられている。電極12A〜12D、22A、22Bは、Cuからなるものである。なお、電極12A〜12D、22A、22Bは、配線の一部であってもよい。
絶縁膜30には、導体からなる埋め込み配線41、42、43、44が上面に設けられている。配線を埋め込むことで、絶縁膜30の表面を平坦にすることができる。
埋め込み配線41、42は、それぞれ一端が電極12A、12Bと対応する位置に配置されている。当該端部には貫通穴41A、42Bが設けられている。貫通穴41A、42Bの大きさはビアホール13A、13Bの大きさに等しい。
埋め込み配線43はボンディングワイヤー24により電極22Aと、埋め込み配線44はボンディングワイヤー25により電極22Bと、それぞれ接続されている。
ビアホール35〜38には、コンタクト部55〜58を構成する導体が充填されている。コンタクト部55は埋め込み配線41と、コンタクト部56は埋め込み配線42と、コンタクト部57は埋め込み配線43と、コンタクト部58は埋め込み配線44と、それぞれ導通している。
なお、開口部63〜68内において、コンタクト部53〜58の表面には、メッキ(例えば、金メッキからなる単層メッキ、或いはニッケルメッキ・金メッキからなる二層メッキ等)が形成されていてもよい。
キャリアー90は、半導体装置1Aとなる部材、例えば複数の半導体構成体10を載置、貼着或いは接着して搬送するためのキャリアーであり、具体的には銅箔である。
次に、図4に示すように、ボンディングワイヤー24、25により電極22A、22Bと埋め込み配線43、44とを接続する。このとき、半導体構成体20の電極22A、22Bが上向きであるため、ボンディングワイヤー24、25により容易に接続することができる。
次に、図6に示すように、キャリアー90をエッチング(例えば、ウェットエッチング等のケミカルエッチング)或いは物理的な引き剥がしによって除去する。キャリアー90を除去しても、封止層29及び絶縁膜30の積層構造により、十分な強度を確保することができる。
次に、ビアホール13A〜13D、スルーホール31、32、ビアホール33〜38内をデスミア処理する。
図13は、本発明の第2の実施形態に係る半導体装置1Bの断面図である。なお、第1実施形態と同様の構成については、下2桁に同符号を付して説明を割愛する。
本実施形態においては、埋め込み配線41、42、43、44がない。絶縁膜130には、半導体構成体110の電極112A〜112Dと対応する位置にそれぞれスルーホール131〜134が形成されている。ビアホール113A〜113D及びスルーホール131〜134にはコンタクト部151〜154を構成する導体が充填されている。コンタクト部151〜154により、電極112Aと半田バンプ171、電極112Bと半田バンプ172、電極112Cと半田バンプ173、電極112Dと半田バンプ174、がそれぞれ導通している。
図17は本発明の第3実施形態に係る半導体装置1Cを示す断面図である。なお、第2実施形態と同様の構成については同符号を付して説明を割愛する。
本実施形態に係る半導体装置1Cでは、第1の絶縁層130A、コンタクト部151A〜156Aに加えて、さらに第2の絶縁層130B、コンタクト部151B〜156Bが形成されている。また、第2の絶縁層130Bの下面にソルダーレジスト160がパターニングされ、コンタクト部151B〜156Bに端子処理後、半田バンプ171〜176が形成されている。
図18は本発明の第4実施形態に係る半導体装置1Dを示す断面図である。なお、第2実施形態と同様の構成については同符号を付して説明を割愛する。
本実施形態に係る半導体装置1Dでは、半導体チップ111の上面に接着樹脂層123Aが塗布され、その上に電極122A、122Bを上側に向けた状態で半導体構成体120Aがボンディングされている。さらに、半導体構成体120Aの半導体チップ121Aの上部に接着樹脂層123Bが塗布され、その上に電極122C、122Dを上側に向けた状態で半導体構成体120Bの半導体チップ121Bがボンディングされている。なお、半導体構成体120Aの電極122A、122Bは、隣接する半導体構成体120Bと重ならないように配置されているので、ボンディングワイヤー124、125により容易に接続パッド145、146と接続することができる。
すなわち、図19(a)に示すように、半導体チップ11の下面に形成された複数の電極12A、12Bを、絶縁コート14により覆ってもよい。
また、図19(b)に示すように、複数の電極12A、12Bに、ギャップや厚さの調整をするために、金属パッド15A、15Bを設けてもよい。さらに、図19(c)に示すように、電極12A、12B及び金属パッド15A、15Bを絶縁コート14により覆ってもよい。
10、20、110、120、120A、120B 半導体構成体
11、21、111、121 半導体チップ
12A〜12D、22A、22B、122A〜122D 電極
13、23、113、123、123A、123B 接着樹脂層
13A〜13D、33〜38 ビアホール
24、25 ボンディングワイヤー
29 封止層
30、130、130A、130B 絶縁層
31、32、131〜134 スルーホール
41〜44 埋め込み配線
41A、42B 貫通穴
50 金属メッキ膜
51〜58、151〜156、151A〜156A、151B〜156B コンタクト部
60 ソルダーレジスト
63〜68 開口部
73〜78、171〜178 半田バンプ
90 基材
145〜148 接続パッド
Claims (8)
- 1又は複数の電極を有し、上下に配列された複数の半導体構成体と、
上面に最下部の前記半導体構成体が固定される絶縁膜と、
前記絶縁膜の上面に設けられ、前記各電極のいずれかにそれぞれ接続される複数の配線と、を備え、
前記最下部の半導体構成体は電極を下に向け、かつ電極を接続される配線と上部に重ねて配置され、
前記他の半導体構成体の電極は、ボンディングワイヤーにより前記いずれかの配線と接続されることを特徴とする半導体装置。 - 前記最下部の半導体構成体を除く他の半導体構成体は電極を上に向けて配置されることを特徴とする請求項1に記載の半導体装置。
- 前記最下部及び最上部の半導体構成体を除いた中間部の半導体構成体の電極は、当該中間部の半導体構成体上の半導体構成体と重ならないように配置されていることを特徴とする請求項1または2に記載の半導体装置。
- 前記複数の配線は、前記絶縁膜の前記半導体構成体が固定される面に埋め込まれていることを特徴とする請求項1〜3のいずれか一項に記載の半導体装置。
- 前記複数の半導体構成体、前記複数の配線及び前記ボンディングワイヤーを封止する封止層を備えることを特徴とする請求項1〜4のいずれか一項に記載の半導体装置。
- 前記絶縁膜及び前記配線は、ビルドアップ法により多層化されていることを特徴とする請求項1〜5のいずれか一項に記載の半導体装置。
- 絶縁膜及び配線が形成されたキャリアーの前記配線が形成された面に、電極を下に向けて最下部の半導体構成体を接着する第1工程と、
前記最下部の半導体構成体の上部に、電極を上に向けて他の1又は複数の半導体構成体を重ねて接着する第2工程と、
前記いずれかの配線と前記他の1又は複数の半導体構成体の電極とをボンディングワイヤーにより接続する第3工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記複数の半導体構成体、前記複数の配線及び前記ボンディングワイヤーを封止する封止層を前記絶縁膜の上部に形成する第4工程と、
前記キャリアーを除去する第5工程と、
前記絶縁膜の下側から前記配線に向けてレーザーを照射することによって前記配線まで到達する穴を形成する第6工程と、
前記絶縁膜の下面及び前記穴の内部に配線を形成する第7工程と、
を含むことを特徴とする請求項7に記載の半導体装置の製造方法。
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