WO2016199437A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2016199437A1
WO2016199437A1 PCT/JP2016/002851 JP2016002851W WO2016199437A1 WO 2016199437 A1 WO2016199437 A1 WO 2016199437A1 JP 2016002851 W JP2016002851 W JP 2016002851W WO 2016199437 A1 WO2016199437 A1 WO 2016199437A1
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Prior art keywords
chip
semiconductor device
semiconductor chip
semiconductor
terminal
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PCT/JP2016/002851
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English (en)
French (fr)
Inventor
山田　隆史
Original Assignee
株式会社ソシオネクスト
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Publication date
Application filed by 株式会社ソシオネクスト filed Critical 株式会社ソシオネクスト
Priority to JP2017523120A priority Critical patent/JPWO2016199437A1/ja
Publication of WO2016199437A1 publication Critical patent/WO2016199437A1/ja
Priority to US15/838,180 priority patent/US10269774B2/en

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present disclosure relates to a semiconductor device on which a stacked body of semiconductor chips is mounted.
  • a structure in which a plurality of semiconductor chips are stacked and mounted is used.
  • a stacked structure of semiconductor chips for example, a chip-on-chip (COC) connection structure for connecting terminals provided on a circuit forming surface of a plurality of semiconductor chips is known.
  • COC chip-on-chip
  • Patent Document 1 shows a structure in which a chip extension portion is provided so as to surround a peripheral portion of a lower semiconductor chip in a chip-on-chip structure.
  • a wiring connected to the terminal of the lower semiconductor chip is provided on the chip extension portion, and the wiring and the external electrode of the package substrate are connected by a bonding wire.
  • Patent Document 2 shows a structure in which a second semiconductor chip is mounted on a first semiconductor chip embedded in a resin layer so as to expose a terminal in a chip-on-chip structure.
  • a wiring layer connected to an external terminal of the semiconductor device is provided on the surface of the resin layer, and terminals such as bumps of the second semiconductor chip are connected to this wiring layer.
  • the terminals of the semiconductor chip and the external electrodes of the package substrate are connected by bonding wires. For this reason, a space and a region for wire bonding are required, so that further miniaturization is difficult. Further, since the bonding wire has a high impedance and a large LC component, it is not suitable for ultrahigh-speed signal transmission of about 10 Gbps, for example. Also, in terms of power supply, a power supply voltage drop tends to occur in the semiconductor chip. Also, the manufacturing process is complicated.
  • the problem in the configuration of Patent Document 1 is solved temporarily.
  • the electrical path from the second semiconductor chip to the external terminal of the semiconductor device includes terminals such as bumps of the second semiconductor chip and a wiring layer provided on the surface of the resin layer in which the first semiconductor chip is embedded. Contains. For this reason, there are problems that the frequency band characteristics are deteriorated due to the impedance at the junction between the terminal and the wiring layer, and that a voltage drop is likely to occur because the current allowable value of the terminal such as a bump is low.
  • This disclosure is intended to provide a semiconductor device including a chip-on-chip structure that has a high density and a small size and is suitable for high-speed operation.
  • a semiconductor device in one aspect of the present invention, includes a support and a first terminal portion provided with a plurality of terminals on a main surface, and a back surface is mounted on the surface of the support.
  • the semiconductor chip has a second terminal portion provided with a plurality of terminals on the main surface, the main surface faces the main surface of the first semiconductor chip, and each terminal of the second terminal portion Comprises a second semiconductor chip connected to each terminal of the first terminal portion of the first semiconductor chip, and an external terminal, the first semiconductor chip comprising the external terminal and a single metal. Connected by conductors.
  • the first semiconductor chip and the external terminal of the semiconductor device are connected by the conductor made of a single metal.
  • the impedance in the electrical path from the first semiconductor chip to the external terminal of the semiconductor device is lowered, and the LC component is also kept low. Therefore, signal attenuation and power supply voltage drop in this electrical path are suppressed, so that the semiconductor device can operate at high speed.
  • a semiconductor device including a chip-on-chip structure can be realized with a high density and a small size and suitable for high speed operation.
  • FIG. 3 is a plan view illustrating a configuration example of the semiconductor device according to the first embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • Sectional drawing which shows the structural example of the semiconductor device which concerns on 2nd Embodiment.
  • Sectional drawing which shows the structural example of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows the other example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows the other example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows the other example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • Process sectional drawing which shows the other example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.
  • the top view which shows the structural example of the semiconductor device which concerns on 3rd Embodiment.
  • Sectional drawing which shows the structural example of the semiconductor device which concerns on 4th Embodiment.
  • Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment Sectional drawing which shows the structural example of the semiconductor device which concerns on 5th Embodiment.
  • Sectional drawing which shows the other structural example of the semiconductor device which concerns on 5th Embodiment. Sectional drawing which shows the other structural example of the semiconductor device which concerns on 5th Embodiment. Sectional drawing which shows the structural example of the semiconductor device which concerns on a modification
  • the semiconductor device described here includes a chip-on-chip (COC) connection structure that connects terminals such as micro bumps provided on the main surface (circuit formation surface) of a plurality of semiconductor chips.
  • COC chip-on-chip
  • FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor device according to the first embodiment. Note that FIG. 1 and the subsequent cross-sectional views are diagrams schematically showing a cross-section of the main part of the semiconductor device.
  • the first semiconductor chip 10 is mounted on the surface of the support 1.
  • the support 1 may be a metal or a substrate such as an organic material or glass epoxy.
  • the first semiconductor chip 10 is, for example, a SoC (System on Chip) and has an integrated circuit such as a logic or a memory.
  • the first semiconductor chip 10 is bonded to the support 1 with an adhesive 8 with the circuit formation surface (corresponding to the main surface) facing upward (direction facing the opposite side of the support 1).
  • the lower side of the drawing is the upper side of the semiconductor device
  • the upper side of the drawing is the lower side of the semiconductor device.
  • the following configuration cross-sectional views are the same unless otherwise specified.
  • the black triangles written in the semiconductor chip indicate which surface of the semiconductor chip is the main surface, and the surface pointed by the vertex of the black triangle is the main surface of the semiconductor chip.
  • the first semiconductor chip 10 is provided with a plurality of terminals 11 made of micro-bump electrodes or pillar electrodes made of Cu on the circuit forming surface. A region where the plurality of terminals 11 are provided is referred to as a first terminal portion 12.
  • the second semiconductor chip 20 is mounted such that the circuit formation surface (corresponding to the main surface) faces the main surface of the first semiconductor chip 10.
  • the second semiconductor chip 20 is a memory chip, for example, and has an integrated circuit such as logic or memory.
  • the second semiconductor chip 20 is provided with a plurality of terminals 21 such as pillar electrodes made of Cu, for example, on the circuit formation surface. A region where the plurality of terminals 21 are provided is referred to as a second terminal portion 22.
  • each terminal 21 of the second terminal portion 22 is connected to each terminal 11 of the first terminal portion 12 of the first semiconductor chip 10.
  • the surface area of the second semiconductor chip 20 is assumed to be larger than the surface area of the first semiconductor chip 10.
  • the chip extension 3 is provided so as to surround the peripheral edge of the first semiconductor chip 10.
  • the chip extension portion 3 is formed of, for example, resin and covers a region other than the first terminal portion 12 on the surface of the circuit formation surface of the first semiconductor chip 10 in addition to the peripheral portion of the first semiconductor chip 10. .
  • a wiring 6 is formed on the surface on the second semiconductor chip 20 side, and a via 7 connected to the wiring 6 is formed.
  • the via 7 is formed in a portion of the chip extension portion 3 that covers the circuit formation surface of the first semiconductor chip 10, and is connected to a terminal 15 provided inside the chip of the first semiconductor chip 10.
  • the connected wiring 6 and via 7 are integrally formed as a conductor made of a single metal such as Cu, for example.
  • An external terminal 2 such as a solder ball connected to the wiring 6 is formed on the surface of the chip extension portion 3. Further, a solder resist 5 is formed so as to cover a region of the surface of the chip extension portion 3 where the external terminals 2 are not formed and the back surface and side surfaces of the second semiconductor chip 20. However, this solder resist 5 may be omitted.
  • a filling layer 4 made of resin is formed between the first semiconductor chip 10 and the second semiconductor chip 20. That is, the portion connecting each terminal 11 of the first semiconductor chip 10 and each terminal 21 of the second semiconductor chip 20 is covered with only one layer of resin.
  • FIG. 2 is a plan view showing a configuration example of the semiconductor device according to the present embodiment, and is a view of the configuration of FIG. FIG. 2 schematically shows a principal plane of the semiconductor device.
  • the second semiconductor chip 20 is mounted on the first semiconductor chip 10, and the external output terminal 2 is connected to the first semiconductor chip 10 via the wiring 6 and the via 7.
  • Each terminal 11 of the first semiconductor chip 10 is connected to each terminal 21 of the second semiconductor chip 20.
  • FIG. 3A to FIG. 3F and FIG. 4A to FIG. 4D are process cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • the support 1 is prepared (FIG. 3A), and a thin film of resin 3A having fluidity that becomes the chip extension portion 3 when cured is formed (FIG. 3B).
  • the first semiconductor chip 10 is mounted on the support 1 using the mounter 91 (FIG. 3C).
  • the first semiconductor chip 10 is bonded to the support 1 with an adhesive 8.
  • a resin is poured (FIG. 3D), and the chip expansion portion 3 is formed by curing the resin while flattening the surface of the resin (FIG. 3E).
  • a via 7 connected to an in-chip terminal of the first semiconductor chip 10 is formed inside the chip extension portion 3, and a wiring 6 is formed on the surface of the chip extension portion 3.
  • the via 7 and the wiring 6 are integrally formed of a single metal. For example, it is formed by Cu plating. Further, a passivation film 92 is formed so as to cover the chip extension portion 3 for protection against singulation (FIG. 3F).
  • the passivation film 92 is removed.
  • the filler 4A is applied on the circuit forming surface of the first semiconductor chip 10, and the second semiconductor chip 20 is mounted on the first semiconductor chip 10 (FIG. 4A).
  • the filler 4A is thermocompression bonded to form the filler layer 4, and the second semiconductor chip 20 is fixed (FIG. 4B).
  • a solder resist 5 is formed on the front surface of the chip extension portion 3, the back surface and side surfaces of the second semiconductor chip 20 (FIG. 4C), and external terminals 2 such as solder balls connected to the wiring 6 are formed (FIG. 4). 4D).
  • the first semiconductor chip 10 and the external terminal 2 of the semiconductor device are connected by the via 7 and the wiring 6.
  • the via 7 and the wiring 6 are integrally formed of a single metal by, for example, Cu plating.
  • connection portion between the first semiconductor chip 10 and the second semiconductor chip 20 is covered with one layer of resin.
  • the first semiconductor chip embedded in the resin layer is connected to the second semiconductor chip, and the space between the first semiconductor chip and the second semiconductor is filled with another resin.
  • the connection portion with the chip is covered with two layers of resin.
  • the semiconductor device according to the present embodiment can be realized by a simple manufacturing process.
  • FIG. 5 is a cross-sectional view showing a configuration example of the semiconductor device according to the second embodiment. 5, the basic configuration is substantially the same as that of FIG. 1 in the first embodiment, and the same reference numerals are given to the same components as those in FIG. 1, and the detailed description thereof may be omitted.
  • the support 1 has a recess 31 on the main surface, that is, the surface on which the first semiconductor chip 10 is mounted.
  • the first semiconductor chip 10 is placed in the recess 31.
  • the chip extension part 3 is thinner and the height of the semiconductor device is lower.
  • the thickness of the first semiconductor chip 10 can be kept thicker than that of the first embodiment when realizing a semiconductor device having an equivalent height.
  • the first semiconductor chip 10 is mounted so as to fit into the recess 31 of the support 1. Thereby, the amount of resin for forming the chip extension portion 3 can be reduced. In addition, since it is not necessary to reduce the thickness of the first semiconductor chip 10, a wafer slice polishing process and manufacturing equipment can be omitted, and manufacturing costs can be reduced. Moreover, since the thermal conductivity of the first semiconductor chip 10 can be kept high by keeping the thickness of the first semiconductor chip 10 thick, the thermal conductivity from the upper surface of the semiconductor device can be increased.
  • FIG. 6 is a cross-sectional view illustrating a configuration example of a semiconductor device according to the third embodiment.
  • the basic configuration is almost the same as that of FIG. 1 in the first embodiment, and the same reference numerals are given to the same components as in FIG. 1, and detailed description thereof is omitted here. There is.
  • the first semiconductor chip 10 is provided with a convex portion 32 made of an insulating material such as resin or polyimide on the circuit forming surface.
  • Each terminal 11 in the first terminal portion 12 of the first semiconductor chip 10 is provided on the top surface of the convex portion 32.
  • the support 1 has a recess 31 on the surface on which the first semiconductor chip 10 is mounted, and the first semiconductor chip 10 fits into the recess 31. Has been implemented.
  • the convex portion 32 may be provided on the circuit formation surface of the first semiconductor chip 10.
  • the support 1 has a hole 33 penetrating from the back surface, that is, the surface opposite to the surface on which the first semiconductor chip 10 is mounted, to the inner surface of the recess 31.
  • the hole 33 is used for sucking the resin forming the chip extension portion 3 in the manufacturing process.
  • the hole 33 may be omitted. Further, in the configuration of FIG. 5, the holes 33 may be formed.
  • FIG. 7A to FIG. 7F and FIG. 8A to FIG. 8D are process cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • the support body 1 in which the recessed part 31 and the hole 33 were formed is prepared (FIG. 7A), and if it hardens
  • the mounter 91 the first semiconductor chip 10 having the convex portions 32 formed on the circuit forming surface is mounted on the support 1 (FIG. 7C).
  • the first semiconductor chip 10 is bonded to the support 1 with an adhesive 8.
  • the first semiconductor chip 10 is bonded while sucking excess fluid resin 3A from the hole 33 (FIG. 7D), and the resin is cured while flattening the surface of the resin, thereby extending the chip extension portion. 3 is formed (FIG. 7E).
  • control is performed so that the resin does not flow into the top surface of the convex portion 32.
  • Vias 7 connected to the in-chip terminals of the first semiconductor chip 10 are formed inside the chip extension portion 3, the terminals 11 are formed on the convex portions 32, and the wiring 6 is formed on the surface of the chip extension portion 3. .
  • the via 7 and the wiring 6 are integrally formed of a single metal.
  • a passivation film 92 is formed so as to cover the chip extension portion 3 for protection against singulation (FIG. 7F).
  • the passivation film 92 is removed.
  • the filler 4A is applied on the circuit formation surface of the first semiconductor chip 10, and the second semiconductor chip 20 is mounted on the first semiconductor chip 10 (FIG. 8A).
  • the filler 4A is thermocompression bonded to form the filling layer 4, and the second semiconductor chip 20 is fixed (FIG. 8B).
  • a solder resist 5 is formed on the front surface of the chip extension portion 3, the back surface and side surfaces of the second semiconductor chip 20 (FIG. 8C), and external terminals 2 such as solder balls connected to the wiring 6 are formed (FIG. 8). 8D).
  • FIG. 9A to 9E are process cross-sectional views illustrating another example of the method for manufacturing a semiconductor device according to the present embodiment.
  • the support body 1 in which the recessed part 31 was formed is prepared (FIG. 9A), and the 1st semiconductor chip 10 in which the convex part 32 was formed in the circuit formation surface is mounted in the support body 1 using the mounter 91 (FIG. 9). 9B).
  • the first semiconductor chip 10 is bonded to the support 1 with an adhesive 8.
  • the resin 3A having fluidity is poured by the coater 93 (FIG. 9C).
  • the resin may be poured while rotating the support 1.
  • the chip extension portion 3 is formed by curing the resin while flattening the surface of the resin (FIG. 9D).
  • a via 7 connected to the output terminal of the first semiconductor chip 10 is formed inside the chip extension portion 3, a terminal 11 is formed on the convex portion 32, and a wiring 6 is formed on the surface of the chip extension portion 3.
  • the via 7 and the wiring 6 are integrally formed of a single metal.
  • a passivation film 92 is formed so as to cover the chip extension portion 3 for protection against singulation (FIG. 9E). The steps after the separation are the same as those described with reference to FIGS. 8A to 8D.
  • the first semiconductor chip 10 has the convex portion 32 formed on the main surface, and the first terminal portion 12 is provided on the top surface of the convex portion 32.
  • the portion joined to the second semiconductor chip 20 is higher than the chip surface.
  • the planar shape of the top surface of the convex portion 32 may be, for example, a square.
  • FIG. 11 is a cross-sectional view illustrating a configuration example of a semiconductor device according to the fourth embodiment.
  • symbol is attached
  • a resin layer 41 is formed on the chip extension portion 3 so as to cover the second semiconductor chip 20 instead of the external terminals 2.
  • External terminals 44 such as solder balls are formed on the surface of the resin layer 41.
  • a via 42 connected to the wiring 6 formed on the surface of the chip extension layer 3 is formed inside the resin layer 41.
  • wirings 43 that connect the vias 42 and the external terminals 44 are formed on the surface of the resin layer 41.
  • FIGS. 13A to 13C are process cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment. Note that the steps up to singulation are the same as those described with reference to FIGS. 9A to 9E in the third embodiment.
  • the passivation film 92 is removed.
  • the filler 4A is applied on the circuit forming surface of the first semiconductor chip 10, and the second semiconductor chip 20 is mounted on the first semiconductor chip 10 (FIG. 12A).
  • the filling material 4A is thermocompression bonded to form the filling layer 4, and the second semiconductor chip 20 is fixed (FIG. 12B).
  • a resin layer 41 is formed on the chip extension portion 3, and is cured while being flattened (FIG. 12C).
  • veer 42 connected with the wiring 6 formed in the surface of the chip expansion part 3 is formed in the resin layer 41 (FIG. 12D).
  • the effects described in the third embodiment can be obtained, and the external terminals 44 can be formed in a range corresponding to the back surface of the second semiconductor chip 20. Therefore, the number of external terminals 44 can be easily increased.
  • a through electrode is formed on a support on which the first semiconductor chip 10 is mounted.
  • the support in this case may be, for example, a substrate structure in which a through hole is formed, or may be formed by forming a via in a metal and insulating the periphery of the via.
  • FIG. 14 is a cross-sectional view showing a configuration example of the semiconductor device according to the fifth embodiment.
  • symbol is attached
  • a support body 51 in which a through electrode 53 is formed is used instead of the support body 1.
  • a via 52 for connecting the wiring 6 formed on the surface of the chip extension 3 and the through electrode 53 is formed in the chip extension 3.
  • a PoP (Package on Package) memory 55 is mounted on the surface of the support 51 opposite to the surface on which the first semiconductor chip 10 is mounted, and the electrode 54 of the PoP memory 55 is connected.
  • the through electrode 53 of the support 51 is connected.
  • FIGS. 16A to 16D are process cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • the support body 51 on which the through electrode 53 is formed is prepared (FIG. 15A), and a thin film of the resin 3A to be the chip extension portion 3 is formed (FIG. 15B).
  • the mounter 91 the first semiconductor chip 10 having the convex portions 32 formed on the circuit formation surface is mounted on the support 51 (FIG. 15C).
  • a resin is poured (FIG. 15D), the surface of the resin is flattened, and the resin is cured to form the chip extension portion 3 (FIG. 15E).
  • the via 7 connected to the in-chip terminal of the first semiconductor chip 10 is formed inside the chip extension portion 3, the terminal 11 is formed on the convex portion 32, and the through electrode 53 in the inside of the chip extension portion 3 Vias 52 are formed at corresponding positions.
  • the via 7 and the wiring 6 are integrally formed of a single metal.
  • a passivation film 92 is formed so as to cover the chip extension portion 3 for protection against singulation (FIG. 15F).
  • the passivation film 92 is removed.
  • the filler 4A is applied on the circuit formation surface of the first semiconductor chip 10, and the second semiconductor chip 20 is mounted on the first semiconductor chip 10 (FIG. 16A).
  • the filler 4A is thermocompression bonded to form the filler layer 4, and the second semiconductor chip 20 is fixed (FIG. 16B).
  • a solder resist 5 is formed on the front surface of the chip extension portion 3, the back surface and side surfaces of the second semiconductor chip 20 (FIG. 16C), and external terminals 2 such as solder balls connected to the wiring 6 are formed (FIG. 16). 16D).
  • FIG. 17 is a sectional view showing another configuration example of the semiconductor device according to the fifth embodiment.
  • the same components as those in FIG. 14 are denoted by the same reference numerals, and detailed description thereof may be omitted here.
  • the upper and lower sides of FIG. 14 and the semiconductor device are reversed.
  • external terminals 57 such as solder balls are formed on the surface of the support 51 opposite to the surface on which the first semiconductor chip 10 is mounted. On the other hand, no external terminal is formed on the surface of the chip extension portion 3.
  • another chip 56 is stacked on the second semiconductor chip 20 to form, for example, a stacked memory.
  • FIG. 18 is a cross-sectional view showing another configuration example of the semiconductor device according to the fifth embodiment.
  • the same components as those in FIG. 14 are denoted by the same reference numerals, and detailed description thereof may be omitted here.
  • the upper and lower sides of the semiconductor device in FIG. 18 are denoted by the same reference numerals, and detailed description thereof may be omitted here.
  • external terminals 57 such as solder balls are formed on the surface of the support 51 opposite to the surface on which the first semiconductor chip 10 is mounted.
  • the wiring 6 connected to the via 52 connected to the through electrode 53 of the support 51 and the external terminal 61 connected to the first semiconductor chip 10 are formed.
  • the PoP memory 55 is mounted, and the electrode 54 of the PoP memory 55 is connected to the external terminal 61.
  • the PoP memory 55 may be a functional component such as a CMOS sensor.
  • FIG. 19 is a cross-sectional view showing another configuration example of the semiconductor device according to the fifth embodiment.
  • the same components as those in FIG. 14 are denoted by the same reference numerals, and detailed description thereof may be omitted here.
  • the configuration of FIG. 19 is obtained by applying the structure according to the fourth embodiment to the configuration of FIG. That is, the resin layer 41 is formed on the chip extension portion 3 so as to cover the second semiconductor chip 20 instead of the external terminals 2. External terminals 44 such as solder balls are formed on the surface of the resin layer 41. Inside the resin layer 41, a via 42 connected to the wiring 6 formed on the surface of the chip extension layer 3 is formed. On the surface of the resin layer 41, wirings 43 that connect the vias 42 and the external terminals 44 are formed.
  • another semiconductor chip or the like can be stacked on the side opposite to the second semiconductor chip 20.
  • the features of the semiconductor device according to the present embodiment may be combined with the semiconductor device according to the first or second embodiment.
  • the chip extension unit 3 may be composed of a plurality of layers. By providing wiring layers on the surfaces of the plurality of layers and connecting the external terminals 2 and the first semiconductor chip 10 using the wiring layers, the connectivity can be improved.
  • FIG. 20 is a cross-sectional view showing a configuration example of a semiconductor device according to this modification.
  • the configuration of FIG. 20 is obtained by configuring the chip extension portion 3 with a plurality of layers (here, two layers) 3a and 3b in the configuration of FIG. 1 shown in the first embodiment.
  • Other configurations are substantially the same as those in FIG. 1, and the same reference numerals are given to the same components as those in FIG. 1, and detailed description thereof may be omitted here.
  • a wiring layer is provided on the surface of each of the plurality of layers 3a and 3b.
  • a wiring 6a is formed on the surface of the layer 3a
  • a wiring 6b is formed on the surface of the layer 3b.
  • the via 7a as the second via connects the wiring 6a in the lowermost layer and the first semiconductor chip 10.
  • the via 7b connects the wiring 6a and the wiring 6b.
  • the wiring 6b in the uppermost layer is connected to the external terminal 2. With such a configuration, the connectivity between the external terminal 2 and the first semiconductor chip 10 can be improved.
  • the wirings 6a and 6b and the vias 7a and 7b are integrally formed as a conductor made of a single metal such as Cu, for example.
  • the chip extension unit 3 is configured with two layers, but the chip extension unit 3 may be configured with three or more layers.
  • wiring is formed on the surface of each layer as a plurality of wirings.
  • a first via that connects the wirings and a second via that connects the wiring in the lowermost layer and the first semiconductor chip 10 are provided, and the wiring in the uppermost layer is connected to the external terminal 2.
  • the chip extension portion composed of a plurality of layers is formed by performing the step of forming the chip extension portion 3, the via 7 and the wiring 6 (FIGS. 3E and 3F) a plurality of times. It can be formed by repeating.
  • the chip extension unit 3 may be composed of a plurality of layers as in FIG. Thereby, the connectivity between the external terminal 2 and the first semiconductor chip 10 can be improved.
  • the convex portion 32 is provided on the circuit forming surface of the first semiconductor chip 10 as in the configuration shown in FIG. 6 in the third embodiment, the number of layers and the height of the chip extension portion 3 are determined.
  • the height of the convex portion 32 may be adjusted to keep the distance between the second semiconductor chip 20 and the terminal 11 constant.
  • a semiconductor device including a chip-on-chip structure can be realized with a high density, a small size, and a structure suitable for high-speed operation.
  • an ultrahigh-speed signal transmission LSI can be realized in a small size. Useful for.

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Abstract

半導体装置において、第１半導体チップ（１０）は、主面に複数の端子（１１）が設けられた第１端子部（１２）を有し、裏面が支持体（１）の表面上に実装されている。第２半導体チップ（２０）は、主面に複数の端子（２１）が設けられた第２端子部（２２）を有し、主面が第１半導体チップ（１０）の主面と対向しており、第２端子部（２２）の各端子（２１）が第１端子部（１２）の各端子（１１）とそれぞれ接続されている。第１半導体チップ（１０）と半導体装置の外部端子（２）とは、単一金属からなる導体（６，７）によって接続されている。

Description

半導体装置
　本開示は、半導体チップの積層体が実装された半導体装置に関する。
　半導体パッケージの高密度化および小型化のために、複数の半導体チップを積層化して実装する構造が用いられている。半導体チップの積層化構造として、例えば、複数の半導体チップの回路形成面に設けられている端子同士を接続するチップオンチップ（Chip On Chip：ＣＯＣ）接続構造が知られている。
　特許文献１では、チップオンチップ構造において、下側の半導体チップの周縁部を取り囲むようにチップ拡張部が設けられた構造が示されている。この構造では、チップ拡張部上に、下側の半導体チップの端子と接続された配線が設けられており、この配線とパッケージ基板の外部電極とがボンディングワイヤによって接続されている。
　特許文献２では、チップオンチップ構造において、端子を表出するように樹脂層に埋め込まれた第１半導体チップの上に、第２半導体チップが搭載された構造が示されている。この構造では、樹脂層の表面に、半導体装置の外部端子と接続された配線層が設けられており、第２半導体チップが有するバンプ等の端子がこの配線層に接続されている。
特開２０１３－３０５６８号公報 特開２０１２－１６９４４０号公報
　特許文献１の構成では、半導体チップの端子とパッケージ基板の外部電極とがボンディングワイヤによって接続されている。このため、ワイヤボンディング用の空間や領域が必要になるため、さらなる小型化が困難である。また、ボンディングワイヤはインピーダンスが高く、ＬＣ成分も大きいため、例えば１０Ｇｂｐｓ程度の超高速信号伝送には不向きである。また、電源供給の点でも、半導体チップ内に電源電圧降下が生じやすい。また、製造工程も複雑である。
　特許文献２の構成では、ワイヤボンディングを用いないため、特許文献１の構成における問題は一応解決している。ただし、第２半導体チップから半導体装置の外部端子に至る電気的経路が、第２半導体チップが有するバンプ等の端子と、第１半導体チップが埋め込まれた樹脂層表面に設けられた配線層とを含んでいる。このため、端子と配線層との接合部におけるインピーダンスによって周波数帯域特性が劣化したり、バンプ等の端子の電流許容値が低いため電圧降下が生じやすくなったりする、といった問題がある。
　本開示は、チップオンチップ構造を含む半導体装置について、高密度で小型であって、かつ、高速動作にも適した構造を提供することを目的とする。
　本発明の一態様では、半導体装置は、支持体と、主面に、複数の端子が設けられた第１端子部を有し、裏面が、前記支持体の表面上に実装されている第１半導体チップと、主面に、複数の端子が設けられた第２端子部を有し、前記主面が、前記第１半導体チップの主面と対向しており、前記第２端子部の各端子が、前記第１半導体チップの前記第１端子部の各端子とそれぞれ接続されている第２半導体チップと、外部端子とを備え、前記第１半導体チップは、前記外部端子と、単一金属からなる導体によって接続されている。
　この態様によると、第１半導体チップと半導体装置の外部端子とは、単一金属からなる導体によって接続されている。これにより、第１半導体チップから半導体装置の外部端子に至る電気的経路におけるインピーダンスが低くなり、かつ、ＬＣ成分も低く抑えられる。したがって、この電気的経路における信号の減衰や電源電圧降下が抑制されるので、半導体装置の高速動作が可能になる。
　本開示によると、チップオンチップ構造を含む半導体装置について、高密度で小型であって、かつ、高速動作にも適した構造を実現することができる。
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　以下、実施形態に係る半導体装置について、図面を参照して説明する。ここで説明する半導体装置は、複数の半導体チップの主面（回路形成面）に設けられているマイクロバンプ等の端子同士を接続するチップオンチップ（Chip On Chip：ＣＯＣ）接続構造を含む。
　（第１実施形態）
　図１は第１実施形態に係る半導体装置の構成例を示す断面図である。なお、図１および以降の断面図は、半導体装置の要部断面を模式的に示す図である。
　図１において、支持体１の表面に第１半導体チップ１０が実装されている。支持体１は金属であってもよいし、有機材やガラスエポキシ等の基板であってもかまわない。第１半導体チップ１０は、例えばＳｏＣ（System on Chip）であり、ロジックやメモリなどの集積回路を有している。第１半導体チップ１０は、回路形成面（主面に相当する）を上向き（支持体１と反対側に向かう向き）にして、接着材８によって支持体１に接着されている。なお、図１では、図面下側を半導体装置の上側とし、図面上側を半導体装置の下側としている。以降の構成断面図も、特に断りのない限り、同様である。また、半導体チップ内に記された黒三角は半導体チップのいずれの面が主面であるかを示すものであり、黒三角の頂点で指す方の面が半導体チップの主面である。第１半導体チップ１０は、回路形成面に、マイクロバンプ電極またはＣｕからなるピラー電極などからなる複数の端子１１が設けられている。複数の端子１１が設けられた領域を第１端子部１２とする。
　第２半導体チップ２０は、回路形成面（主面に相当する）が、第１半導体チップ１０の主面と対向するように実装されている。第２半導体チップ２０は、例えばメモリチップであり、ロジックやメモリなどの集積回路を有している。また第２半導体チップ２０は、回路形成面に、例えばＣｕからなるピラー電極などの複数の端子２１が設けられている。複数の端子２１が設けられた領域を第２端子部２２とする。第２半導体チップ２０は、第２端子部２２の各端子２１が、第１半導体チップ１０の第１端子部１２の各端子１１とそれぞれ接続されている。ここでは、第２半導体チップ２０の表面積は第１半導体チップ１０の表面積よりも大きいものとしている。
　チップ拡張部３は、第１半導体チップ１０の周縁部を取り囲むように設けられている。チップ拡張部３は、例えば樹脂によって形成されており、第１半導体チップ１０の周縁部に加えて、第１半導体チップ１０の回路形成面の表面における第１端子部１２以外の領域を覆っている。チップ拡張部３は、第２半導体チップ２０側の表面に配線６が形成されており、また、この配線６と接続されたビア７が形成されている。ビア７は、チップ拡張部３における、第１半導体チップ１０の回路形成面を覆う部分に形成されており、第１半導体チップ１０のチップ内部に設けられた端子１５と接続されている。接続された配線６およびビア７は、ここでは、例えばＣｕ等の単一金属からなる導体として、一体に形成されている。そして、チップ拡張部３の表面には、配線６と接続された例えば半田ボール等の外部端子２が形成されている。また、チップ拡張部３の表面のうち外部端子２が形成されていない領域、並びに、第２半導体チップ２０の裏面および側面を覆うように、ソルダーレジスト５が形成されている。ただし、このソルダーレジスト５はなくてもかまわない。
　また、第１半導体チップ１０と第２半導体チップ２０との間に、樹脂からなる充填層４が形成されている。すなわち、第１半導体チップ１０の各端子１１と第２半導体チップ２０の各端子２１とを接続する部分は、一層の樹脂のみによって覆われている。
　図２は本実施形態に係る半導体装置の構成例を示す平面図であり、図１の構成を図面下から（すなわち半導体装置の上から）見た図である。図２は半導体装置の要部平面を模式的に示している。図２に示すように、第１半導体チップ１０の上に第２半導体チップ２０が実装されており、外部出力端子２は配線６およびビア７を介して第１半導体チップ１０に接続されている。また、第１半導体チップ１０の各端子１１は第２半導体チップ２０の各端子２１とそれぞれ接続されている。
　図３Ａ～図３Ｆおよび図４Ａ～図４Ｄは、本実施形態に係る半導体装置の製造方法の一例を示す工程断面図である。まず、支持体１を準備し（図３Ａ）、硬化させるとチップ拡張部３になる流動性のある樹脂３Ａの薄膜を形成する（図３Ｂ）。その後、マウンタ９１を用いて第１半導体チップ１０を支持体１に実装する（図３Ｃ）。第１半導体チップ１０は接着材８によって支持体１に接着される。その後、樹脂を流し込み（図３Ｄ）、樹脂の表面を平坦化しつつ、樹脂を硬化させることによって、チップ拡張部３を形成する（図３Ｅ）。チップ拡張部３の内部に、第１半導体チップ１０のチップ内端子と接続されたビア７を形成するとともに、チップ拡張部３の表面に配線６を形成する。ビア７と配線６とは、単一金属によって一体に形成される。例えば、Ｃｕメッキによって形成される。また、個片化に対する保護のために、チップ拡張部３を覆うようにパシベーション膜９２が形成される（図３Ｆ）。
　個片化の後、パシベーション膜９２が除去される。そして、第１半導体チップ１０の回路形成面上に充填材４Ａが塗布され、第２半導体チップ２０が第１半導体チップ１０の上に搭載される（図４Ａ）。充填材４Ａが熱圧着されて充填層４が形成され、第２半導体チップ２０が固定される（図４Ｂ）。その後、チップ拡張部３の表面、第２半導体チップ２０の裏面および側面にソルダーレジスト５が形成され（図４Ｃ）、配線６と接続された例えば半田ボール等の外部端子２が形成される（図４Ｄ）。
　本実施形態の構成によると、第１半導体チップ１０と、半導体装置の外部端子２とは、ビア７および配線６によって接続されている。そして、このビア７および配線６は、例えばＣｕメッキによって、単一金属によって一体に形成される。これにより、第１半導体チップ１０から半導体装置の外部端子２に至る電気的経路におけるインピーダンスが低くなり、かつ、ＬＣ成分も低く抑えられる。したがって、この電気的経路における信号の減衰や電源電圧降下が抑制されるので、半導体装置の高速動作が可能になる。
　また、本実施形態の構成では、第１半導体チップ１０と第２半導体チップ２０との接続部分は、１層の樹脂によって覆われている。一方、上述した特許文献２の構成では、樹脂層に埋め込まれた第１半導体チップが第２半導体チップと接続され、その間を別の樹脂で充填しているため、第１半導体チップと第２半導体チップとの接続部分は２層の樹脂によって覆われている。このため、樹脂同士の膨張係数の相違から接合不良が生じやすい、曲げ応力によりクラック等が発生しやすい、という問題があった。これに対して本実施形態では、このような問題が生じず、信頼性がより高くなる。
　また、工程断面図から分かるように、ワイヤボンディング工程が不要であり、また、工程途中で半導体装置の上下を入れ替える必要もない。したがって、簡素な製造工程によって、本実施形態に係る半導体装置を実現することができる。
　（第２実施形態）
　図５は第２の実施形態に係る半導体装置の構成例を示す断面図である。図５は、基本的な構成は第１実施形態における図１とほぼ同様であり、図１と共通の構成要素には同一の符号を付し、その詳細な説明を省略する場合がある。
　図５の構成では、支持体１は、主面、すなわち第１半導体チップ１０が実装される側の面に凹部３１を有している。そして、第１半導体チップ１０は、その凹部３１内に置かれている。このため、図１の構成と比べると、チップ拡張部３は厚みが薄くなっており、半導体装置の高さが低くなっている。逆にいうと、同等の高さの半導体装置を実現する際に、第１実施形態よりも、第１半導体チップ１０の厚さを厚く保つことができる。
　本実施形態の構成によると、第１半導体チップ１０は、支持体１の凹部３１に嵌まるように、実装されている。これにより、チップ拡張部３を形成するための樹脂の量が少なくて済む。また、第１半導体チップ１０の厚さを薄くする必要がないため、ウェハスライスの研磨プロセスや製造設備を省くことができ、製造コストを削減できる。また、第１半導体チップ１０の厚さを厚く保つことにより、第１半導体チップ１０の熱伝導率を高く保てるため、半導体装置上面からの熱伝導率を大きくできる。
　（第３実施形態）
　図６は第３の実施形態に係る半導体装置の構成例を示す断面図である。図６は、基本的な構成は第１実施形態における図１とほぼ同様であり、図１と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。
　図６の構成では、第１半導体チップ１０は、回路形成面に、例えば樹脂やポリミド等の絶縁性物質等からなる凸部３２が設けられている。そして、第１半導体チップ１０の第１端子部１２における各端子１１は、凸部３２の天面上に設けられている。また、第２実施形態と同様に、支持体１は、第１半導体チップ１０が実装される側の面に凹部３１を有しており、第１半導体チップ１０は、その凹部３１に嵌まるように、実装されている。なお、支持体１に凹部３１が形成されていない図１の構成において、第１半導体チップ１０の回路形成面に凸部３２を設けた構成としてもよい。
　さらに、支持体１は、裏面、すなわち、第１半導体チップ１０が実装された面と反対の面から、凹部３１の内面まで貫通する孔３３が形成されている。孔３３は、製造工程において、チップ拡張部３を形成する樹脂を吸引するために用いられる。なお、孔３３は省いてもかまわない。また、図５の構成において、孔３３を形成してもよい。
　図７Ａ～図７Ｆおよび図８Ａ～図８Ｄは、本実施形態に係る半導体装置の製造方法の一例を示す工程断面図である。まず、凹部３１および孔３３が形成された支持体１を準備し（図７Ａ）、硬化させるとチップ拡張部３になる流動性のある樹脂３Ａの薄膜を形成する（図７Ｂ）。その後、マウンタ９１を用いて、回路形成面に凸部３２が形成された第１半導体チップ１０を支持体１に実装する（図７Ｃ）。第１半導体チップ１０は接着材８によって支持体１に接着される。このとき、孔３３から余分な流動性のある樹脂３Ａを吸引しながら、第１半導体チップ１０を接着し（図７Ｄ）、樹脂の表面を平坦化しつつ、樹脂を硬化させることによって、チップ拡張部３を形成する（図７Ｅ）。このとき、凸部３２の天面には樹脂が流れ込まない制御を行う。チップ拡張部３の内部に、第１半導体チップ１０のチップ内端子と接続されたビア７を形成し、凸部３２に端子１１を形成するとともに、チップ拡張部３の表面に配線６を形成する。ビア７と配線６とは単一金属によって一体に形成される。また、個片化に対する保護のために、チップ拡張部３を覆うようにパシベーション膜９２が形成される（図７Ｆ）。
　個片化の後、パシベーション膜９２が除去される。そして、第１半導体チップ１０の回路形成面上に充填材４Ａが塗布され、第２半導体チップ２０が第１半導体チップ１０の上に搭載される（図８Ａ）。充填材４Ａが熱圧着されて充填層４が形成され、第２半導体チップ２０が固定される（図８Ｂ）。その後、チップ拡張部３の表面、第２半導体チップ２０の裏面および側面にソルダーレジスト５が形成され（図８Ｃ）、配線６と接続された例えば半田ボール等の外部端子２が形成される（図８Ｄ）。
　図９Ａ～図９Ｅは、本実施形態に係る半導体装置の製造方法の他の例を示す工程断面図である。まず、凹部３１が形成された支持体１を準備し（図９Ａ）、マウンタ９１を用いて、回路形成面に凸部３２が形成された第１半導体チップ１０を支持体１に実装する（図９Ｂ）。第１半導体チップ１０は接着材８によって支持体１に接着される。その後、コーター９３によって流動性のある樹脂３Ａを流し込む（図９Ｃ）。このとき、支持体１を回転させながら樹脂を流し込んでもよい。そして、樹脂の表面を平坦化しつつ、樹脂を硬化させることによって、チップ拡張部３を形成する（図９Ｄ）。チップ拡張部３の内部に、第１半導体チップ１０の出力端子と接続されたビア７を形成し、凸部３２に端子１１を形成するとともに、チップ拡張部３の表面に配線６を形成する。ビア７と配線６とは単一金属によって一体に形成される。また、個片化に対する保護のために、チップ拡張部３を覆うようにパシベーション膜９２が形成される（図９Ｅ）。個片化以降の工程は、図８Ａ～図８Ｄを用いて説明した工程と同様である。
　本実施形態に係る構成によると、第１半導体チップ１０は、主面に凸部３２が形成されており、第１端子部１２は、凸部３２の天面上に設けられている。このため、第２半導体チップ２０と接合される部分が、チップ表面より高くなっている。これにより、第２半導体チップ２０の第２端子部２２における各端子２１の高さを低くすることができるので、第１または第２実施形態よりも狭いピッチで端子２１を生成することができる。また、端子２１を形成する材料コストを削減できる。また、充填層４の熱硬化と端子１１，２１の接合との時間差による接合不良を抑制することができる。
　なお、図１０に示すように、凸部３２の天面の平面形状は、例えば正方形であってもよい。これにより、第１半導体チップ１０を樹脂３Ａに埋め込む工程において、樹脂３ＡがＣｏＣ接合部に流れ込むことを防ぐことができる。また、第１半導体チップ１０を搬送する際のマウンタへの吸着がより安定する。
　（第４実施形態）
　図１１は第４の実施形態に係る半導体装置の構成例を示す断面図である。図１１では、第３実施形態における図６と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。
　図１１の構成では、チップ拡張部３の上に、外部端子２の代わりに、樹脂層４１が、第２半導体チップ２０を覆うように形成されている。そして樹脂層４１の表面に、例えば半田ボール等の外部端子４４が形成されている。樹脂層４１の内部には、チップ拡張層３の表面に形成された配線６と接続されたビア４２が形成されている。樹脂層４１の表面には、ビア４２と外部端子４４とを接続する配線４３が形成されている。
　図１２Ａ～図１２Ｄおよび図１３Ａ～図１３Ｃは、本実施形態に係る半導体装置の製造方法の一例を示す工程断面図である。なお、個片化までの工程は、第３実施形態で図９Ａ～図９Ｅを用いて説明した工程と同様である。
　個片化の後、パシベーション膜９２が除去される。そして、第１半導体チップ１０の回路形成面上に充填材４Ａが塗布され、第２半導体チップ２０が第１半導体チップ１０の上に搭載される（図１２Ａ）。充填材４Ａが熱圧着されて充填層４が形成され、第２半導体チップ２０が固定される（図１２Ｂ）。その後、チップ拡張部３の上に、樹脂層４１が形成されて、平坦化しつつ硬化される（図１２Ｃ）。そして、樹脂層４１の内部に、チップ拡張部３の表面に形成された配線６と接続されるビア４２が形成される（図１２Ｄ）。
　ビア４２が形成された樹脂層４１の表面に、例えばＣｕからなる配線４３が形成される（図１３Ａ）。その後、樹脂層４１の表面にソルダーレジスト４５が形成され（図１３Ｂ）、配線４３と接続された例えば半田ボール等の外部端子４４が形成される（図１３Ｃ）。
　本実施形態に係る半導体装置の構造によると、第３の実施形態で説明した作用効果が得られるとともに、外部端子４４は、第２半導体チップ２０の裏面に対応する範囲にも形成することができるので、外部端子４４の個数を容易に増やすことができる。
　なお、本実施形態に係る半導体装置の特徴は、第１または第２実施形態に係る半導体装置と組み合わせてもよい。
　（第５実施形態）
　第５実施形態では、第１半導体チップ１０が実装される支持体に、貫通電極が形成されているものとする。この場合の支持体は、例えば、スルーホールが形成されたサブストレート構造であってもよいし、あるいは、金属にビアを形成し、ビアの周囲を絶縁したものであってもよい。
　図１４は第５実施形態に係る半導体装置の構成例を示す断面図である。図１４では、第３実施形態における図６と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。
　図１４の構成では、支持体１の代わりに、貫通電極５３が形成された支持体５１が用いられている。チップ拡張部３に、チップ拡張部３表面に形成された配線６と貫通電極５３とを接続するビア５２が形成されている。そして図１４の構成では、支持体５１の、第１半導体チップ１０が実装された面と反対側の面に、ＰｏＰ（Package on Package）メモリ５５が実装されており、ＰｏＰメモリ５５の電極５４が支持体５１の貫通電極５３と接続されている。
　図１５Ａ～図１５Ｆおよび図１６Ａ～図１６Ｄは、本実施形態に係る半導体装置の製造方法の一例を示す工程断面図である。まず、貫通電極５３が形成された支持体５１を準備し（図１５Ａ）、チップ拡張部３になる樹脂３Ａの薄膜を形成する（図１５Ｂ）。その後、マウンタ９１を用いて、回路形成面に凸部３２が形成された第１半導体チップ１０を支持体５１に実装する（図１５Ｃ）。その後、樹脂を流し込み（図１５Ｄ）、樹脂の表面を平坦化し、樹脂を硬化させることによって、チップ拡張部３を形成する（図１５Ｅ）。チップ拡張部３の内部に、第１半導体チップ１０のチップ内端子と接続されたビア７を形成し、凸部３２に端子１１を形成するとともに、チップ拡張部３の内部における、貫通電極５３と対応する位置にビア５２を形成する。ビア７と配線６とは単一金属によって一体に形成される。また、個片化に対する保護のために、チップ拡張部３を覆うようにパシベーション膜９２が形成される（図１５Ｆ）。
　個片化の後、パシベーション膜９２が除去される。そして、第１半導体チップ１０の回路形成面上に充填材４Ａが塗布され、第２半導体チップ２０が第１半導体チップ１０の上に搭載される（図１６Ａ）。充填材４Ａが熱圧着されて充填層４が形成され、第２半導体チップ２０が固定される（図１６Ｂ）。その後、チップ拡張部３の表面、第２半導体チップ２０の裏面および側面にソルダーレジスト５が形成され（図１６Ｃ）、配線６と接続された例えば半田ボール等の外部端子２が形成される（図１６Ｄ）。
　図１７は第５実施形態に係る半導体装置の他の構成例を示す断面図である。図１７では、図１４と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。なお、図１７では、図１４と半導体装置の上下が反対に図示されている。
　図１７の構成では、支持体５１の、第１半導体チップ１０が実装された面と反対側の面に、例えば半田ボール等の外部端子５７が形成されている。一方、チップ拡張部３の表面には外部端子が形成されていない。また、第２半導体チップ２０には他のチップ５６が積層されており、例えば積層メモリを構成している。
　図１８は第５実施形態に係る半導体装置の他の構成例を示す断面図である。図１８では、図１４と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。なお、図１８では、図１４と半導体装置の上下が反対に図示されている。
　図１８の構成では、支持体５１の、第１半導体チップ１０が実装された面と反対側の面に、例えば半田ボール等の外部端子５７が形成されている。一方、チップ拡張部３の表面には、支持体５１の貫通電極５３とつなぐビア５２とつながる配線６と第１半導体チップ１０と接続された外部端子６１が形成されている。そして図１８の構成では、ＰｏＰメモリ５５が実装されており、ＰｏＰメモリ５５の電極５４が外部端子６１と接続されている。なお、ＰｏＰメモリ５５はＣＭＯＳセンサー等の機能部品であってもよい。
　図１９は第５実施形態に係る半導体装置の他の構成例を示す断面図である。図１９では、図１４と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。
　図１９の構成は、図１４の構成に、第４実施形態に係る構造を適用したものである。すなわち、チップ拡張部３の上に、外部端子２の代わりに、樹脂層４１が、第２半導体チップ２０を覆うように形成されている。そして樹脂層４１の表面に、例えば半田ボール等の外部端子４４が形成されている。樹脂層４１の内部には、チップ拡張層３の表面に形成された配線６と接続されたビア４２が形成されている。樹脂層４１の表面には、ビア４２と外部端子４４とを接続する配線４３が形成されている。
　本実施形態の構成によると、第２半導体チップ２０と反対側にも他の半導体チップ等の積層が可能になる。なお、本実施形態に係る半導体装置の特徴は、第１または第２実施形態に係る半導体装置と組み合わせてもよい。
　（変形例）
　また、上述の各実施形態において、チップ拡張部３は、複数の層からなるものとしてもよい。この複数の層の表面に配線層をそれぞれ設けて、この配線層を利用して外部端子２と第１半導体チップ１０とを接続することによって、その接続性を向上させることができる。
　図２０は本変形例に係る半導体装置の構成例を示す断面図である。図２０の構成は、第１実施形態で示した図１の構成において、チップ拡張部３を複数の層（ここでは２層）３ａ，３ｂによって構成したものである。その他の構成は図１とほぼ同様であり、図１と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。複数の層３ａ，３ｂの表面には配線層がそれぞれ設けられており、複数の配線として、層３ａの表面に配線６ａが形成され、層３ｂの表面に配線６ｂが形成されている。第２ビアとしてのビア７ａは、最下層にある配線６ａと第１半導体チップ１０とを接続している。ビア７ｂは配線６ａと配線６ｂとを接続している。最上層にある配線６ｂが外部端子２と接続されている。このような構成により、外部端子２と第１半導体チップ１０との接続性を向上させることができる。配線６ａ，６ｂおよびビア７ａ，７ｂは、ここでは、例えばＣｕ等の単一金属からなる導体として、一体に形成されている。
　なお、図２０では、チップ拡張部３は２層で構成されているものとしたが、チップ拡張部３は３層以上で構成されてもよい。この場合は、複数の配線として、各層の表面にそれぞれ配線が形成される。そして、配線同士を接続する第１ビアと、最下層にある配線と第１半導体チップ１０とを接続する第２ビアとが設けられ、最上層にある配線が外部端子２と接続される。
　また、複数の層からなるチップ拡張部は、例えば、第１実施形態で示した製造方法において、チップ拡張部３、ビア７および配線６を形成する工程（図３Ｅおよび図３Ｆ）を、複数回繰り返すことによって、形成することができる。
　また、ここでは、第１実施形態に係る構成についての変形例を示したが、その他の実施形態についても、図２０と同様に、チップ拡張部３は複数の層からなるものとしてもよい。これにより、外部端子２と第１半導体チップ１０との接続性を向上させることができる。なお、第３実施形態において図６に示した構成のように、第１半導体チップ１０の回路形成面に凸部３２を設ける構成の場合には、チップ拡張部３の層数や高さに応じて凸部３２の高さを調整し、第２半導体チップ２０と端子１１との間隔を一定に保つようにしてもよい。
　本開示では、チップオンチップ構造を含む半導体装置について、高密度で小型であって、かつ、高速動作にも適した構造を実現できるので、例えば、超高速信号伝送用ＬＳＩを小さなサイズで実現するのに有用である。
１　支持体
２　外部端子
３　チップ拡張部
３ａ，３ｂ　層
６　配線
６ａ，６ｂ　配線
７　ビア
７ａ，７ｂ　ビア
１０　第１半導体チップ
１１　端子
１２　第１端子部
２０　第２半導体チップ
２１　端子
２２　第２端子部
３１　凹部
３２　凸部
３３　孔
４１　樹脂層
４２　ビア
４４　外部端子
５１　基板
５３　貫通電極

Claims (11)

  1. 　支持体と、
    　主面に、複数の端子が設けられた第１端子部を有し、裏面が、前記支持体の表面上に実装されている第１半導体チップと、
    　主面に、複数の端子が設けられた第２端子部を有し、前記主面が、前記第１半導体チップの主面と対向しており、前記第２端子部の各端子が、前記第１半導体チップの前記第１端子部の各端子とそれぞれ接続されている第２半導体チップと、
    　外部端子とを備え、
    　前記第１半導体チップは、前記外部端子と、単一金属からなる導体によって接続されている
    ことを特徴とする半導体装置。
  2. 　請求項１記載の半導体装置において、
    　前記第１半導体チップの周縁部を取り囲むように設けられたチップ拡張部を備え、
    　前記外部端子は、前記チップ拡張部上に設けられており、
    　前記導体は、
    　前記チップ拡張部の表面に形成されており、前記外部端子と接続された配線と、
    　前記チップ拡張部の内部に形成されており、前記第１半導体チップと前記配線とを接続するビアとを備えている
    ことを特徴とする半導体装置。
  3. 　請求項１記載の半導体装置において、
    　前記第１半導体チップと前記第２半導体チップとの間の、前記第１端子部と前記第２端子部とが接続された部分は、一層の樹脂によって覆われている
    ことを特徴とする半導体装置。
  4. 　請求項１記載の半導体装置において、
    　前記支持体は、前記第１半導体チップが実装された面に、凹部を有しており、
    　前記第１半導体チップは、前記凹部内に置かれている
    ことを特徴とする半導体装置。
  5. 　請求項４記載の半導体装置において、
    　前記支持体は、前記第１半導体チップが実装された面と反対側の面から、前記凹部の内面まで貫通する孔が形成されている
    ことを特徴とする半導体装置。
  6. 　請求項１記載の半導体装置において、
    　前記第１半導体チップは、前記主面に、凸部が形成されており、
    　前記第１端子部は、前記凸部の天面上に設けられている
    ことを特徴とする半導体装置。
  7. 　請求項６記載の半導体装置において、
    　前記凸部の天面の平面形状は、正方形である
    ことを特徴とする半導体装置。
  8. 　請求項１記載の半導体装置において、
    　前記第２半導体チップの周縁部を取り囲むように、かつ、前記第２半導体チップの裏面を覆うように設けられた樹脂層を備え、
    　前記外部端子は、前記樹脂層の、前記第２半導体チップの裏面上に相当する表面上に形成されており、
    　前記導体は、前記樹脂層内に形成されたビアを含む
    ことを特徴とする半導体装置。
  9. 　請求項１記載の半導体装置において、
    　前記支持体は、貫通電極が形成された基板である
    ことを特徴とする半導体装置。
  10. 　請求項９記載の半導体装置において、
    　前記外部端子は、前記基板の裏面に形成されており、
    　前記導体は、前記貫通電極を含む
    ことを特徴とする半導体装置。
  11. 　請求項１記載の半導体装置において、
    　前記第１半導体チップの周縁部を取り囲むように設けられており、複数の層からなるチップ拡張部を備え、
    　前記外部端子は、前記チップ拡張部上に設けられており、
    　前記導体は、
    　前記チップ拡張部を構成する前記複数の層の表面にそれぞれ形成された、複数の配線と、
    　前記チップ拡張部の内部に形成されており、前記複数の配線同士を接続する第１ビアと、
    　前記チップ拡張部の内部に形成されており、前記複数の配線のうち最下層にある配線と前記第１半導体チップとを接続する第２ビアとを備えており、
    　前記複数の配線のうち最上層にある配線が、前記外部端子と接続されている
    ことを特徴とする半導体装置。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7442616B2 (ja) 2019-07-18 2024-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション ３ｄ半導体メモリ構造体を形成する方法、構造体

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10381330B2 (en) * 2017-03-28 2019-08-13 Silicon Storage Technology, Inc. Sacrificial alignment ring and self-soldering vias for wafer bonding

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326211A (ja) * 1993-05-17 1994-11-25 Hitachi Ltd 半導体パッケージと回路基板およびそれを用いた電子機器
JP2001257310A (ja) * 2000-03-09 2001-09-21 Oki Electric Ind Co Ltd 半導体装置およびその製造方法およびその試験方法
JP2008251912A (ja) * 2007-03-30 2008-10-16 Nec Corp 半導体装置及びその製造方法
WO2010047227A1 (ja) * 2008-10-21 2010-04-29 日本電気株式会社 半導体装置及びその製造方法
WO2011021364A1 (ja) * 2009-08-20 2011-02-24 パナソニック株式会社 半導体装置およびその製造方法
WO2013057867A1 (ja) * 2011-10-21 2013-04-25 パナソニック株式会社 半導体装置
WO2013105153A1 (ja) * 2012-01-12 2013-07-18 パナソニック株式会社 半導体装置
JP2014090148A (ja) * 2012-10-31 2014-05-15 Kyocer Slc Technologies Corp 配線基板およびその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5856174A (en) * 1995-06-29 1999-01-05 Affymetrix, Inc. Integrated nucleic acid diagnostic device
JP4580730B2 (ja) * 2003-11-28 2010-11-17 ルネサスエレクトロニクス株式会社 オフセット接合型マルチチップ半導体装置
US20100047227A1 (en) * 2006-02-17 2010-02-25 Kenji Yamamoto Novel anticancer cathepsin formulations and anticancer agent for use in combined anticancer therapy
GB0722068D0 (en) * 2007-11-09 2007-12-19 Mars Inc Predictive test
US20140090148A1 (en) * 2010-09-08 2014-04-03 Foodhandler, Inc. Method for producing thin film gloves using the cutting and sealing process and glove produced therefrom
JP2012169440A (ja) 2011-02-14 2012-09-06 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
JP2013030568A (ja) 2011-07-27 2013-02-07 Panasonic Corp 半導体装置
US9502270B2 (en) * 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326211A (ja) * 1993-05-17 1994-11-25 Hitachi Ltd 半導体パッケージと回路基板およびそれを用いた電子機器
JP2001257310A (ja) * 2000-03-09 2001-09-21 Oki Electric Ind Co Ltd 半導体装置およびその製造方法およびその試験方法
JP2008251912A (ja) * 2007-03-30 2008-10-16 Nec Corp 半導体装置及びその製造方法
WO2010047227A1 (ja) * 2008-10-21 2010-04-29 日本電気株式会社 半導体装置及びその製造方法
WO2011021364A1 (ja) * 2009-08-20 2011-02-24 パナソニック株式会社 半導体装置およびその製造方法
WO2013057867A1 (ja) * 2011-10-21 2013-04-25 パナソニック株式会社 半導体装置
WO2013105153A1 (ja) * 2012-01-12 2013-07-18 パナソニック株式会社 半導体装置
JP2014090148A (ja) * 2012-10-31 2014-05-15 Kyocer Slc Technologies Corp 配線基板およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7442616B2 (ja) 2019-07-18 2024-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション ３ｄ半導体メモリ構造体を形成する方法、構造体

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