JP2005294464A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2005294464A JP2005294464A JP2004106224A JP2004106224A JP2005294464A JP 2005294464 A JP2005294464 A JP 2005294464A JP 2004106224 A JP2004106224 A JP 2004106224A JP 2004106224 A JP2004106224 A JP 2004106224A JP 2005294464 A JP2005294464 A JP 2005294464A
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- Japan
- Prior art keywords
- field effect
- effect transistor
- semiconductor chip
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 488
- 230000005669 field effect Effects 0.000 claims description 277
- 229920005989 resin Polymers 0.000 claims description 99
- 239000011347 resin Substances 0.000 claims description 99
- 229910052751 metal Inorganic materials 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 24
- 230000000694 effects Effects 0.000 claims description 7
- 230000005684 electric field Effects 0.000 claims description 3
- 238000007789 sealing Methods 0.000 description 84
- 230000003071 parasitic effect Effects 0.000 description 45
- 238000000034 method Methods 0.000 description 32
- 230000001965 increasing effect Effects 0.000 description 29
- 238000006243 chemical reaction Methods 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 20
- 239000010931 gold Substances 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 230000001681 protective effect Effects 0.000 description 13
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 11
- 238000007747 plating Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 230000017525 heat dissipation Effects 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- 238000001721 transfer moulding Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 230000020169 heat generation Effects 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 235000010290 biphenyl Nutrition 0.000 description 1
- 239000004305 biphenyl Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000013036 cure process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 235000019800 disodium phosphate Nutrition 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47F—SPECIAL FURNITURE, FITTINGS, OR ACCESSORIES FOR SHOPS, STOREHOUSES, BARS, RESTAURANTS OR THE LIKE; PAYING COUNTERS
- A47F5/00—Show stands, hangers, or shelves characterised by their constructional features
- A47F5/10—Adjustable or foldable or dismountable display stands
- A47F5/101—Display racks with slotted uprights
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47B—TABLES; DESKS; OFFICE FURNITURE; CABINETS; DRAWERS; GENERAL DETAILS OF FURNITURE
- A47B47/00—Cabinets, racks or shelf units, characterised by features related to dismountability or building-up from elements
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47B—TABLES; DESKS; OFFICE FURNITURE; CABINETS; DRAWERS; GENERAL DETAILS OF FURNITURE
- A47B96/00—Details of cabinets, racks or shelf units not covered by a single one of groups A47B43/00 - A47B95/00; General details of furniture
- A47B96/02—Shelves
- A47B96/027—Cantilever shelves
- A47B96/028—Cantilever shelves characterised by support bracket location means, e.g. fixing means between support bracket and shelf
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47B—TABLES; DESKS; OFFICE FURNITURE; CABINETS; DRAWERS; GENERAL DETAILS OF FURNITURE
- A47B96/00—Details of cabinets, racks or shelf units not covered by a single one of groups A47B43/00 - A47B95/00; General details of furniture
- A47B96/06—Brackets or similar supporting means for cabinets, racks or shelves
- A47B96/061—Cantilever brackets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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Abstract
【解決手段】 ハイサイドスイッチ用のパワーMOS・FETとローサイドスイッチ用のパワーMOS・FETとが直列に接続された回路を有する非絶縁型DC−DCコンバータにおいて、ハイサイドスイッチ用のパワートランジスタとローサイドスイッチ用のパワートランジスタと、これらを駆動するドライバ回路とを夫々異なる半導体チップ5a、5b、5cで構成し、前記3つの半導体チップ5a、5b、5cを一つのパッケージ6aに収納し、かつ、前記ハイサイドスイッチ用のパワートランジスタを含む半導体チップ5aと前記ドライバ回路を含む半導体チップ5cとを近接して配置する。
【選択図】 図8
Description
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する樹脂体とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力用電源電位を外部に出力する出力端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記第3半導体チップは、前記第3半導体チップと前記第1半導体チップの距離が前記第3半導体チップと前記第2半導体チップの距離より近くなるように配置するものである。
本実施の形態1の半導体装置は、例えばデスクトップ型のパーソナルコンピュータ、ノート型のパーソナルコンピュータ、サーバまたはゲーム機等の電源回路に用いられる非絶縁型DC−DCコンバータである。図1は、その非絶縁型DC−DCコンバータ1の一例の回路図を示している。非絶縁型DC−DCコンバータ1は、制御回路2、ドライバ回路3a、3b、電界効果トランジスタ(パワーMOS・FET)Q1、Q2、コイルL1、コンデンサC1等のような素子を有している。これら素子は、配線基板に実装され、配線基板の配線を通じて電気的に接続されている。なお、図1の符号4は、上記デスクトップ型のパーソナルコンピュータ、ノート型のパーソナルコンピュータ、サーバまたはゲーム機等のCPU(Central Processing Unit)またはDSP(Digital Signal Processor)等のような負荷回路を示している。符号のET1、ET2及びET3は端子を示している。このような非絶縁型DC−DCコンバータ1は、図54に示すように、一つのCPUに対して複数個並列接続するように配置されている。
図28は本発明の他の実施の形態である半導体装置のパッケージ構成の一例の平面図である。図28に記載の半導体装置は、図8に記載の半導体装置とほぼ同様の構成であるが、半導体チップ5aにおけるゲート電極用のパッドBP3の形状、半導体チップ5bにおける、ゲート電極用のパッドBP7、およびソース電極用パッド5bの形状と、半導体チップ5a、5bにおける、表面保護膜14、22によって覆われる部分、ソースセル領域の形状などが主に異なるものである。なお、図28でも図面を見易くするため、半導体チップ5a、5b、5c、ダイパッド7a1、7a2、7a3及びリード7b上の封止樹脂体8を取り除いて示すとともに、ダイパッド7a1、7a2、7a3及びリード7bにハッチングを付した。
図29は本発明の他の実施の形態である半導体装置のパッケージ構成の一例の平面図である。図29に記載の半導体装置は、図8に記載の半導体装置とほぼ同様の構成であるが、半導体チップ5aにおけるゲート電極パターンが主に異なるものである。なお、図29でも図面を見易くするため、半導体チップ5a、5b、5c、ダイパッド7a1、7a2、7a3及びリード7b上の封止樹脂体8を取り除いて示すとともに、ダイパッド7a1、7a2、7a3及びリード7bにハッチングを付した。
図30は本発明の他の実施の形態である半導体装置のパッケージ構成の一例の平面図である。図30に記載の半導体装置は、図8に記載の半導体装置とほぼ同様の構成であるが、半導体チップ5bにおけるゲート電極パターンが主に異なるものである。なお、図30でも図面を見易くするため、半導体チップ5a、5b、5c、ダイパッド7a1、7a2、7a3及びリード7b上の封止樹脂体8を取り除いて示すとともに、ダイパッド7a1、7a2、7a3及びリード7bにハッチングを付した。
図31は本発明の他の実施の形態である半導体装置のパッケージ構成の一例の平面図である。図31に記載の半導体装置は、図8に記載の半導体装置とほぼ同様の構成であるが、半導体チップ5aのソースと接続するワイヤWRの配置や本数が主に異なる。なお、図31でも図面を見易くするため、半導体チップ5a、5b、5c、ダイパッド7a1、7a2、7a3及びリード7b上の封止樹脂体8を取り除いて示すとともに、ダイパッド7a1、7a2、7a3及びリード7bにハッチングを付した。
図32は本発明の他の実施の形態である半導体装置のパッケージ構成の一例の平面図、図33は図32のD−D線の断面図、図34は本実施の形態6における半導体装置の製造方法を示す組み立てフロー図である。図32に記載の半導体装置は、図8に記載の半導体装置とほぼ同様の構成であるが、リードフレーム40の表面に、部分的に銀ペーストによる表面処理が施されている点が主に異なる。なお、図32でも図面を見易くするため、半導体チップ5a、5b、5c、ダイパッド7a1、7a2、7a3及びリード7b上の封止樹脂体8を取り除いて示すとともに、ダイパッド7a1、7a2、7a3及びリード7bにハッチングを付した。
非DC−DCコンバータの大電流化および高周波化に起因する他の問題として樹脂封止体8の形成後における、半導体装置の信頼性の問題がある。特に、前記実施の形態1〜5での説明では、例えばNi/Pd/Auフラッシュめっきのような鉛フリーめっきを施した複数のダイパッド7a1、7a2、7a3を1つのパッケージ6aに収容する構成なので、高い密着力が必要となる。本実施の形態6では、その密着力を考慮し、リード抜けの防止対策を考慮した構成について説明する。
本実施の形態8では、前記リード抜け防止対策の構成の変形例について説明する。
本実施の形態9では、前記リード抜け防止対策の構成の変形例について説明する。
図41は本発明の他の実施の形態である非絶縁型DC−DCコンバータ1の一部の回路を含むパッケージ6aの構成例の平面図、図42は図41のE−E線の断面図である。なお、図41でも図面を見易くするため、一部の樹脂封止体8を取り除いて示すとともに、ダイパッド7a1、7a2、7a3及びリード7bにハッチングを付した。
図43は本発明の他の実施の形態10である半導体装置の製造方法を示す組み立てフロー図である。
図44は本発明の他の実施の形態11である半導体装置の製造方法を示す組み立てフロー図である。
非絶縁型DC−DCコンバータ1の大電流化および高周波化に起因する問題として動作時の熱の問題がある。特に、前記実施の形態1〜10での説明では、3つの半導体チップ5a、5b、5cを1つのパッケージ6aに収容する構成なので、高い放熱性が必要となる。本実施の形態12では、その放熱性を考慮した構成について説明する。
本実施の形態14では、前記放熱構成の変形例について説明する。
本実施の形態15では、前記放熱構成の変形例について説明する。
2 制御回路
3a ドライバ回路、第1制御回路
3b ドライバ回路、第2制御回路
4 負荷回路
5a、5b、5c 半導体チップ
5ax、5bx 主面
5ay、5by 裏面
6a パッケージ
7a1、7a2、7a3 ダイパッド(チップ搭載部)
7b、7b1、7b2、7b3、7b4 リード
8 樹脂封止体
10 リードフレーム
11、11a ハーフエッチ領域
12 絶縁層
13 配線層
13a、13b 層配線層
14、22 表面保護膜
14a、22a ボンディング開口
15、26 半導体基板
16ep エピタキシャル層
17n1、17n2 n型半導体領域
17p p型半導体領域
18 溝
19、23p、23n ゲート絶縁膜
20 キャップ絶縁膜
21 絶縁酸化膜
21a 開口部
22 表面保護膜
24a p-型の半導体領域
24b p+型の半導体領域
25a n-型の半導体領域
25b n+型の半導体領域
27 配線基板
27a、27b、27c、27d 配線
28、29 パッケージ
30、31 チップ部品
40、42、44、47 リードフレーム
41 ペースト材
43 切り欠き部
45 スリット
46 溝
48、48a、48b、48c 金属板配線
49 バンプ電極
50 非絶縁型DC−DCコンバータ
60、62 金属体
61 接着剤
BP、BP1、BP2、BP3 ボンディングパッド
BP4、BP5、BP6、BP7、BP8 ボンディングパッド
D1、D2 寄生ダイオード
DR1、DR2、DR3、DR4 ドレイン領域
FLD フィールド酸化膜
G1 ゲート領域
G2、G3、G4 ゲート領域
I11、I12、I21、I22 電流
LgH、LsH、LgL、LsL 寄生インダクタンス
LdH、LsH、LdL、LsL 寄生インピーダンス
NWL n型のウエル領域
PWL p-型のウエル領域
Q1、Q2、Q3、Q4、Q5、Q6 電界効果トランジスタ
SR1、SR2、SR3、SR4 ソース領域
WR、WR1、WR2、WR3 ボンディングワイヤ
Claims (29)
- それぞれが所定の間隔を持って配置された第1チップ搭載部、第2チップ搭載部及び第3チップ搭載部と、
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する樹脂体とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力用電源電位を外部に出力する出力端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記第3半導体チップは、前記第3半導体チップと前記第1半導体チップの距離が前記第3半導体チップと前記第2半導体チップの距離より近くなるように配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、更に前記第1、第2及び第3半導体チップの各々は、四角形状の主面と、前記四角形状の主面の辺に沿って配置された複数の電極を有し、前記第3半導体チップの前記複数の電極中で、前記第1及び第2電界効果トランジスタの夫々のソース及びゲートに電気的に接続される電極は、前記第1及び第2半導体チップの夫々と最も隣接する前記主面の角部を規定する2辺に沿って配置されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第3半導体チップの制御回路は前記第1電界効果トランジスタのゲートを制御する第1制御回路と、前記第2電界効果トランジスタのゲートを制御する第2制御回路を有することを特徴とする半導体装置。
- 請求項3記載の半導体装置において、更に前記第1電界効果トランジスタのゲートと前記第1制御回路とを電気的に接続する第1ワイヤと、前記第2電界効果トランジスタのゲートと前記第2制御回路とを電気的に接続する第2ワイヤを有し、前記第1ワイヤの長さは前記第2ワイヤの長さよりも短いことを特徴とする半導体装置。
- 請求項3記載の半導体装置において、更に前記第3半導体チップは、四角形状の主面と、その主面に形成された複数の電極と、前記第2制御回路の出力段を構成する第3電界効果トランジスタとを有し、
前記第3電界効果トランジスタは、前記第3半導体チップの4辺の内で、前記第2半導体チップに最も近接する1辺側に配置され、
前記複数の電極中で、前記第3電界効果トランジスタのソースに接続されるソース用電極は、他の電極よりもチップの内側に配置されていることを特徴とする半導体装置。 - それぞれが所定の間隔を持って配置された第1チップ搭載部、第2チップ搭載部及び第3チップ搭載部と、
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する樹脂体とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力電源電位を外部に出力する出力端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記第2半導体チップは、前記出力端子よりも前記第2電源端子に近い位置に配置されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、更に前記第2半導体チップは、長方形状の主面と、その主面上に形成され、各々が最上層の金属配線により形成され、かつ、前記第2電界効果トランジスタのゲート及びソースに接続されたゲート電極及びソース電極を有し、
前記ゲート電極は、前記第2半導体チップの一対の長辺の一方から他方に向かって延びる複数のゲート電極パターンを有し、
前記ソース電極は、前記複数のゲート電極パターン間に配置され、かつ、前記第2半導体チップの一対の長辺の他方から一方に向かって延びる複数のソース電極パターンを有することを特徴とする半導体装置。 - 請求項7記載の半導体装置において、前記複数のゲート電極パターンの一端部は、前記長辺の他方に到達していないことを特徴とする半導体装置。
- 請求項6記載の半導体装置において、更に前記第3半導体チップはその主面に形成された複数のワイヤボンディング用端子を有し、前記第2電界効果トランジスタのゲートに接続されるワイヤボンディング用端子の外形サイズは前記第3半導体チップの複数のワイヤボンディング用端子の外形サイズと同じ大きさで形成されていることを特徴とする半導体装置。
- 請求項6記載の半導体装置において、前記第2半導体チップは、四角形状を有し、
前記第2電界効果トランジスタのゲートに接続されるワイヤボンディング用端子は、前記第2半導体チップの4つの角部のうち、前記第3半導体チップに最も近い角部に配置されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、更に前記第3半導体チップは前記第2電界効果トランジスタのゲートを制御する制御回路と、
前記第2電界効果トランジスタのソース及びゲートと前記制御回路とを夫々電気的に接続する第1及び第2ワイヤとを有し、
前記第1及び第2ワイヤは並べて形成することを特徴とする半導体装置。 - 請求項6記載の半導体装置において、更に前記第3半導体チップは前記第2電界効果トランジスタのゲートを制御する制御回路と、
前記第2電界効果トランジスタのソースと前記第2電源端子とを電気的に接続する複数の第1ワイヤと、前記第2電界効果トランジスタのゲートと前記制御回路とを電気的に接続する第2ワイヤを有し、
前記複数の第1ワイヤの太さは前記第2ワイヤよりも太いことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、更に前記第2電界効果トランジスタのソースと前記第2電源端子とを電気的に接続する金属体を有することを特徴とする半導体装置。
- それぞれが所定の間隔を持って配置された第1チップ搭載部、第2チップ搭載部及び第3チップ搭載部と、
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する樹脂体とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力用電源電位を外部に出力する出力用端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記第1の半導体チップは、前記第2チップ搭載部の一辺と隣り合う前記第1チップ搭載部の一辺に寄せて配置されていることを特徴とする半導体装置。 - 請求項14記載の半導体装置において、更に前記第1半導体チップは、長方形状の主面と、その主面上に形成され、各々が最上層の金属配線により形成され、かつ、前記第1電界効果トランジスタのゲート及びソースに接続されたゲート電極及びソース電極を有し、
前記ソース電極は、前記第2チップ搭載部の一辺と隣り合う前記第1チップ搭載部の一辺の近くに配置することを特徴とする半導体装置。 - 請求項14記載の半導体装置において、更に前記第1半導体チップの厚さ方向と交差する平面形状は長方形状に形成され、長手方向に形成される一辺は、前記第2チップ搭載部の一辺と隣り合う前記第1チップ搭載部の一辺の近くに配置され、
前記第1電界効果トランジスタのソースと前記第2チップ搭載部とを電気的に接続する複数のワイヤを有し、
前記複数のワイヤは並べて形成していることを特徴とする半導体装置。 - 請求項14記載の半導体装置において、更に前記第1半導体チップは、長方形状の主面と、その主面上に形成され、各々が最上層の金属配線により形成され、かつ、前記第2電界効果トランジスタのゲート及びソースに接続されたゲート電極及びソース電極を有し、
前記ゲート電極は、前記第1半導体チップの一対の短辺の一方から他方に向かって延びる複数のゲート電極パターンを有し、
前記ソース電極は、前記複数のゲート電極パターン間に配置され、かつ、前記第1半導体チップの一対の短辺の他方から一方に向かって延びる複数のソース電極パターンを有することを特徴とする半導体装置。 - 請求項17記載の半導体装置において、更に前記ゲート電極パターンは前記ソース電極の間に形成される第1部分と、前記第1半導体チップの主面の周辺に配置される第2部分とを有し、
前記第1部分の幅は前記第2部分の幅よりも太く形成することを特徴とする半導体装置。 - 請求項17記載の半導体装置において、前記第1電界効果トランジスタのソースと前記第2チップ搭載部とを電気的に接続する複数のワイヤを有し、
前記複数のワイヤは前記第1部分を挟んで千鳥配置することを特徴とする半導体装置。 - 請求項14記載の半導体装置において、更に前記第3半導体チップは複数の端子を有し、前記第1電界効果トランジスタのゲートの外形サイズは前記第3半導体チップの複数の端子の外形サイズと同じ大きさで形成されていることを特徴とする半導体装置。
- 請求項14記載の半導体装置において、更に前記第1半導体チップは、長方形状の主面と、その主面上に形成され、各々が最上層の金属配線により形成され、かつ、前記第2電界効果トランジスタのゲート及びソースに接続されたゲート電極及びソース電極を有し、
前記ゲート電極は前記第3チップ搭載部の一辺と隣り合う辺の真ん中に近い位置に配置することを特徴とする半導体装置。 - 請求項14記載の半導体装置において、更に前記第1電界効果トランジスタのソースと前記第2チップ搭載部とを電気的に接続する金属体を有することを特徴とする半導体装置。
- それぞれが所定の間隔を持って配置された第1チップ搭載部、第2チップ搭載部及び第3チップ搭載部と、
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する樹脂体とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力用電源電位を外部に出力する出力用端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記第1半導体チップは前記第1電界効果トランジスタのソースと前記第2チップ搭載部とを電気的に接続する複数の第1ワイヤと、前記第1電界効果トランジスタのソースと前記制御回路とを電気的に接続する複数の第2ワイヤとを有することを特徴とする半導体装置。 - 請求項23記載の半導体装置において、前記複数の第1ワイヤの太さは前記複数の第2ワイヤの太さよりも太く形成されていることを特徴とする半導体装置。
- 請求項23記載の半導体装置において、更に前記第1電界効果トランジスタのゲートと前記制御回路とを電気的に接続する複数の第3ワイヤとを有し、
前記複数の第2ワイヤと前記複数の第3ワイヤは隣り合うように並べて接続されていることを特徴とする半導体装置。 - それぞれが所定の間隔を持って配置された第1チップ搭載部、第2チップ搭載部及び第3チップ搭載部と、
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する樹脂体とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力用電源電位を外部に出力する出力用端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記第1及び第2電界効果トランジスタは、第1主面と前記第1主面に対向する第2主面とを有する半導体基板と、前記半導体基板の第1主面から第2主面に向かって形成された溝と、前記溝の内壁面に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と、前記第1主面に形成され、かつ、前記ゲート電極と隣接して形成されたソース用の半導体領域と、前記第2主面に形成されたドレイン用の半導体領域により形成されていることを特徴とする半導体装置。 - 請求項26記載の半導体装置において、前記第1及び第2電界効果トランジスタのゲート電極の側面に形成され、かつ、前記半導体基板の厚さ方向に形成され、かつ、前記ソース及びドレイン用の半導体領域間にチャネル形成用の半導体領域が形成されていることを特徴とする半導体装置。
- 請求項26記載の半導体装置において、前記第1半導体チップの外形サイズは前記第3半導体チップの外形サイズよりも大きく形成され、前記第2半導体チップの外形サイズは前記第1半導体チップの外形サイズよりも大きく形成されていることを特徴とする半導体装置。
- 請求項26記載の半導体装置において、前記第1電界効果トランジスタの閾値電圧は前記第2電界効果トランジスタよりも低い閾値電圧で制御されていることを特徴とする半導体装置。
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Also Published As
Publication number | Publication date |
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US20130203217A1 (en) | 2013-08-08 |
US20140312510A1 (en) | 2014-10-23 |
US20140003002A1 (en) | 2014-01-02 |
US20070145580A1 (en) | 2007-06-28 |
US8013430B2 (en) | 2011-09-06 |
KR20110121599A (ko) | 2011-11-07 |
US8159054B2 (en) | 2012-04-17 |
CN101582415B (zh) | 2011-04-13 |
US20120139130A1 (en) | 2012-06-07 |
US20100141229A1 (en) | 2010-06-10 |
KR101116195B1 (ko) | 2012-03-07 |
US20090218683A1 (en) | 2009-09-03 |
CN1677666A (zh) | 2005-10-05 |
JP4489485B2 (ja) | 2010-06-23 |
US20050218489A1 (en) | 2005-10-06 |
US7554181B2 (en) | 2009-06-30 |
KR20060041974A (ko) | 2006-05-12 |
US7928589B2 (en) | 2011-04-19 |
CN100524735C (zh) | 2009-08-05 |
KR101116202B1 (ko) | 2012-03-07 |
US20110273154A1 (en) | 2011-11-10 |
US7554209B2 (en) | 2009-06-30 |
US9412701B2 (en) | 2016-08-09 |
TWI364098B (en) | 2012-05-11 |
CN101582415A (zh) | 2009-11-18 |
US8575733B2 (en) | 2013-11-05 |
US8350372B2 (en) | 2013-01-08 |
TW200536241A (en) | 2005-11-01 |
US8796827B2 (en) | 2014-08-05 |
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