US11088074B2 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

Info

Publication number
US11088074B2
US11088074B2 US16/472,559 US201716472559A US11088074B2 US 11088074 B2 US11088074 B2 US 11088074B2 US 201716472559 A US201716472559 A US 201716472559A US 11088074 B2 US11088074 B2 US 11088074B2
Authority
US
United States
Prior art keywords
resin film
electrodes
plural
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/472,559
Other versions
US20200020632A1 (en
Inventor
Kazuhiro Maeda
Takayuki Hisaka
Hitoshi Kurusu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MAEDA, KAZUHIRO, KURUSU, HITOSHI, HISAKA, TAKAYUKI
Publication of US20200020632A1 publication Critical patent/US20200020632A1/en
Application granted granted Critical
Publication of US11088074B2 publication Critical patent/US11088074B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4821—Bridge structure with air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to a semiconductor device wherein a hollow structure sealed with a resin film is formed, and a method for manufacturing same.
  • High electron mobility transistors formed of compound semiconductors are applied to microwave and millimeter wave amplifiers because they have excellent high frequency characteristics and low noise characteristics.
  • HEMT High electron mobility transistors
  • Increase in mutual conductance and reduction in the capacitance between a gate electrode and a source electrode are effective means for enhancing f r and f max .
  • the present invention has been made to solve the problems as described above, and has an object to provide a semiconductor device capable of preventing chemicals from entering the hollow structure and enhancing the high frequency characteristics by reducing the capacitance, and a method for manufacturing same.
  • a semiconductor device includes: a semiconductor substrate; a multi-finger transistor including plural control electrodes, plural first electrodes, and plural second electrodes provided on the semiconductor substrate; a resin film covering the transistor, and a first wiring provided on the resin film and electrically connecting the plural first electrodes to one other, wherein the resin film covers contact portions between the first wiring and the plural first electrodes, and a first hollow structure sealed with the resin film is provided around the plural control electrodes and the plural second electrodes.
  • the first hollow structure sealed with the resin film is formed around the plural control electrodes and the plural second electrodes.
  • the capacitance of the transistor can be reduced as much as possible as compared with a case where the hollow structure is formed only around the control electrodes. As a result, the capacitance can be reduced to enhance the high frequency characteristics.
  • the resin film covers the contact portion between the first wiring and the first electrode. Therefore, resists or chemicals such as an inorganic aqueous solution which are used in steps after formation of the first hollow structure can be prevented from entering the first hollow structure.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along I-IT of FIG. 1 .
  • FIG. 3 is a cross-sectional view taken along III-IV of FIG. 1 .
  • FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
  • FIG. 10 is a cross-sectional view taken along I-II of FIG. 9 .
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 14 is a cross-sectional view taken along I-II of FIG. 13 .
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along I-II of FIG. 1 .
  • FIG. 3 is a cross-sectional view taken along III-IV of FIG. 1 .
  • a multi-finger field effect transistor including plural gate electrodes 2 , plural source electrodes 3 , and plural drain electrodes 4 is formed on a semiconductor substrate 1 .
  • the cross-sectional shape of the gate electrode 2 is T-type or Y-type.
  • the plural gate electrodes 2 are connected to a gate pad 6 via a gate wiring 5 .
  • the plural source electrodes 3 are connected to a source pad 9 via a source wiring 7 and a connection wiring 8 .
  • the plural drain electrodes 4 are connected to a drain pad 11 via a drain wiring 10 .
  • Insulating films 12 and 13 and resin films 14 and 15 cover the transistor.
  • the connection wiring 8 is formed on the resin film 15 .
  • the connection wiring 8 and the source wiring 7 electrically connect the plural source electrodes 3 to one other.
  • the resin film 14 covers contact portions between the connection wiring 8 and the plural source electrodes 3 .
  • Hollow structures 16 sealed with the resin films 14 and 15 are formed around the plural gate electrodes 2 and the plural drain electrodes 4 .
  • a hollow structure 17 sealed with the resin films 14 and 15 is formed at an intersection portion of the gate wiring 5 and the connection wiring 8 .
  • the thicknesses of the resin films 14 and 15 are equal to 2 to 20 ⁇ m.
  • the heights of the hollow structures 16 and 17 are equal to 1 to 10 ⁇ m.
  • the widths and depths of the hollow structures 16 and 17 are equal to several ⁇ m to several hundreds ⁇ m.
  • the hollow structures 16 and 17 are formed not over the whole chip, but for each of elements of a circuit such as a transistor and a wiring.
  • a transistor having the gate electrodes 2 , the source electrodes 3 , and the drain electrodes 4 is formed on the semiconductor substrate 1 .
  • lower layer wirings such as the gate wiring 5 are simultaneously formed.
  • the insulating film 12 is formed on the entire surface.
  • the insulating film 12 is opened at a place to which an electrical wiring is connected in a subsequent step.
  • the resin film 14 which is a photosensitive resin film is formed on the entire surface by a coating method using a spin coater, or a laminating method, or an STP (Spin-coating film Transfer and hot-Pressing technology) method.
  • the resin film 14 is subjected to patterning by exposure and development so that the source electrodes 3 are covered while the gate electrodes 2 and the drain electrodes 4 are not covered, but surrounded.
  • the resin film 14 can be easily patterned.
  • the resin film 14 is also opened in a region on the gate wiring 5 which will become the intersection portion of the wirings later. Thereafter, curing processing is performed to cure the resin film 14 .
  • a sheet film of a photosensitive resin film as the resin film 15 is bonded to the upper surface of the resin film 14 by the laminating method or the STP method.
  • the hollow structure 16 sealed with the resin films 14 and 15 is formed around the gate electrodes 2 and the drain electrode 4 .
  • the hollow structure 17 can be formed in a region above the gate wiring 5 on the same plane.
  • the resin film 15 is exposed and developed to form through holes 18 above the source electrodes 3 and the like. Thereafter, the curing processing is performed to cure the resin film 15 .
  • the resin film 15 may be non-photosensitive resin, and in this case, dry etching is used when the through holes 18 are formed.
  • connection wiring 8 connected to the source electrodes 3 through the through holes 18 is formed on the resin film 15 by plating or vapor deposition.
  • a power supply layer is formed, patterning is performed with a resist, and then electrolytic plating is performed. Thereafter, the resist and the power supply layer are removed.
  • the vapor deposition method patterning is performed with a resist, a metal film is formed by vapor deposition, and the resist is removed by a lift-off method.
  • the outside of the resin film 14 and the outside of the resin film 15 are covered with the insulating film 13 . However, portions required for contacts are opened. As a result, the semiconductor device according to the present embodiment is manufactured.
  • the hollow structures 16 sealed with the resin films 14 and 15 are formed around the gate electrodes 2 and the drain electrodes 4 .
  • the capacitance of the transistor can be reduced as much as possible as compared with a case where the hollow structures are formed only around the gate electrodes 2 . As a result, the capacitance can be reduced to enhance the high frequency characteristics.
  • the resin film 14 covers the contact portion between the connection wiring 8 and the source electrode 3 .
  • the resin film 15 is pasted as shown in FIG. 6 , the hollow structures 16 are completely sealed. Therefore, resists or chemicals such as an inorganic aqueous solution which are used in steps after formation of the hollow structures 16 can be prevented from entering the hollow structures 16 .
  • the hollow structure 17 sealed with the resin films 14 and 15 is formed at the intersection portion of the gate wiring 5 and the connection wiring 8 .
  • the wiring capacitance can be reduced, so that characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated.
  • the hollow structure 17 may be formed at an intersection portion of the gate wiring 5 and the drain wiring 10 .
  • FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
  • FIG. 10 is a cross-sectional view taken along I-II of FIG. 9 .
  • the connection wiring 8 is formed above the plural gate electrodes 2 and the plural drain electrodes 4 and on the resin film 15 , and electrically connects the plural source electrodes 3 to another.
  • the connection wiring 8 extends in a direction perpendicular to the longitudinal direction of the drain electrodes 4 .
  • the other configuration is the same as that of the first embodiment, and even in this case, the same effect as the first embodiment can be obtained.
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention.
  • a lower layer wiring 19 and an upper layer wiring 20 are formed in a region other than a field effect transistor.
  • the lower layer wiring 19 is covered with the resin films 14 and 15
  • the upper layer wiring 20 is formed on the resin film 15 .
  • the hollow structure 17 sealed with the resin films 14 and 15 is formed at an intersection portion of the lower layer wiring 19 and the upper layer wiring 20 .
  • FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
  • Support poles 21 for supporting the resin film 15 above the hollow structures 16 and 17 are formed inside the hollow structures 16 and 17 .
  • the capacitance of the device is increased as compared with the third embodiment, the structure can be stably formed, so that production stability is enhanced.
  • the other configuration and effect are the same as the third embodiment.
  • FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 14 is a cross-sectional view taken along I-II of FIG. 13 .
  • a multi-finger bipolar transistor including plural base electrodes 22 , plural emitter electrodes 23 , and plural collector electrodes 24 is formed on a semiconductor substrate 1 .
  • the plural base electrodes 22 are connected to a base pad 26 via a base wiring 25 .
  • the plural emitter electrodes 23 are connected to an emitter pad 28 via a connection wiring 27 .
  • the plural collector electrodes 24 are connected to a collector pad 30 via a collector wiring 29 .
  • connection wiring 27 for electrically connecting the plural emitter electrodes 23 to each other is formed on the resin film 15 .
  • the resin film 14 covers contact portions between the connection wiring 27 and the plural emitter electrodes 23 .
  • the hollow structures 16 sealed with the resin films 14 and 15 are formed around the plural base electrodes 22 and the plural collector electrodes 24 . Even in the case of such a bipolar transistor, the same effect as the first and second embodiments can be obtained.
  • the second hollow structure may be formed at the intersection portion of the wirings.

Abstract

A multi-finger transistor including plural control electrodes (2), plural first electrodes (3), and plural second electrodes (4) is provided on a semiconductor substrate (1). A resin film (14,15) covers the transistor. A first wiring (8) electrically connecting the plural first electrodes (3) to one other is provided on the resin film (14,15). The resin film (14,15) covers contact portions between the first wiring (8) and the plural first electrodes (3). A first hollow structure (16) sealed with the resin film (14,15) is provided around the plural control electrodes (2) and the plural second electrodes (4).

Description

FIELD
The present invention relates to a semiconductor device wherein a hollow structure sealed with a resin film is formed, and a method for manufacturing same.
BACKGROUND
High electron mobility transistors (HEMTs) formed of compound semiconductors are applied to microwave and millimeter wave amplifiers because they have excellent high frequency characteristics and low noise characteristics. In order to enhance the high frequency characteristics of HEMT, it is necessary to enhance the cutoff frequency (fr) and the maximum operating frequency (fmax). Increase in mutual conductance and reduction in the capacitance between a gate electrode and a source electrode are effective means for enhancing fr and fmax.
On the other hand, with respect to HEMTs to which a wafer level package technique is applied, it has been reported that the capacitance increases and the high frequency characteristics deteriorate because a resin film is filled under a ridge portion of a Y-type gate, (for example, see Non-Patent Literature 1). In order to solve this problem, removal of a resin film around a gate electrode is known as means for preventing deterioration of the high frequency characteristics (for example, see Patent Literatures 1 to 3). Moreover, since an increase in capacitance is suppressed as much as possible in addition to formation of a hollow structure around the gate electrode, a transistor in which the hollow structure is extended to the peripheries of source and drain electrodes, and a method for manufacturing the same have been proposed (for example, see Patent Literatures 4 and 5).
CITATION LIST Patent Literature
  • [PTL 1] JP H05-335343 A
  • [PTL 2] JP 2015-046445 A
  • [PTL 3] JP 2016-039319 A
  • [PTL 4] JP 2014-209522 A
  • [PTL 5] JP 2009-176930 A
Non Patent Literature
  • [NPL n] T. Hisakal, H. Sasakil, T. Katohl, K. Kanayal, N. Yoshidal, A. A. Villanueva, and J. A. del Alamo, IEICE Electronics Express, Vol. 7, No. 8, P. 558-562
SUMMARY Technical Problem
However, in a structure in which the resin film is not formed over the entire transistor, there is a problem that resists and chemicals such as an inorganic aqueous solution used in subsequent steps enter the hollow structure from the gap between the resin film and the electrode. Furthermore, in a semiconductor device to which the wafer level package technique is applied, wiring portions other than the transistor are covered with the resin film, so that the capacitance of the entire device increases. As a result, there has been a problem that high frequency characteristics such as gain or noise characteristics deteriorate.
The present invention has been made to solve the problems as described above, and has an object to provide a semiconductor device capable of preventing chemicals from entering the hollow structure and enhancing the high frequency characteristics by reducing the capacitance, and a method for manufacturing same.
Solution to Problem
A semiconductor device according to the present invention includes: a semiconductor substrate; a multi-finger transistor including plural control electrodes, plural first electrodes, and plural second electrodes provided on the semiconductor substrate; a resin film covering the transistor, and a first wiring provided on the resin film and electrically connecting the plural first electrodes to one other, wherein the resin film covers contact portions between the first wiring and the plural first electrodes, and a first hollow structure sealed with the resin film is provided around the plural control electrodes and the plural second electrodes.
Advantageous Effects of Invention
In the present invention, the first hollow structure sealed with the resin film is formed around the plural control electrodes and the plural second electrodes. By expanding the hollow structure of the transistor as described above, the capacitance of the transistor can be reduced as much as possible as compared with a case where the hollow structure is formed only around the control electrodes. As a result, the capacitance can be reduced to enhance the high frequency characteristics. The resin film covers the contact portion between the first wiring and the first electrode. Therefore, resists or chemicals such as an inorganic aqueous solution which are used in steps after formation of the first hollow structure can be prevented from entering the first hollow structure.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along I-IT of FIG. 1.
FIG. 3 is a cross-sectional view taken along III-IV of FIG. 1.
FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 10 is a cross-sectional view taken along I-II of FIG. 9.
FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 14 is a cross-sectional view taken along I-II of FIG. 13.
 DESCRIPTION OF EMBODIMENTS
A semiconductor device and a method for manufacturing same according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.
First Embodiment
FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along I-II of FIG. 1. FIG. 3 is a cross-sectional view taken along III-IV of FIG. 1. A multi-finger field effect transistor including plural gate electrodes 2, plural source electrodes 3, and plural drain electrodes 4 is formed on a semiconductor substrate 1. The cross-sectional shape of the gate electrode 2 is T-type or Y-type. The plural gate electrodes 2 are connected to a gate pad 6 via a gate wiring 5. The plural source electrodes 3 are connected to a source pad 9 via a source wiring 7 and a connection wiring 8. The plural drain electrodes 4 are connected to a drain pad 11 via a drain wiring 10.
Insulating films 12 and 13 and resin films 14 and 15 cover the transistor. The connection wiring 8 is formed on the resin film 15. The connection wiring 8 and the source wiring 7 electrically connect the plural source electrodes 3 to one other. The resin film 14 covers contact portions between the connection wiring 8 and the plural source electrodes 3. Hollow structures 16 sealed with the resin films 14 and 15 are formed around the plural gate electrodes 2 and the plural drain electrodes 4. Furthermore, a hollow structure 17 sealed with the resin films 14 and 15 is formed at an intersection portion of the gate wiring 5 and the connection wiring 8.
The thicknesses of the resin films 14 and 15 are equal to 2 to 20 μm. The heights of the hollow structures 16 and 17 are equal to 1 to 10 μm. The widths and depths of the hollow structures 16 and 17 are equal to several μm to several hundreds μm. The hollow structures 16 and 17 are formed not over the whole chip, but for each of elements of a circuit such as a transistor and a wiring.
Subsequently, a method of manufacturing a semiconductor device according to the present embodiment will be described. FIGS. 4 to 8 are cross-sectional views showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 4, 6 and 8 correspond to the cross-sectional view of FIG. 2, and FIGS. 5 and 7 correspond to the cross-sectional view of FIG. 3.
First, as shown in FIGS. 4 and 5, a transistor having the gate electrodes 2, the source electrodes 3, and the drain electrodes 4 is formed on the semiconductor substrate 1. At this time, lower layer wirings such as the gate wiring 5 are simultaneously formed. The insulating film 12 is formed on the entire surface. The insulating film 12 is opened at a place to which an electrical wiring is connected in a subsequent step. Next, the resin film 14 which is a photosensitive resin film is formed on the entire surface by a coating method using a spin coater, or a laminating method, or an STP (Spin-coating film Transfer and hot-Pressing technology) method. The resin film 14 is subjected to patterning by exposure and development so that the source electrodes 3 are covered while the gate electrodes 2 and the drain electrodes 4 are not covered, but surrounded. By using the photosensitive resin film as described above, the resin film 14 can be easily patterned. Furthermore, the resin film 14 is also opened in a region on the gate wiring 5 which will become the intersection portion of the wirings later. Thereafter, curing processing is performed to cure the resin film 14.
Next, as shown in FIGS. 6 and 7, a sheet film of a photosensitive resin film as the resin film 15 is bonded to the upper surface of the resin film 14 by the laminating method or the STP method. As a result, the hollow structure 16 sealed with the resin films 14 and 15 is formed around the gate electrodes 2 and the drain electrode 4. At the same time, the hollow structure 17 can be formed in a region above the gate wiring 5 on the same plane.
Next, as shown in FIG. 8, the resin film 15 is exposed and developed to form through holes 18 above the source electrodes 3 and the like. Thereafter, the curing processing is performed to cure the resin film 15. The resin film 15 may be non-photosensitive resin, and in this case, dry etching is used when the through holes 18 are formed.
Next, the connection wiring 8 connected to the source electrodes 3 through the through holes 18 is formed on the resin film 15 by plating or vapor deposition. In the case of the plating, a power supply layer is formed, patterning is performed with a resist, and then electrolytic plating is performed. Thereafter, the resist and the power supply layer are removed. On the other hand, in the case of the vapor deposition method, patterning is performed with a resist, a metal film is formed by vapor deposition, and the resist is removed by a lift-off method. Finally, the outside of the resin film 14 and the outside of the resin film 15 are covered with the insulating film 13. However, portions required for contacts are opened. As a result, the semiconductor device according to the present embodiment is manufactured.
In the present embodiment, the hollow structures 16 sealed with the resin films 14 and 15 are formed around the gate electrodes 2 and the drain electrodes 4. By expanding the hollow structures of the transistor as described above, the capacitance of the transistor can be reduced as much as possible as compared with a case where the hollow structures are formed only around the gate electrodes 2. As a result, the capacitance can be reduced to enhance the high frequency characteristics.
The resin film 14 covers the contact portion between the connection wiring 8 and the source electrode 3. As a result, when the resin film 15 is pasted as shown in FIG. 6, the hollow structures 16 are completely sealed. Therefore, resists or chemicals such as an inorganic aqueous solution which are used in steps after formation of the hollow structures 16 can be prevented from entering the hollow structures 16.
Furthermore, the hollow structure 17 sealed with the resin films 14 and 15 is formed at the intersection portion of the gate wiring 5 and the connection wiring 8. By forming the hollow structure between the wirings as described above, the wiring capacitance can be reduced, so that characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated. Note that the hollow structure 17 may be formed at an intersection portion of the gate wiring 5 and the drain wiring 10.
Second Embodiment
FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a cross-sectional view taken along I-II of FIG. 9. The connection wiring 8 is formed above the plural gate electrodes 2 and the plural drain electrodes 4 and on the resin film 15, and electrically connects the plural source electrodes 3 to another. The connection wiring 8 extends in a direction perpendicular to the longitudinal direction of the drain electrodes 4. The other configuration is the same as that of the first embodiment, and even in this case, the same effect as the first embodiment can be obtained.
Third Embodiment
FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. A lower layer wiring 19 and an upper layer wiring 20 are formed in a region other than a field effect transistor. The lower layer wiring 19 is covered with the resin films 14 and 15, and the upper layer wiring 20 is formed on the resin film 15. The hollow structure 17 sealed with the resin films 14 and 15 is formed at an intersection portion of the lower layer wiring 19 and the upper layer wiring 20. By forming the hollow structure between the wirings as described above, the wiring capacitance can be reduced, so that characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated. The other configuration and effect are the same as the second embodiment.
Fourth Embodiment
FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. Support poles 21 for supporting the resin film 15 above the hollow structures 16 and 17 are formed inside the hollow structures 16 and 17. As a result, it is possible to prevent the resin film 15 from hanging down and prevent defects in the process. Although the capacitance of the device is increased as compared with the third embodiment, the structure can be stably formed, so that production stability is enhanced. The other configuration and effect are the same as the third embodiment.
Fifth Embodiment
FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention. FIG. 14 is a cross-sectional view taken along I-II of FIG. 13. A multi-finger bipolar transistor including plural base electrodes 22, plural emitter electrodes 23, and plural collector electrodes 24 is formed on a semiconductor substrate 1. The plural base electrodes 22 are connected to a base pad 26 via a base wiring 25. The plural emitter electrodes 23 are connected to an emitter pad 28 via a connection wiring 27. The plural collector electrodes 24 are connected to a collector pad 30 via a collector wiring 29.
The connection wiring 27 for electrically connecting the plural emitter electrodes 23 to each other is formed on the resin film 15. The resin film 14 covers contact portions between the connection wiring 27 and the plural emitter electrodes 23. The hollow structures 16 sealed with the resin films 14 and 15 are formed around the plural base electrodes 22 and the plural collector electrodes 24. Even in the case of such a bipolar transistor, the same effect as the first and second embodiments can be obtained.
Furthermore, as in the third embodiment, the second hollow structure may be formed at the intersection portion of the wirings. As a result, since the wiring capacitance is reduced, the characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated.
REFERENCE SIGNS LIST
  • 1 semiconductor substrate; 2 gate electrode (control electrode); 3 source electrode (first electrode); 4 drain electrode (second electrode); 5 gate wiring (second wiring); 8,27 connection wiring (first wiring); 14,15 resin film; 16,17 hollow structure; 19 lower layer wiring; 20 upper layer wiring; 21 support pole; 22 base electrode (control electrode); 23 emitter electrode (first electrode); 24 collector electrode (second electrode)

Claims (5)

The invention claimed is:
1. A semiconductor device comprising:
a semiconductor substrate;
a multi-finger transistor including plural control electrodes, plural first electrodes, and plural second electrodes provided on the semiconductor substrate;
a first resin film formed on the semiconductor substrate;
a second resin film covering the multi-finger transistor and contacting the first resin film; and
a first wiring provided on the second resin film and electrically connecting the plural first electrodes to one other, wherein
the first resin film covers part of contact portions between the first wiring and the plural first electrodes which is formed on a region of the multi-finger transistor, and
a first hollow structure sealed with the second resin film is provided around the plural control electrodes and one of the plural second electrodes, wherein
the second resin film defines an upper surface of the first hollow structure.
2. The semiconductor device according to claim 1, further comprising
a second wiring provided on the semiconductor substrate, covered with the second resin film, and electrically connecting the plural control electrodes to one other, wherein
a second hollow structure sealed with the second resin film is provided at an intersection portion of the first wiring and the second wiring.
3. The semiconductor device according to claim 1, wherein
the first wiring is provided above the plural control electrodes and the plural second electrodes.
4. The semiconductor device according to claim 3, further comprising
a lower layer wiring covered with the second resin film, and an upper layer wiring provided on the second resin film, wherein
a second hollow structure sealed with the second resin film is provided at an intersection portion of the lower layer wiring and the upper layer wiring.
5. The semiconductor device according to claim 4, further comprising
a support pole supporting the second resin film and provided inside the second hollow structure.
US16/472,559 2017-04-04 2017-04-04 Semiconductor device and method for manufacturing same Active US11088074B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/014100 WO2018185839A1 (en) 2017-04-04 2017-04-04 Semiconductor device and method for manufacturing same

Publications (2)

Publication Number Publication Date
US20200020632A1 US20200020632A1 (en) 2020-01-16
US11088074B2 true US11088074B2 (en) 2021-08-10

Family

ID=60205942

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/472,559 Active US11088074B2 (en) 2017-04-04 2017-04-04 Semiconductor device and method for manufacturing same

Country Status (7)

Country Link
US (1) US11088074B2 (en)
JP (1) JP6222419B1 (en)
KR (1) KR102177894B1 (en)
CN (1) CN110476231A (en)
DE (1) DE112017007395T5 (en)
TW (1) TWI659506B (en)
WO (1) WO2018185839A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710715A (en) * 2020-05-14 2020-09-25 西安电子科技大学 Gallium nitride microwave millimeter wave transistor structure with air cavity and preparation method
US11302609B2 (en) 2020-08-31 2022-04-12 Nxp Usa, Inc. Radio frequency power dies having flip-chip architectures and power amplifier modules containing the same
TWI751008B (en) * 2021-01-27 2021-12-21 鴻鎵科技股份有限公司 Package structure of double transistor
FR3121544B1 (en) * 2021-03-31 2023-11-24 St Microelectronics Crolles 2 Sas Thermal and electrical insulation structure
US20230299172A1 (en) * 2022-03-17 2023-09-21 Analog Devices, Inc. Sealed cavity embedded in a semiconductor wafer

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335343A (en) 1992-05-27 1993-12-17 Sony Corp Field effect transistor
US5408742A (en) * 1991-10-28 1995-04-25 Martin Marietta Corporation Process for making air bridges for integrated circuits
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US5966520A (en) * 1995-11-03 1999-10-12 Motorola, Inc. Method of designing unit FET cells with unconditional stability
US6424006B1 (en) * 1995-06-20 2002-07-23 Infineon Technologies Ag Semiconductor component
US20020140007A1 (en) * 2001-03-30 2002-10-03 Fujitsu Quantum Devices Limited Semiconductor device and method for fabricating the same
US20040058485A1 (en) 2002-08-29 2004-03-25 Fujitsu Limited Semiconductor device with mushroom gate
US6724067B2 (en) * 2001-04-13 2004-04-20 Anadigics, Inc. Low stress thermal and electrical interconnects for heterojunction bipolar transistors
US20090189200A1 (en) 2008-01-24 2009-07-30 Kabushiki Kaisha Toshiba Semiconductor device and fabrication method of the semiconductor device
US20120133440A1 (en) * 2010-11-26 2012-05-31 Kabushiki Kaisha Toshiba Power amplifying device and coupled power amplifying device
US20120267795A1 (en) * 2011-04-21 2012-10-25 Sumitomo Electric Device Innovations, Inc. Semiconductor device
US20130056875A1 (en) 2011-09-01 2013-03-07 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
US20140103434A1 (en) * 2012-10-11 2014-04-17 International Business Machines Corporation Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages
US20140306231A1 (en) 2013-04-16 2014-10-16 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20150060946A1 (en) 2013-08-27 2015-03-05 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
US20160042994A1 (en) 2014-08-08 2016-02-11 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
US10276671B2 (en) * 2016-12-28 2019-04-30 Fujitsu Limited Semiconductor device, method for manufacturing semiconductor device, and electronic device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6195536A (en) * 1984-10-16 1986-05-14 Sanken Electric Co Ltd Manufacture of resin-sealed type semiconductor device
KR20020035841A (en) * 1999-07-28 2002-05-15 가나이 쓰토무 Semiconductor device
JP2003332508A (en) * 2002-05-16 2003-11-21 Renesas Technology Corp Semiconductor device and its manufacturing method
TWI288443B (en) * 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
JP4489485B2 (en) * 2004-03-31 2010-06-23 株式会社ルネサステクノロジ Semiconductor device
JP5343301B2 (en) * 2005-11-28 2013-11-13 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US8193526B2 (en) * 2007-08-07 2012-06-05 Panasonic Corporation Transistor having an organic semiconductor with a hollow space
US8907473B2 (en) * 2009-02-02 2014-12-09 Estivation Properties Llc Semiconductor device having a diamond substrate heat spreader
JP2014060245A (en) * 2012-09-18 2014-04-03 Mitsubishi Electric Corp Semiconductor device
JP6299665B2 (en) * 2015-04-30 2018-03-28 三菱電機株式会社 Field effect transistor

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408742A (en) * 1991-10-28 1995-04-25 Martin Marietta Corporation Process for making air bridges for integrated circuits
JPH05335343A (en) 1992-05-27 1993-12-17 Sony Corp Field effect transistor
US6424006B1 (en) * 1995-06-20 2002-07-23 Infineon Technologies Ag Semiconductor component
US5966520A (en) * 1995-11-03 1999-10-12 Motorola, Inc. Method of designing unit FET cells with unconditional stability
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US20020140007A1 (en) * 2001-03-30 2002-10-03 Fujitsu Quantum Devices Limited Semiconductor device and method for fabricating the same
US6724067B2 (en) * 2001-04-13 2004-04-20 Anadigics, Inc. Low stress thermal and electrical interconnects for heterojunction bipolar transistors
US20040058485A1 (en) 2002-08-29 2004-03-25 Fujitsu Limited Semiconductor device with mushroom gate
JP4284639B2 (en) 2002-08-29 2009-06-24 富士通株式会社 Manufacturing method of semiconductor device
JP2009176930A (en) 2008-01-24 2009-08-06 Toshiba Corp Semiconductor device and manufacturing method thereof
US20090189200A1 (en) 2008-01-24 2009-07-30 Kabushiki Kaisha Toshiba Semiconductor device and fabrication method of the semiconductor device
US20120133440A1 (en) * 2010-11-26 2012-05-31 Kabushiki Kaisha Toshiba Power amplifying device and coupled power amplifying device
US20120267795A1 (en) * 2011-04-21 2012-10-25 Sumitomo Electric Device Innovations, Inc. Semiconductor device
US20130056875A1 (en) 2011-09-01 2013-03-07 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
JP2013055126A (en) 2011-09-01 2013-03-21 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
US20140103434A1 (en) * 2012-10-11 2014-04-17 International Business Machines Corporation Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages
US20140306231A1 (en) 2013-04-16 2014-10-16 Fujitsu Limited Semiconductor device and method of manufacturing the same
JP2014209522A (en) 2013-04-16 2014-11-06 富士通株式会社 Semiconductor device and manufacturing method of the same
US20150060946A1 (en) 2013-08-27 2015-03-05 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
JP2015046445A (en) 2013-08-27 2015-03-12 富士通株式会社 Compound semiconductor device and method of manufacturing the same
US20160042994A1 (en) 2014-08-08 2016-02-11 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
JP2016039319A (en) 2014-08-08 2016-03-22 三菱電機株式会社 Semiconductor equipment manufacturing method
US10276671B2 (en) * 2016-12-28 2019-04-30 Fujitsu Limited Semiconductor device, method for manufacturing semiconductor device, and electronic device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
An Office Action mailed by Taiwanese Patent Office dated Oct. 19, 2018, which corresponds to Taiwanese Patent Application No. 106116429.
International Search Report; Written Opinion; and Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration issued in PCT/JP2017/014100; dated Jun. 20, 2017.
Takayuki Hisaka et al., Simultaneous achievement of high performance and high reliability on a 38/77 GHz InGaAs/AlGaAs Phemtmmic, IEICE Electronics Express, Apr. 25, 2010, vol. 7, No. 8, p. 558-562, Cambridge MA, USA.

Also Published As

Publication number Publication date
TW201843778A (en) 2018-12-16
WO2018185839A1 (en) 2018-10-11
US20200020632A1 (en) 2020-01-16
JP6222419B1 (en) 2017-11-01
JPWO2018185839A1 (en) 2019-04-11
KR102177894B1 (en) 2020-11-12
CN110476231A (en) 2019-11-19
KR20190117756A (en) 2019-10-16
DE112017007395T5 (en) 2019-12-12
TWI659506B (en) 2019-05-11

Similar Documents

Publication Publication Date Title
US11088074B2 (en) Semiconductor device and method for manufacturing same
KR102199173B1 (en) High Electron Mobility Transistor
JP2017188685A (en) Semiconductor device
JP5162826B2 (en) Semiconductor device and manufacturing method thereof
KR101685834B1 (en) Method for manufacturing semiconductor device
US7358179B2 (en) Method of manufacturing semiconductor device including air space formed around gate electrode
JPS5914906B2 (en) Method for manufacturing field effect transistors
US20120193795A1 (en) Semiconductor device having an airbridge and method of fabricating the same
JPH11274175A (en) Semiconductor device and its manufacture
US11094792B2 (en) Manufacturing method of split gate structure and split gate structure
TW548845B (en) Schottky barrier diode and method for producing the same
KR102497370B1 (en) Manufacturing method of semiconductor device
JP2012069987A (en) Method of manufacturing semiconductor device
US20110053336A1 (en) Method for selective deposition of dielectric layers on semiconductor structures
JPWO2007083354A1 (en) Semiconductor device and manufacturing method thereof
KR100211941B1 (en) Method for fabricating heterojunction bipolar device
CN112435927A (en) Preparation process method of GaN device
US9406774B1 (en) Field effect transistor and method of making
TW202320284A (en) Semiconductor structure and method of fabricating the same
CN110767650A (en) SMIM capacitor structure for improving breakdown resistance and manufacturing method
JP2006073787A (en) Semiconductor device and its manufacturing method
JP2002043317A (en) Method for manufacturing semiconductor device
KR19990055175A (en) Metal wiring formation method of semiconductor device
JPS59123269A (en) Manufacture of semiconductor device
JPS61242084A (en) Manufacture of field-effect transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI ELECTRIC CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAEDA, KAZUHIRO;HISAKA, TAKAYUKI;KURUSU, HITOSHI;SIGNING DATES FROM 20190513 TO 20190523;REEL/FRAME:049551/0499

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE