JPS61242084A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form a recessed region dug into an operating layer to a section nearer to a source, and to realize a FET having higher performance by etching a metallic film on the source side up to the depth of a section coated with an etching-resistant material. CONSTITUTION:An insulating film 3, a metallic film 4 and an etching-resistant material 5 are shaped onto an operating layer 2, sections except sections corresponding to source-drain electrodes in the etching-resistant material 5 are removed, and the source side is etched in quantity more than the drain side in the metallic film 4. The insulating film 3 is etched to expose the operating layer 2 only by the width of gate electrodes G, recessed regions are formed to the operating layer, and a Schottky gate metal is evaporated, thus shaping the gate electrodes G. The insulating film sections except sections, on which the Schottky gate metal directly deposits, and deposit films on the insulating film sections are removed, an ohmic metal is evaporated, and the residual insulating films and the deposit films on the insulating films are taken away.

Description

DETAILED DESCRIPTION OF THE INVENTION A] Field of Industrial Application The present invention relates to a method for manufacturing an ultra-high frequency field effect transistor using a compound semiconductor.

Town Conventional technology Schottky junction gate type field effect transistor C using GaAS as an ultra-high frequency field effect transistor
FET J is a typical example.

Conventional high gain, high output, and highly reliable GaASFET
Various proposals have been made to obtain the .

The source and drain electrodes of the combs are arranged alternately,
By placing the gate electrode between them, the output power can be increased by obtaining the maximum gate width with the minimum area, and by creating a single-scess structure in which the channel part where the gate electrode is placed is dug, the drain can have a high withstand voltage. We are trying to

Furthermore, in JP-A No. 56-131963, in order to obtain high gate reverse breakdown voltage and low source resistance, the gate electrode is connected to the source electrode. ! It is formed in a biased manner. However, since it is necessary to deposit the gate electrode diagonally from two directions, a device for this purpose is required.

The procedure for forming the recessed region of the channel portion where the gate electrode is arranged in the source electrode band is as follows. FIGS. 6A) to 6D> are cross-sectional views of the main steps. For example, a 5i02 insulating film (8
form; The insulating film 131 is further coated with photoresist (9)
Coat the insulation pattern 181 and make a window in the desired area.
(Fig. 3 (A) J. The insulating film (8) is etched.
) to form a recess region by etching the n-type active layer +21 to a desired depth, and then depositing a Schottky gate metal to form a gate electrode (G) (Fig. 3 (8)).
). Schottky gate metal deposited on photoresist +91, the photoresist 191 and the insulating film (8)
Remove by etching.

Then, photoresist Ill is applied again, 7-y, windows are opened in the electrode and drain electrode parts, and ohmic metal is deposited (8g3 (C)J, finally the photoresist 1) [1 and deposited on it. F'ET is created by etching away the ohmic and ft stripes (as shown in Figure 6).
). In this case, the gate electrode is deposited from one direction perpendicular to the surface, so no special equipment is required. However, in the case of this type of ultra-high frequency FET, the source, drain! The interelectrode distance 1 sd is less than 3 am, and the comb-shaped source and train electrodes are arranged alternately, making it extremely difficult to align the gate electrode with the source and drain electrodes. Expensive alignment equipment is required.

c) Problems to be Solved by the Invention The present invention aims to provide a method for manufacturing an ultra-high frequency FET0 in which a gate electrode is arranged in a source electrode band without using the problem.

2) Means for Solving the Problems The present invention forms a metal film and an etching-resistant material on the active layer, removes the portions of the etching-resistant material other than those that are exposed to the source and drain currents, and removes the metal film. Etch the source side more than the drain side. Then, the insulating film is etched to expose the active layer by the width of the gate electrode, a recess region is formed in the active layer, and a Schottky gate metal is deposited. Furthermore, an electric field including removing a part of the insulating film other than that on which the Schottky gate metal is directly deposited and the deposited film thereon, depositing an ohmic metal, and removing the remaining insulating film and the deposited film thereon. This is a method for manufacturing an effect transistor.

By etching deep into the part covered with the gold etching material on the source side, a recessed region dug into the active layer is formed closer to the source.

Example @1 Figures (A) to 0 are cross-sectional views of main parts of the embodiment of the present invention.

FIG. 2 is a plan view showing the electrode arrangement of the FET according to the present invention. +1) is a semi-insulating GaAs substrate with an n-type GaAs active layer +23 epitaxially grown.

However, outside the area surrounded by the dashed line in FIG. 2, the active layer is removed by covering the area with photoresist and immersing it in a tartaric acid-based etching solution to perform etching. Operating layer 1
Insulating film 131 such as polyimide on 2+ and metal lI4
! , here forming A I II+41. The A l
[Coat photoresist (51) on I41 and open a window with a distance of 1 sd (approximately 3 μm J) between the source and drain electrodes (
Figure 1 (A)). Next, more of the Al@(4) is etched on the drain side and the source side (M1 Fig. 6)).

This is a conductive material that has a smaller ionization tendency than A1, and in this case, the unetched A1 on the PT plate and source side.
41, and in that state, immerse the entire PT board and substrate in a phosphoric acid-based etching solution.

Normally, the window opening is only at the ionization part of A1.
The bond between Al”+3e J, hydrogen ion, and electron (2+ H+ 2e = H2t) causes the reaction A l no engineering?
f:/g is performed, but on the side that is in conduction with the PT plate, bonding of hydrogen ions and electrons also occurs on the surface of the PT plate, so melting of Al is promoted, and as a result, it is in conduction with the Pt plate. A1 on the side is etched more than A1 on the non-conducting side.

The insulating film 1 exposed by etching the Al sliding door (4)
31 is etched using a hydrazine solution to expose the active layer 12 by a width corresponding to the gate electrode. This exposed working layer (21) was replaced with tartaric acid-H2O2moz
After slightly etching with a etchant to obtain a recessed area, a Schottky junction is formed with the active layer 12).
A gate electrode G) is formed by depositing u-Pt-Ti.

In this vapor deposition process, photoresist 151. Insulating film 13
Au-Pt-Ti is also deposited on the + (FIG. 10).

Photoresist (5) and Au-Pt deposited on it
-Ti is removed using a photoresist etchant, and A1 (4) is further removed using a phosphoric acid-based eftinda solution. Next, the exposed insulating film 131 was masked with Au-Pt-Ti.

Dry etching (see Figure 1)]. Continuing.

A source electrode (S) and a drain electrode (DJ are obtained by depositing, for example, N1-(Au+Ge), which forms an ohmic contact with the active layer (21).
). The last remaining insulating film 131 is deposited on top of Au-Pt-Ti! : By removing it together with N1-(Au+Ge) using a hydrazine solution, an ultra-high frequency FET is completed (1@Figure 1).

[Effects of the Invention] As is clear from the above description, the present invention enables the recessed region forming the gate electrode to be precisely placed close to the source without using an expensive alignment technique or an expensive alignment device. Since the electrodes can also be deposited by conventional methods, an FET with higher performance can be achieved without increasing costs.

[Brief explanation of drawings]

Figures 1(A) to 0 are cross-sectional views of the main steps of the embodiment of the present invention, Figure 2 is a flat C diagram showing the electrode arrangement of the FET, and Figures 3) to 0) are main points showing the conventional manufacturing method. It is a sectional view of a part. Width...semi-insulating GfaAS substrate, (2T...n-type operating layer. +3+...insulating film, 141...A1 electrode, ◎...source electrode, G)...gate electrode, ■ )...Drain electrode.

Claims (1)

[Claims] (1) There is a semiconductor active layer region on a semi-insulating substrate, a source electrode and a drain electrode are arranged on the active layer region, and an electric field having a junction type gate electrode between the source and drain electrodes near the source electrode. In a method for manufacturing an effect transistor, a step of forming an insulating film and further a metal film on an active layer, a step of covering the metal film with an etching-resistant material and selectively opening the etching-resistant material, and a step of forming a source side from a drain side. etching more of the metal film, etching the exposed insulating film to expose the active layer by the width of the gate electrode, etching the exposed surface of the active layer, and etching the etching-resistant material. and a step of vapor depositing a Schottky gate metal using an insulating film as a mask to form a gate electrode, a Schottky gate metal on the etching-resistant material, an insulation not covered by the etching-resistant material, the metal film, and the Schottky gate metal. An electric field characterized by comprising the following steps: removing a film portion, depositing an ohmic metal to form source and drain electrodes, and removing the remaining insulating film and the Schottky gate metal and ohmic metal thereon. Method of manufacturing effect transistors.