JP2006073787A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses film floating and peel-off near a via-hole in a heat treatment process after plated wiring, and maintains high yielding and high reliability. <P>SOLUTION: In this semiconductor device, a convex step 4 is formed on a semiconductor substrate 1, a via hole 2 is formed as penetrating from the top face of the step 4 to the rear of the substrate 1, first plated wiring 6 is formed in the via hole 2 with a seed layer 5 as a lower layer, and the surface of the substrate 1 is covered with an insulating film 3. In addition, the first plated wiring 6 is formed as covering the step 4, an electrode 8 is provided over the rear of the semiconductor substrate 1, and the first plated wiring 6 is connected to the electrode 8 at the rear of the substrate 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a via hole and a manufacturing method, and more particularly to suppression of film peeling by heat treatment after formation of a plated wiring after formation of a via hole.

  In recent years, the frequency band of mobile communication devices such as mobile phones has been increased from the MHz band to the GHz band. Gallium arsenide (GaAs) field effect transistors (FETs) and heterojunction bipolar transistors (HBTs) are widely used in frequency conversion circuits and signal amplification circuits in the reception / transmission units of these mobile communication devices. The FET or HBT is formed on a compound semiconductor substrate made of GaAs or InGaAs, and the electrode of the transistor on the substrate is electrically connected to the lead frame or the mounting substrate. This transistor electrode is connected to the lead frame or the mounting board electrode by forming a through hole (via hole) in the compound semiconductor substrate on which the transistor is formed, and using this, the electrical connection between the transistor electrode and the lead frame or mounting board is made. Connection is made (see Patent Document 1).

  A semiconductor element in which via holes are formed in a conventional compound semiconductor substrate to externally connect transistor electrodes to a lead frame or a mounting substrate will be described with reference to FIG. A transistor is formed on the upper surface (not shown) of the semi-insulating substrate 1 made of GaAs.

The insulating film 3 formed on the semiconductor substrate 1 is opened by etching, and then the semiconductor substrate 1 is further etched to form a via hole 2 up to a depth in the middle of the substrate. Thereafter, the metal wiring 5 connected to the electrode of the transistor is formed in the via hole 2 and on the surface of the semiconductor substrate 1, and the plated wiring 6 is further formed. The substrate 1 is polished until it reaches the metal surface of the via hole 2, and a back surface metal film 8 made of gold is formed on the back surface of the substrate 1, and is connected to a lead frame to be mounted or an electrode of the mounting substrate.
JP 11-168104 A

  However, when a via hole is formed on a substrate and a plated wiring is formed as described above, an insulating film floats and peels off around the via hole due to a heat treatment process after the plated wiring is formed, and reliability and yield are increased. The problem of affecting the problem occurred.

  In order to alleviate the film stress, reducing the stress of the insulating film deposited on the substrate and reducing the stress of the plated wiring after forming the via hole did not improve.

  The present invention relates to a semiconductor element having a via hole on a semiconductor substrate, and a semiconductor element capable of suppressing the film floating and film peeling around the via hole in the heat treatment step after the plating wiring is formed. The purpose is to provide a method.

  In order to solve the above problems, a semiconductor element of the present invention is a semiconductor element in which a via hole is formed in a semiconductor substrate having a stepped portion on the surface, and the via hole reaches the back surface of the substrate from the upper surface of the stepped portion. The conductor is formed on the side wall of the via hole, and the conductor is formed to extend over the entire step portion.

  Preferably, GaAs or InGaAs is exposed on the substrate surface where the via hole is formed and is in contact with the conductor.

  It is preferable that the surface of the step portion is either GaAs or InGaAs.

  The conductor is preferably used as a wiring that connects between semiconductor elements formed on a semiconductor substrate.

  It is preferable that the conductor is formed thicker in the peripheral part of the via hole than in other parts.

  When the semiconductor substrate is viewed from above, the distance from the boundary between the thick portion and the thin portion of the conductor to the end of the thin portion of the conductor is the thickness of the thick portion and the thin portion of the conductor. More preferably, the distance is 5 times or more the difference from the thickness.

  It is more preferable that the conductor and the insulating film opening have a rounded shape around the via hole when the semiconductor substrate is viewed from above.

  The method for manufacturing a semiconductor device of the present invention includes a step of etching a semiconductor substrate to form a convex stepped portion, a step of depositing an insulating film on the semiconductor substrate including the stepped portion, and etching the insulating film. A step of exposing the upper surface of the stepped portion, a step of etching the semiconductor substrate to form a via hole reaching the semiconductor substrate from the upper surface of the stepped portion, the semiconductor substrate including the insulating film, and the A step of depositing a seed layer in the via hole; and a step of depositing a conductor on the seed layer, wherein the conductor is formed to cover the stepped portion.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor element, the step of etching a semiconductor substrate to form a convex stepped portion, the step of depositing an insulating film on the semiconductor substrate including the stepped portion, Etching the insulating film to expose the upper surface of the stepped portion; etching the semiconductor substrate to form a via hole reaching the semiconductor substrate from the upper surface of the stepped portion; and the semiconductor including the insulating film Depositing a seed layer on the substrate and in the via hole; depositing a first conductor on the seed layer; and depositing a second conductor on the first conductor. The first conductor is deposited so as to cover the stepped portion, and the second conductor is formed so as to completely cover the first conductor. Features.

  The first conductor is deposited only in the via hole and around the via hole, and the second conductor is deposited around the via hole at a distance between the end of the first conductor and the end of the first conductor. It is preferable that the first conductor is formed to be 5 times or more the thickness of the first conductor.

  In the semiconductor element of the present invention, in a semiconductor element having a via hole, the film stress variation in the lateral direction caused by the heat treatment is provided by providing a step around the via hole with respect to film peeling due to the heat treatment after forming the plated wiring after the via hole is formed. It is possible to suppress film peeling by blocking at a step. Further, by forming the via hole region on the surface of GaAs or InGaAs, film adhesion can be improved and peeling can be suppressed.

  Further, when the plated wiring is formed twice in the via hole and on the substrate surface, the distance between the first plated wiring end and the second plated wiring end is set to 5% of the first plated wiring thickness on the substrate surface. By setting it to be twice or more, it is possible to suppress the film floating and film peeling by suppressing the fluctuation of the film stress caused by the end of the first plated wiring from the upper part by the second plated wiring.

  In addition, by making the insulating film opening pattern and the shape pattern of the first plated wiring circular, the distance from the second plated wiring formed by the rectangular pattern is dispersed, thereby reducing local stress. Thus, film peeling can be suppressed.

  Next, a semiconductor device and a manufacturing method according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has a via hole 2 on a semiconductor substrate 1 having a via hole diameter of 30 to 70 μm and a via hole depth of about 90 to 140 μm. A first plated wiring 6 having a seed layer 5 as a lower layer is formed in the via hole 2, and the surface of the substrate 1 in the vicinity of the via hole 2 is covered with an insulating film 3. An electrode 8 is provided on the entire back surface of the semiconductor substrate 1, the via hole 2 reaches from the surface of the substrate 1 to the back surface, and the first plated wiring 6 formed from the inside to the surface of the substrate 1 is the electrode 8. And connected.

  Hereinafter, the manufacturing method of the semiconductor element in the first embodiment will be described with reference to FIG.

  First, using a resist mask on a semiconductor substrate 1 made of GaAs or InGaAs, a step 4 having a depth of about 200 nm to 300 nm is formed by wet etching in a region where a via hole is to be formed using a phosphoric acid etchant (FIG. 2). (A)).

  Note that in this etching, dry etching using a chlorine-based gas may be used. Thereafter, the insulating film 3 is deposited, and the insulating film 3 is opened 7 by wet etching using a resist mask in a region where a via hole is to be formed. For example, as the insulating film 3 to be deposited, either silane-based plasma SiO or a laminated structure of SiN, SiO and SiN is deposited to a thickness of about 400 nm. Note that the etching at this time may be dry etching using a fluorine-based gas (FIG. 2B).

  Thereafter, using a resist mask having a thickness of about 20 to 27 μm, a via hole 2 having a diameter of 30 to 70 μm and a depth of about 90 to 140 μm is formed by dry etching using a chlorine-based gas (FIG. 2C). ).

  Further, a seed layer 5 for energizing when forming a conductor made of the plated wiring 6 is deposited on the surface of the semiconductor substrate 1 and in the via hole 2 by sputtering. For example, as a seed layer formed by long throw sputtering with a relatively long distance between the wafer and the target of about 170 mm, a thin film having a laminated structure of Ti 45 to 150 nm and Au 100 to 150 nm is deposited. The seed layer 5 may be deposited by either sputtering or vacuum deposition in which the distance between the wafer and the target that is normally used is about 60 mm. Thereafter, a wiring pattern for connecting the elements is selectively formed by electrolytic Au plating using a resist mask (FIG. 2D).

  Next, the substrate 1 is polished from the back surface so that the bottom of the via hole 2 is exposed on the back surface of the substrate 1 (FIG. 2E).

  A metal film is entirely deposited on the back surface of the substrate 1 to form an electrode 8 (FIG. 2F). Thereafter, heat treatment is performed at about 300 ° C. to 350 ° C. in order to reduce the resistance of the plated wiring 6 and the electrode 8 and to recover damage caused by sputtering or the like.

  According to the present embodiment, by providing the step 4 on the surface of the semiconductor substrate 1 before forming the via hole, in the heat treatment step after forming the first plated wiring 6, the first plated wiring 6, In addition, the fluctuation of the film stress generated in the lateral direction of the insulating film 3 is blocked by the step 4, so that the film floating and film peeling of the insulating film 3 can be suppressed.

  The heat treatment step may be performed immediately after the formation of the first plated wiring 6.

(Second Embodiment)
3A and 3B are schematic views of a semiconductor device according to the second embodiment of the present invention. FIG. 3A is a cross-sectional view, and FIG. 3B is a plan view seen from above.

  As shown in FIG. 3A, the semiconductor element of this embodiment includes a first plated wiring 6 formed only in the via hole 2 and a portion covering the stepped portion 4 of the substrate 1, the via hole 2, and the substrate surface. The second plating wiring 9 to be connected to the electrode of the transistor is formed, and these are formed by dividing the plating process into two times.

  As shown in FIG. 3B, in the region where the via hole is to be formed, the shape of the opening 7 of the insulating film 3 is a square, and is formed only in the portion covering the inside of the via hole 2 and the stepped portion 4 of the substrate 1. The same applies to the shape of the first plated wiring 6.

  As shown in FIG. 3, when the wiring width of the first plating wiring 6 is x1 and the wiring width of the second plating wiring 9 is x2, the end portion of the first plating wiring 6 and the second plating wiring 9 are arranged. The distance x to the end of is about half of the difference between x2 and x1. x is set to about 10 to 20 μm and is set to 5 times or more with respect to the thickness t (= 2 μm) of the first plated wiring 6, which occurs in the heat treatment process after the formation of the second plated wiring 9. The fluctuation of the film stress generated in the lateral direction of the insulating film 3 starting from the end of the first plated wiring 6 is suppressed from above by the second plated wiring 9, so that the insulating film 3 floats and peels off. It is possible to suppress.

(Third embodiment)
The semiconductor element in the third embodiment of the present invention is the same as the semiconductor element shown in the second embodiment in that wiring is formed by plating twice, but as shown in FIG. The distance x between the end portion of the wiring 6 and the end portion of the second plating wiring 9 is not less than five times the thickness of the first plating wiring 6, but also the opening pattern of the insulating film 3 and the first By making the shape pattern of the first plated wiring 6 circular, the distance between the opening and each plated wiring end can be evenly distributed, and the local area applied to the second plated wiring 9 and the insulating film 3 can be distributed. It is possible to suppress the film floating and film peeling of the insulating film 3 by reducing the stress.

  A method for manufacturing a semiconductor element in the second and third embodiments of the present invention will be described with reference to FIG.

  First, using a resist mask on a semiconductor substrate 1 made of GaAs or InGaAs, a step 4 having a depth of about 200 nm to 300 nm is formed by wet etching in a region where a via hole is to be formed using a phosphoric acid-based etchant (FIG. 5). (A)).

  Thereafter, the insulating film 3 is deposited, and the insulating film 3 is opened 7 by wet etching with a resist mask in a region where the via hole 2 is to be formed. For example, as the insulating film 3 to be deposited, either silane-based plasma SiO or a laminated structure of SiN, SiO and SiN is deposited to a thickness of about 400 nm. The resist mask used for etching the insulating film 3 may be formed by the square pattern shown in FIG. 3B or the circular pattern shown in FIG. In addition, the etching at this time may be dry etching using a fluorine-based gas (FIG. 5B).

  Thereafter, using a resist mask having a thickness of about 20 to 27 μm, via holes 2 having a diameter of 30 to 70 μm and a depth of about 90 to 140 μm are formed by dry etching using a chlorine-based gas (FIG. 5C). ).

  Thereafter, a seed layer 5 for energizing when forming a conductor made of the plated wiring 6 is deposited on the surface of the semiconductor substrate 1 and in the via hole 2 by sputtering. For example, the seed layer 5 formed by long throw sputtering with a relatively long distance between the wafer and the target of about 170 mm deposits a thin film having a laminated structure of Ti 45 to 150 nm and Au 100 to 150 nm.

  The seed layer 5 may be deposited by either sputtering or vacuum deposition in which the distance between the wafer and the target that is normally used is about 60 mm. Thereafter, the first plated wiring 6 is selectively formed only in the via hole 2 by electrolytic Au plating using a resist mask.

  When the opening pattern of the insulating film 3 is formed in a circular shape, the resist mask for forming the first plated wiring 6 may be formed in a circular pattern (FIG. 5D).

  Thereafter, when forming a wiring pattern for connecting elements, selective electrolysis is performed using a resist mask for the wiring pattern formed at a distance of at least five times the plating film thickness of the first plating wiring 6. A second plated wiring 9 is formed by Au plating (FIG. 5E).

  Next, after polishing the substrate 1 from the back surface so that the bottom of the via hole 2 is exposed on the back surface of the substrate 1, a metal film is entirely deposited on the back surface of the substrate 1 to form an electrode 8 (see FIG. 5 (f)).

  As described above, according to the present embodiment, in the heat treatment step after the second plated wiring 9 is formed, the film generated in the lateral direction of the insulating film 3 with the end portion of the first plated wiring 6 as a base point By suppressing the fluctuation of stress from the upper part by the second plated wiring 9, it is possible to suppress the film floating and film peeling of the insulating film 3. Further, by making the opening pattern of the insulating film 3 and the shape pattern of the first plated wiring 6 circular, the distance between the opening and each plated wiring end can be evenly distributed. By reducing the local stress applied to the plated wiring 9 and the insulating film 3, it is possible to suppress film floating and film peeling of the insulating film 3.

  In the first to third embodiments, GaAs or InGaAs is exposed on the surface of the semiconductor substrate 1.

  This is because the GaAs and InGaAs layers are not affected by the surface natural oxide film due to the inclusion of Al, as compared with AlGaAs, etc., so that the film adhesion of the insulating film is improved and in the heat treatment process after the plating wiring is formed. This is because the effect of suppressing the occurrence of film peeling becomes greater.

  In the first to third embodiments, the substrate 1 itself is made of GaAs or InGaAs, but the same effect can be obtained if only the surface of the stepped portion formed around the via hole is made of GaAs or InGaAs.

  The semiconductor element according to the present invention is useful as a semiconductor element having high yield and high reliability because it can suppress film peeling due to heat treatment after formation of a plated wiring after formation of a via hole.

Sectional drawing of the semiconductor element in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor element in the 1st Embodiment of this invention It is the schematic diagram of the semiconductor element in the 2nd Embodiment of this invention, (a) is sectional drawing, (b) is the top view seen from the top The top view of the semiconductor element in the 3rd Embodiment of this invention Process sectional drawing which shows the manufacturing method of the semiconductor element in the 2nd and 3rd embodiment of this invention Sectional view of a conventional semiconductor device

Explanation of symbols

1 Semiconductor substrate (GaAs, InGaAs)
2 Via hole 3 Insulating film 4 Step 5 Seed layer 6 First plating wiring 7 Insulating film opening 8 Back electrode 9 Second plating wiring

Claims (10)

A semiconductor element in which a via hole is formed in a semiconductor substrate having a stepped portion on the surface,
The via hole is formed to reach the back surface of the substrate from the upper surface of the stepped portion,
A conductor is formed on the side wall of the via hole,
The semiconductor element, wherein the conductor is formed to extend over the entire step portion. A semiconductor device, wherein the via hole is formed and GaAs or InGaAs is exposed on a substrate surface in contact with the conductor. 2. The semiconductor element according to claim 1, wherein the surface of the stepped portion is either GaAs or InGaAs. The semiconductor element according to claim 1, wherein the conductor is used as a wiring connecting between semiconductor elements formed on a semiconductor substrate. The semiconductor element according to claim 1, wherein the conductor is formed thicker in the peripheral portion of the via hole than in other portions. When the semiconductor substrate is viewed from above, the distance from the boundary between the thick portion and the thin portion of the conductor to the end of the thin portion of the conductor is the thickness of the thick portion and the thin portion of the conductor. 6. The semiconductor element according to claim 5, wherein the semiconductor element is separated by 5 times or more of the difference from the thickness. The semiconductor element according to claim 5, wherein when viewed from above, the conductor and the insulating film opening have a rounded shape around the via hole. Etching the semiconductor substrate to form a convex stepped portion;
Depositing an insulating film on the semiconductor substrate including the stepped portion;
Etching the insulating film to expose the upper surface of the stepped portion;
Etching the semiconductor substrate to form a via hole reaching the semiconductor substrate from the upper surface of the stepped portion;
Depositing a seed layer on the semiconductor substrate including the insulating film and in the via hole;
Depositing a conductor on the seed layer,
The method of manufacturing a semiconductor element, wherein the conductor is formed so as to cover the stepped portion. Etching the semiconductor substrate to form a convex stepped portion;
Depositing an insulating film on the semiconductor substrate including the stepped portion;
Etching the insulating film to expose the upper surface of the stepped portion;
Etching the semiconductor substrate to form a via hole reaching the semiconductor substrate from the upper surface of the stepped portion;
Depositing a seed layer on the semiconductor substrate including the insulating film and in the via hole;
Depositing a first conductor on the seed layer;
Depositing a second conductor on the first conductor; and
The first conductor is deposited so as to cover the stepped portion;
The method of manufacturing a semiconductor element, wherein the second conductor is formed so as to completely cover the first conductor. The first conductor is deposited only in the via hole and around the via hole,
The second conductor is formed such that the distance between the end of the first conductor and the end of the first conductor is at least five times the thickness of the first conductor deposited around the via hole. The method of manufacturing a semiconductor device according to claim 9.

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