JP2007317887A - Method for forming through-hole electrode - Google Patents

Method for forming through-hole electrode Download PDF

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JP2007317887A
JP2007317887A JP2006145814A JP2006145814A JP2007317887A JP 2007317887 A JP2007317887 A JP 2007317887A JP 2006145814 A JP2006145814 A JP 2006145814A JP 2006145814 A JP2006145814 A JP 2006145814A JP 2007317887 A JP2007317887 A JP 2007317887A
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substrate
step
surface
formed
upper surface
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JP4950559B2 (en
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Ryoji Imai
Narimasa Iwamoto
Hiroshi Iwano
Yoshiharu Nakamura
Tomohiro Nakatani
芳春 中村
友洋 中谷
良治 今井
成正 岩本
博 岩野
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Matsushita Electric Works Ltd
松下電工株式会社
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Abstract

When a portion of a conductive film formed on one surface of a substrate is removed by polishing, occurrence of peeling of the conductive film to be a through-hole electrode is reduced.
Through holes 2 and 2 are formed in a substrate 1 by sandblasting. Thereafter, blast particles having a predetermined type and particle size are sprayed again at a predetermined pressure on the upper surface 10 of the substrate 1 by the sand blasting method to roughen the upper surface 10 of the substrate 1. Thereafter, the substrate 1 is cleaned. Thereafter, the sheet metal layer 4 is integrally formed from the upper surface 10 of the substrate 1 to the wall surface 22 of each through hole 2. Thereafter, copper plating is formed on the entire surface of the sheet metal layer 4 to form the metal plating layer 5. Thereafter, the upper surface 10 side of the substrate 1 is polished simultaneously with etching by a chemical mechanical polishing method, and portions of the sheet metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the substrate 1 are removed by polishing. Hole electrodes 3 and 3 are formed in the through holes 2 and 2 of the substrate 1.
[Selection] Figure 1

Description

  The present invention relates to a method for forming a through-hole electrode in a substrate used in, for example, a semiconductor device.

  Conventionally, as an example of a through-hole structure of a substrate used in, for example, a semiconductor device, as shown in FIG. 4D, through-holes 71 and 71 are formed in the substrate 70, and each through-hole 71 has the first conventional example. Some have through-hole electrodes 72 provided. The through hole electrode 72 of the first conventional example is formed in order to conduct between the upper surface 700 and the lower surface 701 of the substrate 70.

  Next, a method for forming the through hole electrode 72 of the first conventional example will be described. First, as shown in FIG. 4A, through holes 71 and 71 are formed in the substrate 70. Subsequently, as shown in FIG. 4B, the sheet metal layer 73 is integrally formed from the upper surface 700 and the lower surface 701 of the substrate 70 to the wall surface 710 of each through hole 71. The sheet metal layer 73 is a conductive film having, for example, a one-layer configuration of an aluminum (Al) layer or a two-layer configuration of a chromium (Cr) layer / copper (Cu) layer. The thickness of the sheet metal layer 73 is 0.02 μm or more and 0.5 μm or less. Thereafter, a metal plating layer 74 is formed on the entire surface of the sheet metal layer 73 as shown in FIG. The metal plating layer 74 is a conductive film such as copper, silver (Ag), nickel (Ni), or gold (Au). The thickness of the metal plating layer 74 is 1 μm or more and 100 μm or less. Thereafter, portions of the sheet metal layer 73 and the metal plating layer 74 formed on the upper surface 700 and the lower surface 701 of the substrate 70 are polished and removed. As described above, the through hole electrode 72 of the first conventional example can be formed on the substrate 70.

As another example of the conventional through-hole structure, Patent Document 1 provides a through-hole electrode (through-hole electrode of the second conventional example) for electrically connecting the upper and lower wiring circuits of the interlayer insulating film. A through-hole structure is disclosed. The through hole electrode of the second conventional example is the same as the through hole electrode of the first conventional example by a forming method including a step of removing a portion formed on the upper surface of the interlayer insulating film among the conductive films of the sheet metal layer and the plated metal layer. Similarly, it is formed on the substrate.
JP 11-163129 A (pages 2 and 3 and FIGS. 1 and 2)

  However, in the first conventional example of the method for forming a through-hole electrode, the adhesion between the portion of the conductive film (sheet metal layer 73 and metal plating layer 74) formed on the upper surface 700 of the substrate 70 and the substrate 70 is low. Since there is a shortage, peeling of the conductive film occurs. In this state, when the portion of the conductive film formed on the upper surface 700 of the substrate 70 is polished and removed, the conductive film that becomes the through-hole electrode 72 is peeled off in a wide range and with a high frequency as shown in FIG. There was a problem that it occurred. Also, the through hole electrode forming method of the second conventional example is formed on the upper surface of the interlayer insulating film in the conductive film (sheet metal layer and plated metal layer) in the same manner as the through hole electrode forming method of the first conventional example. Since the adhesion between the exposed portion and the interlayer insulating film is insufficient, when the portion of the conductive film formed on the upper surface of the interlayer insulating film is removed by polishing, the conductive film that becomes the through-hole electrode is not peeled off. There was a problem that it occurred in a wide range and with high frequency.

  The present invention has been made in view of the above points. The object of the present invention is to provide a conductive film that becomes a through-hole electrode when a portion of the conductive film formed on one surface of the substrate is removed by polishing. An object of the present invention is to provide a method of forming a through-hole electrode that can reduce the occurrence of film peeling.

  The invention according to claim 1 is a first step of forming a through hole in a substrate, a second step of roughening one surface of the substrate, and the substrate after the first step and the second step. A third step of integrally forming a conductive film from the one surface to the wall surface of the through hole, and a portion of the conductive film formed on the one surface of the substrate after the third step is polished and removed And a fourth step.

  According to this method, a portion of the conductive film formed on one surface of the substrate is formed by roughening one surface of the substrate and then forming the conductive film from the one surface to the wall surface of the through hole. Can be improved by an anchor effect, so that when a portion of the conductive film formed on one surface of the substrate is removed by polishing, a through-hole electrode is formed. Generation | occurrence | production of peeling of an electrically conductive film can be reduced.

  The invention according to claim 2 is a first step of forming a recess on one surface of the substrate, a second step of roughening the one surface of the substrate, the first step and the second step. And a third step of integrally forming a conductive film from the one surface of the substrate to a wall surface and a bottom surface of the recess, and forming at least one of the conductive films on the one surface of the substrate after the third step. A fourth step of polishing and removing the portion that has been removed, and at least after the third step, the portion of the conductive film formed on the bottom surface of the recess faces the other surface of the substrate facing the one surface And a fifth step of polishing the other surface side of the substrate until it is exposed to the surface of the substrate to form a through hole.

  According to this method, the conductive film is formed on one surface of the conductive film by roughening one surface of the substrate and then forming the conductive film from the one surface to the wall surface and the bottom surface of the recess. Since the adhesion force between the portion and one surface of the substrate can be improved by the anchor effect, when the portion of the conductive film formed on the one surface of the substrate is removed by polishing, Occurrence of peeling of the conductive film can be reduced. Further, by exposing a portion of the conductive film formed on the bottom surface of the recess to the other surface side of the substrate, an airtight through hole can be formed in the substrate.

  The invention according to claim 3 is the invention according to claim 1 or 2, wherein the second step is a step of roughening the one surface of the substrate using abrasive grains by a sandblast method. It is characterized by. According to this method, one surface of the substrate can be roughened in a short time.

  The invention according to claim 4 is the invention according to claim 3, wherein the grain size of the abrasive grains is # 600 or more and # 2000 or less as defined in JIS R 6001. According to this method, abrasive grains having a grain size of # 600 or more and # 2000 or less are sprayed on one surface of the substrate to form irregularities having a surface roughness of 2 μm or more and 6 μm or less on one surface of the substrate. The adhesion between the portion of the conductive film formed on one surface of the substrate and the one surface of the substrate can be maximized.

  The invention according to claim 5 is the invention according to claim 3 or 4, further comprising a sixth step of cleaning the substrate between the second step and the third step. According to this method, the abrasive grains remaining on the substrate can be removed.

  The invention according to claim 6 is the invention according to claim 1 or 2, wherein the second step is a step of roughening the one surface of the substrate by a dry etching method. . According to this method, since the abrasive grains and the like do not remain after the one surface of the substrate is roughened, the cleaning step can be omitted, and the cost can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, when the part formed in the one surface of the board | substrate among the electrically conductive films is grind | polished off, generation | occurrence | production of peeling of the electrically conductive film used as a through-hole electrode can be reduced.

(Embodiment 1)
Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a process diagram showing a method for forming a through-hole electrode.

  First, the through hole structure of Embodiment 1 will be described. The through-hole structure of the first embodiment is used in, for example, a semiconductor device, and as shown in FIG. 1E, through-holes 2 and 2 are formed in a substrate 1, and through-hole electrodes 3 are provided in each through-hole 2. It is what was done.

  The substrate 1 is made of, for example, a silicon-based material such as silicon (Si) or a silicon compound, or glass. Although the thickness of this board | substrate 1 is not limited, It is preferable that it is the range of 100 micrometers or more and 1 cm or less.

  Each through-hole 2 is formed to communicate between the upper surface 10 and the lower surface 11 of the substrate 1 in a circular shape when viewed from the upper surface 10 of the substrate 1 by, for example, sandblasting. The through hole 2 is formed in a tapered shape in which the inner diameter gradually decreases from the upper surface opening 20 toward the lower surface opening 21. The diameter of the through hole 2 when viewed from the upper surface 10 of the substrate 1 is not limited, but is preferably in the range of 10 μm to 1 mm.

  The through-hole electrode 3 includes a sheet metal layer 4 and a metal plating layer 5, and conducts a conductive region (not shown) on the upper surface 10 of the substrate 1 and a conductive region (not shown) on the lower surface 11. is there. The sheet metal layer 4 is a conductive film made of, for example, aluminum, copper, chromium, or a metal material mainly composed of these, and is formed on the wall surface 22 of the through hole 2. The metal plating layer 5 is a conductive film made of, for example, copper, silver, nickel, gold, or a metal material containing these as a main component, and is formed on the surface of the sheet metal layer 4. The thickness of the through-hole electrode 3 is not limited, but is preferably in the range of 1 μm to 100 μm.

  Next, a method for forming the through-hole electrode 3 of Embodiment 1 will be described. Here, a glass substrate is used as the substrate 1. First, the substrate 1 is mask-exposed with a sheet resist and developed (step A1). After step A1, as shown in FIG. 1A, through holes 2 and 2 are formed in the substrate 1 by sandblasting (step A2). After step A2, the sheet resist is peeled from the substrate 1 (step A3).

  After step A3, as shown in FIG. 2 (b), blast particles (abrasive grains) are sprayed onto the upper surface 10 of the substrate 1 at a pressure of 0.2 MPa or more and 0.5 MPa or less by a sand blasting method. Is roughened (step A4). The blast particles used in step A4 are, for example, alumina particles, glass particles, silicon carbide particles, iron particles, etc., and have a particle size of 3 μm or more and 100 μm or less. In step A4, the surface roughness of the upper surface 10 of the substrate 1 can be set to 0.5 μm or more and 100 μm or less by setting the type, particle size, spraying pressure, and the like of the blast particles. The surface roughness is the difference between the peak portion and the valley portion on the surface.

  After step A4, the substrate 1 is subjected to ultrasonic cleaning and cleaning with a surfactant (step A5). After step A5, as shown in FIG. 1C, chromium having a thickness of 0.02 μm or more and 0.5 μm or less is formed as a first layer from the upper surface 10 of the substrate 1 to the wall surface 22 of each through hole 2. The sheet metal layer 4 is integrally formed by forming a copper layer having a thickness of 0.02 μm or more and 0.6 μm or less by sputtering as a layer (step A6). After step A6, the substrate 1 is put into a plating tank (not shown) in which a plating solution mainly composed of copper sulfate and a surface active agent is stored, and as shown in FIG. A copper plating having a thickness of 1 μm or more and 100 μm or less is formed on the entire surface of 4 to form a metal plating layer 5 (step A7).

  After the step A7, the substrate 1 is bonded to a polishing plate (not shown) and rotated, and the upper surface 10 side of the substrate 1 is polished simultaneously with etching by a chemical mechanical polishing method to obtain a sheet metal layer. 4 and the portion of the metal plating layer 5 formed on the upper surface 10 of the substrate 1 are polished and removed chemically and mechanically (step A8). By performing the steps A1 to A8, the through-hole electrodes 3 and 3 can be formed in the through-holes 2 and 2 of the substrate 1 as shown in FIG.

  As described above, according to the first embodiment, the sheet metal layer 4 and the metal plating layer 5 are formed from the upper surface 10 to the wall surface 22 of each through hole 2 after the upper surface 10 of the substrate 1 is roughened by the sandblast method. Since the adhesion between the portion of the metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the substrate 1 and the upper surface 10 of the substrate 1 can be improved by the anchor effect, the sheet metal layer 4 and the metal When the portion of the plating layer 5 formed on the upper surface 10 of the substrate 1 is polished and removed, the sheet metal layer 4 formed on the wall surface 22 of each through hole 2 and the metal plating layer 5 is peeled off. Generation can be reduced. Further, the upper surface 10 of the substrate 1 can be roughened in a short time by a sand blasting method (for example, about 5 minutes per 4 inch wafer). Furthermore, the abrasive grains remaining on the substrate 1 can be removed by cleaning the substrate 1 after roughening the upper surface 10 of the substrate 1.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIG.

  The through-hole structure of the second embodiment is similar to the through-hole structure of the first embodiment, in which through-holes 2 and 2 are formed in the substrate 1 and through-hole electrodes 3 are provided in each through-hole 2 (FIG. 1 (d)).

  Next, a method for forming the through-hole electrode 3 of Embodiment 2 will be described. Here, a glass substrate is used as the substrate 1. First, similarly to the steps A1 to A3 of the first embodiment, the substrate 1 is mask-exposed with a sheet resist, developed (step B1), and the through holes 2 and 2 are formed in the substrate 1 by the sandblast method (step B2). The sheet resist is peeled from the substrate 1 (step B3).

  After Steps B1 to B3, the upper surface 10 of the substrate 1 is roughened by blast particles having a particle size of # 600 or more and # 2000 or less as defined in JIS R 6001 by a sandblasting method (Step B4) (FIG. 1). (See (b)). The blast particles used in step B4 are, for example, alumina particles, glass particles, silicon carbide particles, iron particles, and the like. By the step B4, the surface roughness of the upper surface 10 of the substrate 1 can be set to 2 μm or more and 6 μm or less.

  After step B4, the substrate 1 is washed (step B5) in the same manner as in steps A5 to A8 of the first embodiment, and each through hole 2 is formed from the upper surface 10 of the substrate 1 by sputtering as shown in FIG. The sheet metal layer 4 is integrally formed over the wall surface 22 (step B6), and the metal plating layer 5 is formed on the entire surface of the sheet metal layer 4 (step B7) as shown in FIG. A portion of the sheet metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the sheet metal 1 is chemically and mechanically polished and removed by mechanical polishing (step B8). By performing steps B1 to B8, the through-hole electrodes 3 and 3 can be formed in the through-holes 2 and 2 of the substrate 1 as shown in FIG.

  As described above, according to the second embodiment, blast particles having a particle size of # 600 or more and # 2000 or less as defined by JIS standard are sprayed on the upper surface 10 of the substrate 1 to form irregularities having a surface roughness of 2 μm or more and 6 μm or less. 1 to maximize the adhesion between the portion of the sheet metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the substrate 1 and the upper surface 10 of the substrate 1. it can. Thereby, when the part formed in the upper surface 10 of the board | substrate 1 among the sheet metal layers 4 and the metal plating layers 5 is polished and removed, the sheet metal layer that is formed on the wall surface 22 of each through hole 2 and becomes the through hole electrode 3. Generation | occurrence | production of peeling of 4 and the metal plating layer 5 can further be reduced.

(Embodiment 3)
Embodiment 3 of the present invention will be described with reference to FIG. FIG. 2 is a process diagram illustrating a method for forming a through-hole electrode according to the third embodiment.

  First, the through hole structure of Embodiment 3 will be described. As shown in FIG. 2E, the through-hole structure of the third embodiment is such that through-holes 2 and 2 are formed in the substrate 1 and through-hole electrodes 3a are provided in each through-hole 2. The substrate 1 and the through hole 2 in the third embodiment are the same as the substrate and the through hole in the first embodiment. However, the thickness of the substrate 1 is preferably in the range of 0.5 mm to 1 cm.

  Each through-hole electrode 3 a is formed by closing not only the wall surface 22 of the through-hole 2 but also the lower surface opening 21 of the through-hole 2. Each through-hole electrode 3a is the same as the through-hole electrode 3 (see FIG. 1) of the first embodiment except for the points described above.

  Next, a method for forming the through-hole electrode 3a of Embodiment 3 will be described. Here, a glass substrate is used as the substrate. First, in the same manner as in step A1 of the first embodiment, the substrate 1 is mask-exposed and developed (step C1). After step C1, as shown in FIG. 2A, recesses 6 and 6 are formed on the upper surface 10 of the substrate 1 by a sandblasting method (step C2). Each recess 6 has a diameter of 10 μm or more and 1 mm or less. After step C2, the sheet resist is peeled from the substrate 1 in the same manner as in step A3 of Embodiment 1 (step C3). After the step C3, similarly to the steps A4 and A5 of the first embodiment, the upper surface 10 of the substrate 1 is roughened by the sandblast method (step C4) (see FIG. 2B), and the substrate 1 is washed (step C5). ). In step A4, as in the first embodiment, the surface roughness of the upper surface 10 of the substrate 1 is set to 0.5 μm or more and 100 μm or less by setting the type, particle diameter, spraying pressure, and the like of the blast particles. it can.

  After steps C4 and C5, as shown in FIG. 2C, chromium having a thickness of 0.02 μm or more and 0.5 μm or less as a first layer from the upper surface 10 of the substrate 1 to the wall surface 60 and the bottom surface 61 of each recess 6. As a second layer, a film having a thickness of 0.02 μm or more and 0.6 μm or less is formed by sputtering to form the sheet metal layer 4 integrally (step C6). After step C6, the substrate 1 is put into a plating tank (not shown) storing a plating solution mainly composed of copper sulfate and a surface active agent, and as shown in FIG. A copper plating having a thickness of 1 μm or more and 100 μm or less is formed on the entire surface of 4 to form a metal plating layer 5 (step C7). At this time, the additive of the plating solution is adjusted so that the metal plating layer 5 is formed thick on the bottom surface 61 of each recess 6.

  After the step C7, as in the step A8 of the first embodiment, a portion of the sheet metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the substrate 1 is chemically and mechanically processed by a chemical mechanical polishing method. Then, polishing is removed (step C8). After Step C8, the substrate 1 is exposed until the portion formed on the bottom surface 61 of each recess 6 in the sheet metal layer 4 or the metal plating layer 5 is exposed on the surface on the lower surface 11 side of the substrate 1 by chemical mechanical polishing. The through holes 2 and 2 are formed by chemically and mechanically polishing the lower surface 11 side (step C9). By performing steps C1 to C9, the through-hole electrodes 3a and 3a can be formed in the through-holes 2 and 2 of the substrate 1 as shown in FIG.

  As described above, according to the third embodiment, the sheet metal layer 4 and the metal plating layer 5 are formed from the upper surface 10 to the wall surface 60 of each recess 6 after the upper surface 10 of the substrate 1 is roughened by the sandblasting method, as in the first embodiment. By forming, the adhesion between the portion of the sheet metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the substrate 1 and the upper surface 10 of the substrate 1 can be improved by the anchor effect. The sheet metal layer 4 and the metal plating that are formed on the wall surface 60 of each recess 6 and become the through-hole electrode 3a when the portion formed on the upper surface 10 of the substrate 1 is polished and removed from the sheet metal layer 4 and the metal plating layer 5. Generation | occurrence | production of peeling of the layer 5 can be reduced.

  Further, by exposing the sheet metal layer 4 or the metal plating layer 5 formed on the bottom surface 61 of each recess 6 to the lower surface 11 side of the substrate 1, airtight through holes 2 and 2 can be formed in the substrate 1. it can.

  As a modification of the third embodiment, step C9 may be performed before or simultaneously with step C8. Even with such a forming method, the airtight through holes 2 and 2 can be formed in the substrate 1 as in the third embodiment.

  As another modification of the third embodiment, in step C9, the sheet metal layer 4 formed on the bottom surface 61 of the recess 6 may be removed by polishing simultaneously with the lower surface 11 side of the substrate 1. Since the sheet metal layer 4 is thin, it is often removed by polishing. Even with such a forming method, the airtight through holes 2 and 2 can be formed in the substrate 1 as in the third embodiment.

  As a modification of any one of the first to third embodiments, a silicon substrate may be used as the substrate 1. Even in such a case, the through-hole electrodes 3 (3a) and 3 (3a) can be formed in the through-holes 2 and 2 of the substrate 1 by the same formation method as that for the glass substrate.

  As another modification of any one of the first to third embodiments, in the step of roughening the upper surface 10 of the substrate 1 (steps A4, B4, and C4), for example, by mechanical polishing or the like instead of the sandblast method. The upper surface 10 of the substrate 1 may be roughened. Also by such a forming method, the upper surface 10 of the substrate 1 can be roughened in a short time as in the first to third embodiments.

  As another modified example of any one of the first to third embodiments, a step of roughening the upper surface 10 of the substrate 1 (steps A4, B4, C4), a step of exposing the substrate 1 to a mask with a sheet resist, and developing ( It may be performed before the steps A1, B1, C1) and the step of forming the through holes 2, 2 or the recesses 6, 6 in the substrate 1 (steps A2, B2, C2). Even with such a forming method, it is possible to reduce the occurrence of peeling of the sheet metal layer 4 and the metal plating layer 5 as in the first to third embodiments.

  Furthermore, as another modified example of any one of the first to third embodiments, a sheet resist is again formed on the upper surface 10 of the substrate 1 before the step of roughening the upper surface 10 of the substrate 1 (steps A4, B4, C4). May be exposed to a mask and developed. According to such a forming method, it is possible to prevent the surface of the upper surface 10 of the substrate 1 from being roughened to a portion that does not need to be roughened.

  As another modification of any one of the first to third embodiments, in the step of forming the sheet metal layer 4 on the substrate 1 (steps A6, B6, and C6), a vacuum deposition method or a CVD (Chemical Vapor Deposition) is used instead of the sputtering method. ) And chromium and copper may be formed by the method. Even with such a forming method, the sheet metal layer 4 can be formed on the substrate 1 as in the case of the sputtering method.

(Embodiment 4)
Embodiment 4 of the present invention will be described with reference to FIG. FIG. 3 is a process diagram illustrating a method for forming a through-hole electrode according to the fourth embodiment.

  First, the through hole structure of Embodiment 4 will be described. In the through hole structure of the fourth embodiment, as shown in FIG. 3 (f), through holes 2a and 2a are formed in the substrate 1, and through hole electrodes 3 are provided in the respective through holes 2a. The substrate 1 and the through-hole electrode 3 of the fourth embodiment are the same as the substrate and the through-hole electrode of the first embodiment.

  Each through hole 2a is formed in a cylindrical shape from the upper surface opening 20a to the lower surface opening 21a. The through hole 2a is the same as the through hole 2 (see FIG. 1) of the first embodiment except for the points described above.

  Next, a method for forming the through-hole electrode 3 of Embodiment 4 will be described. Here, a silicon substrate is used as the substrate 1. First, in the same manner as in step A1 of the first embodiment, the substrate 1 is subjected to mask exposure with a sheet resist and developed (step D1). After step D1, as shown in FIG. 3A, through holes 2a and 2a are formed in the substrate 1 by etching (step D2). After step D2, as shown in FIG. 3B, the insulating layer 12 is integrally formed from the upper surface 10 and the lower surface 11 of the substrate 1 to the wall surface 22a of each through hole 2a by a thermal oxidation method (step D3).

  After the step D3, the substrate 1 is placed in a chamber of an ion milling apparatus, and the inside of the chamber is evacuated and then argon is introduced. As shown in FIG. 3C, this is one of dry etching methods. The top surface 10 of the substrate 1 is roughened by ion milling (step D4). The gas used in step D4 is an inert gas argon. By the process D4, the surface roughness of the upper surface 10 of the substrate 1 can be set to an atomic size or more and 10 nm or less. The gas used in step D4 is not limited to argon, and other inert gas may be used depending on the application.

  After step D4, as shown in FIG. 3D, chromium having a thickness of 0.02 μm or more and 0.5 μm or less is applied as a first layer to the upper surface 10 of the substrate 1 and the wall surface 22a of the through hole 2a. As above, copper having a thickness of 0.02 μm or more and 0.6 μm or less is formed by vacuum deposition to form the sheet metal layer 4 (step D5). After step D5, similarly to steps A7 and A8 of the first embodiment, a metal plating layer 5 is formed on the entire surface of the sheet metal layer 4 (step D6) (see FIG. 3E), and chemical mechanical polishing is performed. The portion of the sheet metal layer 4 and the metal plating layer 5 formed on the upper surface 10 of the substrate 1 is chemically and mechanically polished and removed by the method (step D7). By performing steps D1 to D7, the through-hole electrodes 3 and 3 can be formed in the through-holes 2a and 2a of the substrate 1 as shown in FIG.

  As described above, according to the fourth embodiment, the upper surface 10 of the substrate 1 is roughened and simultaneously cleaned by the ion milling method. Thereby, like Embodiment 1, by forming the sheet metal layer 4 and the metal plating layer 5 on the upper surface 10 after roughening the upper surface 10 of the substrate 1, of the sheet metal layer 4 and the metal plating layer 5. Since the adhesion between the portion formed on the upper surface 10 of the substrate 1 and the upper surface 10 of the substrate 1 can be improved by the anchor effect, the upper surface 10 of the substrate 1 among the sheet metal layer 4 and the metal plating layer 5. When polishing and removing the formed portion, the occurrence of peeling of the sheet metal layer 4 and the metal plating layer 5 formed on the wall surface 22a of each through hole 2a and serving as the through hole electrode 3 can be reduced.

  Further, unlike the case of the sandblasting method, the cleaning process is omitted because the upper surface 10 of the substrate 1 is cleaned and blast particles (abrasive grains) do not remain after the upper surface 10 of the substrate 1 is roughened. Therefore, cost reduction can be achieved.

  As a modification of the fourth embodiment, a glass substrate may be used as the substrate 1. Even in such a case, the through-hole electrodes 3 and 3 can be formed in the through-holes 2a and 2a of the substrate 1 by the same formation method as that for the silicon substrate.

  As another modification of the fourth embodiment, in step D3, the insulating layer 12 may be formed on the substrate 1 by the CVD method instead of the thermal oxidation method. Even with such a formation method, the insulating layer 12 can be formed on the substrate 1 as in the case of the thermal oxidation method.

Furthermore, as another modification of the fourth embodiment, in step D4, the upper surface 10 of the substrate 1 may be roughened by another dry etching method such as a plasma etching method or a sputter etching method instead of the ion milling method. In the case of the sputter etching method, an inert gas such as argon is used as in the case of the ion milling method. On the other hand, in the case of the plasma etching method, a reactive gas such as CF 4 gas is used instead of argon, unlike the case of the ion milling method. Even in the formation method as described above, when the portions formed on the upper surface 10 of the substrate 1 in the sheet metal layer 4 and the metal plating layer 5 are polished and removed, as in the case of the ion milling method, The occurrence of peeling of the sheet metal layer 4 and the metal plating layer 5 formed on the wall surface 22a of the hole 2a and serving as the through-hole electrode 3 can be reduced, and the upper surface 10 of the substrate 1 is cleaned. Since the blast particles and the like do not remain after the roughening, the cleaning step can be omitted and the cost can be reduced.

  As another modification of the fourth embodiment, in step D5, copper may be formed by a CVD method or a sputtering method instead of the vacuum evaporation method. Even if it is such a formation method, the sheet metal layer 4 can be formed similarly to the case of a vacuum evaporation method.

  As a modification of any of the first to fourth embodiments, the sheet metal layer 4 is not formed from the upper surface 10 of the roughened substrate 1 to the wall surface 22 (22a) of the through holes 2 (2a) and 2 (2a). The metal plating layer 5 may be integrally formed directly. Even with such a forming method, when the portion of the metal plating layer 5 formed on the upper surface 10 of the substrate 1 is polished and removed, the occurrence of peeling of the metal plating layer 5 that becomes the through-hole electrode 3 is reduced. be able to.

It is process drawing which shows the formation method of the through-hole electrode of Embodiment 1, 2 by this invention. It is process drawing which shows the formation method of the through-hole electrode of Embodiment 3 by this invention. It is process drawing which shows the formation method of the through-hole electrode of Embodiment 4 by this invention. It is process drawing which shows the formation method of the conventional through-hole electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 10 Upper surface 11 Lower surface 2, 2a Through hole 22, 22a Wall surface 3, 3a Through hole electrode 4 Sheet metal layer 5 Metal plating layer 6 Recess 60 Wall surface 61 Bottom surface

Claims (6)

  1. A first step of forming a through hole in the substrate;
    A second step of roughening one surface of the substrate;
    A third step of integrally forming a conductive film from the one surface of the substrate to the wall surface of the through hole after the first step and the second step;
    And a fourth step of polishing and removing a portion of the conductive film formed on the one surface of the substrate after the third step.
  2. A first step of forming a recess in one surface of the substrate;
    A second step of roughening the one surface of the substrate;
    A third step of integrally forming a conductive film from the one surface of the substrate to the wall surface and bottom surface of the recess after the first step and the second step;
    A fourth step of polishing and removing a portion of the conductive film formed on the one surface of the substrate after at least the third step;
    At least after the third step, the other portion of the substrate is exposed until the portion of the conductive film formed on the bottom surface of the recess is exposed on the surface on the other surface side facing the one surface of the substrate. A through-hole electrode forming method comprising: a fifth step of polishing a surface side to form a through-hole.
  3.   The method of forming a through-hole electrode according to claim 1 or 2, wherein the second step is a step of roughening the one surface of the substrate using abrasive grains by a sandblast method.
  4.   The method for forming a through-hole electrode according to claim 3, wherein the grain size of the abrasive grains is # 600 or more and # 2000 or less as defined in JIS R 6001.
  5.   The method for forming a through-hole electrode according to claim 3 or 4, further comprising a sixth step of cleaning the substrate between the second step and the third step.
  6. 3. The method for forming a through-hole electrode according to claim 1, wherein the second step is a step of roughening the one surface of the substrate by a dry etching method.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009290198A (en) * 2008-05-30 2009-12-10 Lg Electronics Inc Soft film and display device
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01105206A (en) * 1987-10-17 1989-04-21 Sumita Kogaku Glass Seizosho:Kk Optical fiber for illumination
JPH02303086A (en) * 1989-05-17 1990-12-17 Hitachi Ltd Manufacture of printed wiring board, and sputter deposition equipment and copper-clad laminate therefor
JPH05129775A (en) * 1991-11-06 1993-05-25 Shirai Denshi Kogyo Kk Manufacture of printed wiring board
JP2002246744A (en) * 2001-02-20 2002-08-30 Nec Corp Conductor-forming method, and multilayer wiring board manufacturing method using the same
JP2003283085A (en) * 2002-03-26 2003-10-03 Nec Kansai Ltd Wiring board
JP2003318550A (en) * 2002-04-18 2003-11-07 Mitsubishi Electric Corp Laminated wiring board and multilayer wiring assembly, and method for manufacturing the same
JP2006066581A (en) * 2004-08-26 2006-03-09 Fuji Photo Film Co Ltd Method of manufacturing conductive pattern material
JP2006073787A (en) * 2004-09-02 2006-03-16 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01105206A (en) * 1987-10-17 1989-04-21 Sumita Kogaku Glass Seizosho:Kk Optical fiber for illumination
JPH02303086A (en) * 1989-05-17 1990-12-17 Hitachi Ltd Manufacture of printed wiring board, and sputter deposition equipment and copper-clad laminate therefor
JPH05129775A (en) * 1991-11-06 1993-05-25 Shirai Denshi Kogyo Kk Manufacture of printed wiring board
JP2002246744A (en) * 2001-02-20 2002-08-30 Nec Corp Conductor-forming method, and multilayer wiring board manufacturing method using the same
JP2003283085A (en) * 2002-03-26 2003-10-03 Nec Kansai Ltd Wiring board
JP2003318550A (en) * 2002-04-18 2003-11-07 Mitsubishi Electric Corp Laminated wiring board and multilayer wiring assembly, and method for manufacturing the same
JP2006066581A (en) * 2004-08-26 2006-03-09 Fuji Photo Film Co Ltd Method of manufacturing conductive pattern material
JP2006073787A (en) * 2004-09-02 2006-03-16 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
JP2009290198A (en) * 2008-05-30 2009-12-10 Lg Electronics Inc Soft film and display device
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US9847277B2 (en) 2010-09-17 2017-12-19 Tessera, Inc. Staged via formation from both sides of chip
US9362203B2 (en) 2010-09-17 2016-06-07 Tessera, Inc. Staged via formation from both sides of chip
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers

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