JP2012216858A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP2012216858A JP2012216858A JP2012135933A JP2012135933A JP2012216858A JP 2012216858 A JP2012216858 A JP 2012216858A JP 2012135933 A JP2012135933 A JP 2012135933A JP 2012135933 A JP2012135933 A JP 2012135933A JP 2012216858 A JP2012216858 A JP 2012216858A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- semiconductor device
- main surface
- power transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】出力電流等が異なる複数の半導体装置PDを製造する場合に、半導体装置PDの制御回路用の半導体チップ4Cが電気的に接続されるリード8Aの配置および本数等は共通にし、半導体装置PDのパワートランジスタ用の半導体チップ4PH,4PLが電気的に接続されるリード8Bの配置および本数等をその半導体装置PDに必要とされる出力電流等に応じて変えるようにした。これにより、半導体装置PDの制御回路(PWM回路)が誤動作するポテンシャルを低減できるので、半導体装置を実装する配線基板の配線パターンの設計を容易にするような半導体装置PDを提供することができる。
【選択図】図8
Description
図1は、本実施の形態1の半導体装置を有するネットワーク電源システム(電子装置)の一例の説明図である。
図22は本発明の他の実施の形態である半導体装置PDの上面側の全体平面図、図23は図22のX2−X2線の断面図である。なお、図22の半導体装置PDの裏面の全体平面図は図5と同じである。また、図22では、説明上、パッケージ5の内部を透かして見せている。また、図22では、図面を見易くするため、リード板35a,35bにハッチングを付している。
前記実施の形態1,2では、出力電流の増大に応じてパワートランジスタ用の半導体チップ4PH,4PLを一方向に長くしてゲート幅を大きくするようにした。しかし、このように半導体チップ4PH,4PLを大きくしていくと、半導体チップ4PH,4PLに加わる応力が大きくなり、半導体チップ4PH,4PLとダイパッド8D2,8D3との接合部に剥離が生じる等、信頼性の確保が困難になる。
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
2 制御回路
3 ドライバ回路
4C 半導体チップ
4PH,4PL 半導体チップ
4HS 半導体基板
4HS1 半導体層
4HS2 エピタキシャル層
5 パッケージ(封止体)
8 リードフレーム(配線基板)
8A,8A1,8A2,8A3,8A4 リード(第1外部端子、配線基板)
8B,8B1,8B2,8B3 リード(第2外部端子、配線基板)
8D1,8D2,8D3 ダイパッド(配線基板)
8L リード配線(配線基板)
10A,10A1,10A2 ボンディングパッド
10GH,10GL ボンディングパッド
10SH,10SL ボンディングパッド
10GF1,10GF2 ゲートフィンガ
12a,12b 接着層
15 配線基板
16A,16B 配線
19 表面保護膜
20L1,20L2 ゲート配線
20G ゲート電極
22 フィールド絶縁膜
23 半導体領域
24 半導体領域
25 溝
26 ゲート絶縁膜
29 絶縁膜
30a,30b コンタクトホール
31 溝
32 半導体領域
35a,35b リード板
36a〜36d 接合層
IN 入力
P1 AC/DC切換モード整流器
P2 DC/DCコンバータ
P3 48V Bricコンバータ
P4 POL電源
P5 PPOD電源
LD 負荷
PD 半導体装置
QH1,QL1 パワーMOS・FET(パワートランジスタ)
Cin 入力コンデンサ
Cout 出力コンデンサ
L コイル
D ドレイン
S ソース
VIN 入力電源
ET1,ET2 端子
N 出力ノード
Dp1,Dp2 寄生ダイオード
Ton パルス幅
T パルス周期
WA ボンディングワイヤ
WB1 ボンディングワイヤ
WB2 ボンディングワイヤ
BDH 裏面電極
PWL1 p型ウエル
Claims (10)
- (a)厚さ方向に沿って互いに反対側に位置する第1主面および第2主面を有する配線基板を準備する工程、
(b)前記配線基板の第1主面上にパワートランジスタ用の半導体チップおよび制御回路用の半導体チップを搭載する工程を有し、
前記(a)工程においては、
前記配線基板の第2主面に配置される外部端子のうち、前記制御回路用の半導体チップに電気的に接続される外部端子の配置を固定し、前記パワートランジスタ用の半導体チップに電気的に接続される外部端子の配置を変える工程を有することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記パワートランジスタ用の半導体チップを、前記制御回路用の半導体チップの長手方向に対して交差するように配置し、
前記パワートランジスタ用の半導体チップの辺の長さを変える工程を有することを特徴とする半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記パワートランジスタ用の半導体チップの辺のうち、前記制御回路用の半導体チップの長手方向に対して交差する方向に沿う辺の長さを変える工程を有することを特徴とする半導体装置の製造方法。 - 厚さ方向に沿って互いに反対側に位置する第1主面および第2主面を有する配線基板と、
前記配線基板の第1主面上に搭載されたパワートランジスタ用の半導体チップおよび制御回路用の半導体チップと、
前記パワートランジスタ用の半導体チップおよび前記制御回路用の半導体チップを封止する封止体とを備え、
前記封止体の第1主面および第2主面は四角形状に形成されており、
前記封止体の第2主面には、その四辺に沿って、
前記制御回路用の半導体チップに電気的に接続された複数の第1外部端子と、
前記パワートランジスタ用の半導体チップに電気的に接続された複数の第2外部端子とが配置されており、
前記パワートランジスタ用の半導体チップと、前記制御回路用の半導体チップとは、その各々の長手方向が互いに交差するように配置されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記制御回路用の半導体チップは、パルス幅変調信号を生成する回路を有することを特徴とする半導体装置。 - 請求項4記載の半導体装置において、QFN構成であることを特徴とする半導体装置。
- 請求項4記載の半導体装置において、QFP構成であることを特徴とする半導体装置。
- 厚さ方向に沿って互いに反対側に位置する第1主面および第2主面を有する配線基板と、
前記配線基板の第1主面上に搭載されたパワートランジスタ用の複数の半導体チップと、
前記配線基板の第1主面上に搭載された制御回路用の半導体チップとを有し、
前記配線基板は、前記制御回路用の半導体チップに電気的に接続された複数の外部端子と、前記パワートランジスタ用の複数の半導体チップに電気的に接続された複数の外部端子とを備え、
前記パワートランジスタ用の複数の半導体チップの各々のパワートランジスタは電気的に並列に接続されていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記パワートランジスタ用の複数の半導体チップは、DC/DCコンバータのロウサイド用のパワートランジスタを有しており、
前記配線基板の第1主面には、前記ロウサイド用のパワートランジスタを有する前記複数の半導体チップの他に、前記DC/DCコンバータのハイサイド用のパワートランジスタを有する半導体チップが搭載されていることを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記ロウサイド用のパワートランジスタを有する前記複数の半導体チップの長辺の長さの和は、前記ハイサイド用のパワートランジスタを有する半導体チップの長辺の長さよりも長いことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012135933A JP5412559B2 (ja) | 2012-06-15 | 2012-06-15 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012135933A JP5412559B2 (ja) | 2012-06-15 | 2012-06-15 | 半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006043293A Division JP5291864B2 (ja) | 2006-02-21 | 2006-02-21 | Dc/dcコンバータ用半導体装置の製造方法およびdc/dcコンバータ用半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012216858A true JP2012216858A (ja) | 2012-11-08 |
JP5412559B2 JP5412559B2 (ja) | 2014-02-12 |
Family
ID=47269270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012135933A Expired - Fee Related JP5412559B2 (ja) | 2012-06-15 | 2012-06-15 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5412559B2 (ja) |
Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05299576A (ja) * | 1992-04-17 | 1993-11-12 | Mitsubishi Electric Corp | マルチチップ型半導体装置及びその製造方法 |
JPH1131775A (ja) * | 1997-07-10 | 1999-02-02 | Shindengen Electric Mfg Co Ltd | 樹脂封止型半導体装置の製造方法およびこれに使用するリ ードフレーム |
JP2001032009A (ja) * | 1999-07-19 | 2001-02-06 | Nippon Steel Corp | クロムを含有する溶鋼の精錬方法 |
JP2002083927A (ja) * | 2000-09-07 | 2002-03-22 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2002100775A (ja) * | 2000-09-21 | 2002-04-05 | Denso Corp | 電圧駆動型パワー素子 |
JP2002100776A (ja) * | 2000-09-21 | 2002-04-05 | Denso Corp | 電圧駆動型パワー素子 |
JP2002203957A (ja) * | 2000-12-28 | 2002-07-19 | Rohm Co Ltd | トランジスタ |
JP2002203941A (ja) * | 2001-01-04 | 2002-07-19 | Nissan Motor Co Ltd | 半導体実装構造 |
JP2004055755A (ja) * | 2002-07-18 | 2004-02-19 | Sanyo Electric Co Ltd | 混成集積回路装置 |
JP2004055756A (ja) * | 2002-07-18 | 2004-02-19 | Sanyo Electric Co Ltd | 混成集積回路装置 |
WO2004064110A2 (en) * | 2003-01-03 | 2004-07-29 | Gem Services, Inc. | Space-efficient package for laterally conducting device |
JP2004266096A (ja) * | 2003-02-28 | 2004-09-24 | Renesas Technology Corp | 半導体装置及びその製造方法、並びに電子装置 |
JP2004311901A (ja) * | 2003-04-10 | 2004-11-04 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2004342735A (ja) * | 2003-05-14 | 2004-12-02 | Renesas Technology Corp | 半導体装置および電源システム |
JP2005093762A (ja) * | 2003-09-18 | 2005-04-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2005223008A (ja) * | 2004-02-03 | 2005-08-18 | Toshiba Corp | 半導体モジュール |
JP2005294464A (ja) * | 2004-03-31 | 2005-10-20 | Renesas Technology Corp | 半導体装置 |
JP2006208152A (ja) * | 2005-01-27 | 2006-08-10 | Hitachi Ulsi Systems Co Ltd | 電池監視装置 |
JP2006310663A (ja) * | 2005-04-28 | 2006-11-09 | Toshiba Corp | 演算処理装置 |
WO2007095468A2 (en) * | 2006-02-13 | 2007-08-23 | Fairchild Semiconductor Corporation | Multi-chip module for battery power control |
-
2012
- 2012-06-15 JP JP2012135933A patent/JP5412559B2/ja not_active Expired - Fee Related
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05299576A (ja) * | 1992-04-17 | 1993-11-12 | Mitsubishi Electric Corp | マルチチップ型半導体装置及びその製造方法 |
JPH1131775A (ja) * | 1997-07-10 | 1999-02-02 | Shindengen Electric Mfg Co Ltd | 樹脂封止型半導体装置の製造方法およびこれに使用するリ ードフレーム |
JP2001032009A (ja) * | 1999-07-19 | 2001-02-06 | Nippon Steel Corp | クロムを含有する溶鋼の精錬方法 |
JP2002083927A (ja) * | 2000-09-07 | 2002-03-22 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2002100775A (ja) * | 2000-09-21 | 2002-04-05 | Denso Corp | 電圧駆動型パワー素子 |
JP2002100776A (ja) * | 2000-09-21 | 2002-04-05 | Denso Corp | 電圧駆動型パワー素子 |
JP2002203957A (ja) * | 2000-12-28 | 2002-07-19 | Rohm Co Ltd | トランジスタ |
JP2002203941A (ja) * | 2001-01-04 | 2002-07-19 | Nissan Motor Co Ltd | 半導体実装構造 |
JP2004055755A (ja) * | 2002-07-18 | 2004-02-19 | Sanyo Electric Co Ltd | 混成集積回路装置 |
JP2004055756A (ja) * | 2002-07-18 | 2004-02-19 | Sanyo Electric Co Ltd | 混成集積回路装置 |
WO2004064110A2 (en) * | 2003-01-03 | 2004-07-29 | Gem Services, Inc. | Space-efficient package for laterally conducting device |
JP2004266096A (ja) * | 2003-02-28 | 2004-09-24 | Renesas Technology Corp | 半導体装置及びその製造方法、並びに電子装置 |
JP2004311901A (ja) * | 2003-04-10 | 2004-11-04 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2004342735A (ja) * | 2003-05-14 | 2004-12-02 | Renesas Technology Corp | 半導体装置および電源システム |
JP2005093762A (ja) * | 2003-09-18 | 2005-04-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2005223008A (ja) * | 2004-02-03 | 2005-08-18 | Toshiba Corp | 半導体モジュール |
JP2005294464A (ja) * | 2004-03-31 | 2005-10-20 | Renesas Technology Corp | 半導体装置 |
JP2006208152A (ja) * | 2005-01-27 | 2006-08-10 | Hitachi Ulsi Systems Co Ltd | 電池監視装置 |
JP2006310663A (ja) * | 2005-04-28 | 2006-11-09 | Toshiba Corp | 演算処理装置 |
WO2007095468A2 (en) * | 2006-02-13 | 2007-08-23 | Fairchild Semiconductor Corporation | Multi-chip module for battery power control |
Also Published As
Publication number | Publication date |
---|---|
JP5412559B2 (ja) | 2014-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5291864B2 (ja) | Dc/dcコンバータ用半導体装置の製造方法およびdc/dcコンバータ用半導体装置 | |
KR101204139B1 (ko) | Dc/dc 컨버터용 반도체장치 | |
US8044520B2 (en) | Semiconductor device | |
JP4426955B2 (ja) | 半導体装置 | |
US9520341B2 (en) | Semiconductor package with conductive clips | |
KR101086751B1 (ko) | 반도체 장치 및 전원 시스템 | |
KR101131662B1 (ko) | 반도체장치 | |
JP2006216940A (ja) | 半導体装置 | |
JP2003124436A (ja) | 半導体装置 | |
JP4769784B2 (ja) | 半導体装置 | |
US11990455B2 (en) | Semiconductor device | |
JP5315378B2 (ja) | Dc/dcコンバータ用半導体装置 | |
JP4250191B2 (ja) | Dc/dcコンバータ用半導体装置 | |
JP4344776B2 (ja) | 半導体装置 | |
JP2013141035A (ja) | 半導体装置 | |
EP2645413B1 (en) | Integrated dual power converter package having internal driver IC | |
JP5292388B2 (ja) | 半導体装置 | |
US11145629B2 (en) | Semiconductor device and power conversion device | |
JP4705945B2 (ja) | 半導体装置 | |
JP5412559B2 (ja) | 半導体装置の製造方法 | |
JP2006253734A (ja) | 半導体装置 | |
JP5648095B2 (ja) | 半導体装置 | |
JP2011228719A (ja) | Dc/dcコンバータ用半導体装置 | |
JP2008130719A (ja) | 半導体装置及びdc−dcコンバータ | |
TW201320262A (zh) | 一種倒裝晶片的半導體器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130524 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130730 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130926 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131015 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131111 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5412559 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |