TWI791200B - 薄型系統級封裝 - Google Patents

薄型系統級封裝 Download PDF

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Publication number
TWI791200B
TWI791200B TW110108822A TW110108822A TWI791200B TW I791200 B TWI791200 B TW I791200B TW 110108822 A TW110108822 A TW 110108822A TW 110108822 A TW110108822 A TW 110108822A TW I791200 B TWI791200 B TW I791200B
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Taiwan
Prior art keywords
electrically connected
package
copper
passive element
pin
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TW110108822A
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English (en)
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TW202236539A (zh
Inventor
林俊榮
古瑞庭
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華東科技股份有限公司
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Application filed by 華東科技股份有限公司 filed Critical 華東科技股份有限公司
Priority to TW110108822A priority Critical patent/TWI791200B/zh
Priority to CN202110661247.8A priority patent/CN115084119A/zh
Priority to KR1020210079790A priority patent/KR102559874B1/ko
Priority to US17/353,861 priority patent/US11869876B2/en
Priority to JP2021103912A priority patent/JP7141498B1/ja
Publication of TW202236539A publication Critical patent/TW202236539A/zh
Application granted granted Critical
Publication of TWI791200B publication Critical patent/TWI791200B/zh

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Abstract

本發明陳述一種薄型系統級封裝，其主要特徵為封裝結構中不具備印刷電路板者，其具有一銅支架之一頂面上之複數晶粒，該些晶粒與該銅支架之複數資訊連結腳電性連接，另該該頂面上之一被動元件與該些晶粒電性連接，而該些晶粒電性連接於該銅支架之該接地腳，該些晶粒及該被動元件透過一絕緣膠固定於該銅支架之該頂面上，最後由一模製化合物，其囊封該銅支架之該頂面上之該些晶粒及該被動元件。

Description

薄型系統級封裝
本發明係關於一種系統級封裝，特別在於封裝結構中不具備印刷電路板，並以絕緣膠固定元件，再以金屬線或導電膠電性導通。
目前在積體電路之封裝技術中，多會將一個系統或子系統的全部或大部份電子功能組態在整合型基板內，而晶片以2D、3D的方式接合到整合型基板的封裝手法，以上製程多以系統級封裝(System in Package,SiP)稱呼。
系統級封裝(System in Package,SiP)不僅可以組合多個晶片，還可以作為一個專門的處理器、DRAM、快閃記憶體與被動元件結合電阻器和電容器、連接器、天線等，全部設置在同一基板上。這意味著，一個完整的功能單位可以建在一個多晶片封裝，因此，需要添加少量的外部元件，使其工作。
系統級封裝(System in Package,SiP)較單晶片系統(System on a Chip,SoC)降低系統成本，除了顯著減小封裝體積、重量，還可以降低功耗；然而，在系統級封裝(System in Package,SiP)中，一個封裝體裡面可能有幾十顆裸晶片，當中一個裸晶片壞了就會浪費整個封裝體裡面其他的裸晶片，而且廠商需要圍繞系統級封裝(System in Package,SiP)需求布置產線，或對原有的機台配比進行調整，並保證機台的利用效率。
關於系統級封裝(System in Package,SiP)之文獻，多個專利如下：
US 15/939,097描述系統級封裝結構及組裝的方法。在一實施例中，一系統級封裝包括相對的電路板，各自包括安裝組件與相對的該電路板的安裝組件重疊。相對的該等電路板之間的一間隙可以造模材料填充，該造模材料額外封裝重疊的該等安裝組件。在一些實施例中，使用可提供機械或電連接的一或多個插置器將相對的該等電路板彼此堆疊。
US 61/929,130揭露系統級封裝模組包含一非記憶體晶片、一包裹式記憶體及一密封封裝材料。該非記憶體晶片具有複數個襯墊。該包裹式記憶體包含一第一記憶體晶粒和一第二記憶體晶粒，其中該第一記憶體晶粒和該第二記憶體晶粒並排形成在一基板之上，該第一記憶體晶粒包含一第一組襯墊和該第二記憶體晶粒包含一第二組襯墊。該密封封裝材料封裝該非記憶體晶片和該包裹式記憶體，其中該非記憶體晶片通過該複數個襯墊、該第一組襯墊和該第二組襯墊電耦接該包裹式記憶體。該第一組襯墊通過旋轉一預定角度或鏡像映射對應該第二組襯墊。
TW 201737452提出了一種系統級封裝，包括一重佈層(RDL)結構、一第一半導體晶粒，安裝在該重佈層結構的第一側上，該第一半導體晶粒具有與該重佈層結構直接接觸的主動面、複數個導電指部，位於該第一半導體晶粒周圍的重佈層結構的第一側上、一第二半導體晶粒，直接堆疊在該第一半導體晶粒上，該第二半導體晶粒透過複數個接合引線電連接至該複數個導電指部、以及一模蓋，封住該第一半導體晶粒、該導電指部、該第二半導體晶粒和該重佈層結構的第一側。此外，此發明 還提供了一種用於製造系統級封裝的方法，可以提高佈線靈活性。
但是，在越來嚴苛的市場競爭中，面對需要再次降低製程成本，並且進一步提供縮小封裝體積及重量，使封裝業者面臨巨大壓力，如何達成並保持可靠度將具有極高的難度。
有鑑於以上問題，本發明提供一種系統級封裝，主要利用封裝結構中不具備印刷電路板，以達成大幅減少整體成本之效果。
因此，本發明之主要目的係在提供一種系統級封裝，將印刷電路板移除，使封裝厚度變薄。
本發明再一目的係在提供一種系統級封裝，因封裝後變薄，在產品中更可增加更多層，而增加各類功能。
本發明再一目的係在提供一種系統級封裝，使用絕緣膠固定元件，可以降低設置成本及整體厚度。
本發明再一目的係在提供一種系統級封裝，利用導電膠導通元件，可以降低設置成本及提高電性效率。
本發明再一目的係在提供一種系統級封裝，透過金屬線直連，可提高電性性能，並減少廢熱產出。
為達成上述目地，本發明所使用的主要技術手段是採用以下技術方案來實現的。本發明為一種薄型系統級封裝，其為封裝結構中不具備印刷電路板者，其包含：一銅支架具有複數資訊連結腳及至少一接地腳；該銅支架之一頂面上之複數晶粒；該些晶粒與該銅支架之該資訊連結腳電性連接；該銅支架之該頂面上之至少一被動元件；該被動元件與該些晶粒 電性連接；該些晶粒及該被動元件透過一絕緣膠固定於該銅支架之該頂面上；該些晶粒電性連接於該銅支架之該接地腳；一模製化合物，其囊封該銅支架之該頂面上之該些晶粒及該被動元件。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
前述的封裝，其中該些晶粒，透過複數第一金屬線與該銅支架之該資訊連結腳電性連接。
前述的封裝，其中該被動元件，透過複數第二金屬線與該晶粒電性連接。
前述的封裝，其中該些晶粒，透過一導電膠與該銅支架之該資訊連結腳電性連接。
前述的封裝，透過一導電膠與該銅支架之該接地腳電性連接。
前述的封裝，透過複數第三金屬線與該銅支架之該接地腳電性連接。
前述的封裝，其中該被動元件，透過一導電膠與該銅支架之該資訊連結腳電性連接。
前述的封裝，其中該被動元件，透過一導電膠與該銅支架之該接地腳電性連接。
前述的封裝，其中該被動元件，透過至少一第四金屬線與該銅支架之該資訊連結腳電性連接。
前述的封裝，其中該被動元件，透過至少一第五金屬線與該 銅支架之該接地腳電性連接。
相較於習知技術，本發明具有功效在於：(1)利用金屬線打線取代印刷電路板，以達成大幅減少整體成本之效果；(2)使用絕緣膠固定元件，可以降低設置成本及整體厚度；(3)利用導電膠導通元件，可以降低設置成本及提高電性效率。
10:銅支架
11:資訊連結腳
12:接地腳
13:頂面
20:晶粒
20`:晶粒
30:第一金屬線
31:第二金屬線
32:第三金屬線
33:第四金屬線
34:第五金屬線
40:被動元件
50:模製化合物
51:導電膠
52:絕緣膠
〔圖1〕係本發明第一實施型態之封裝示意圖。
〔圖2a〕係本發明第二實施型態之封裝示意圖。
〔圖2b〕係本發明第三實施型態之封裝示意圖。
〔圖2c〕係本發明第四實施型態之封裝示意圖。
〔圖2d〕係本發明第五實施型態之封裝示意圖。
〔圖2e〕係本發明第六實施型態之封裝示意圖。
〔圖2f〕係本發明第七實施型態之封裝示意圖。
〔圖3〕係本發明第一實施型態之電性連結示意圖。
〔圖4a〕係本發明第二實施型態之電性連結示意圖。
〔圖4b〕係本發明第三實施型態之電性連結示意圖。
〔圖4c〕係本發明第四實施型態之電性連結示意圖。
〔圖4d〕係本發明第五實施型態之電性連結示意圖。
〔圖4e〕係本發明第六實施型態之電性連結示意圖。
〔圖4f〕係本發明第七實施型態之電性連結示意圖。
為了讓本發明之目的、特徵與功效更明顯易懂，以下特別列舉本發明之較佳實施型態：
如圖1及圖3所示，為本發明一種系統級封裝之第一實施型態；請先參考第1圖所示，一種薄型系統級封裝，其為封裝結構中不具備印刷電路板者，其包含：一銅支架(10)具有複數資訊連結腳(11)及至少一接地腳(12)；該銅支架(10)之一頂面(13)上之複數晶粒(20,20`)；該些晶粒(20,20`)與該銅支架(10)之該資訊連結腳(11)電性連接；該銅支架(10)之該頂面(13)上之至少一被動元件(40)；該被動元件(40)與該些晶粒(20,20`)電性連接；該些晶粒(20,20`)及該被動元件(40)透過一絕緣膠(52)固定於該銅支架(10)之該頂面(13)上；該些晶粒(20,20`)電性連接於該銅支架(10)之該接地腳(12)；一模製化合物(50)，其囊封該銅支架(10)之該頂面(13)上之該些晶粒(20,20`)及該被動元件(40)。
具體而言，其中晶粒(20)透過第一金屬線(30)與該銅支架(10)之該資訊連結腳(11)電性連接，而被動元件(40)透過第二金屬線(31)與該晶粒(20)電性連接，且該晶粒(20)透過第三金屬線(32)與該銅支架(10)之該接地腳(12)電性連接。
實務來說，晶粒(20)可部分透過複數第一金屬線(30)與該資訊連結腳(11)電性連接，另被動元件(40)可部分透過第二金屬線(31)與該晶粒(20)電性連接，且晶粒(20)可部分透過第三金屬線(32)與該接地腳(12)電性連接。
詳細來說，該銅支架(10)係指導線架，其是晶粒(Die) 封裝內部的金屬結構，用於將信號從晶粒(Die)傳遞到外部，其由不同的部分組成，透過結構連接將所有這些零件固定在框架結構內，這使得整個引線框架易於自動化處理；再，該資訊連結腳(11)功效為提供該晶粒(20)與外界的電性連接；該接地腳(12)係為在電路設計時之地線，地線則被廣泛作為電位的參考點，為整個電路提供一個基準電位，以地線上電壓為0V，以統一整個電路電位；絕緣膠(52)係具備固定物件及不導電特性之膠狀物，在質變後呈固化狀，並維持固定物件及不導電特性。
接著，該些晶粒(20,20`)是指晶粒(Die)是以半導體材料製作而成未經封裝的一小塊積體電路本體，主要來源為由晶圓切割分離；其中，第一金屬線(30)、第二金屬線(31)與第三金屬線(32)實為打線接合(Wire bonding)的金屬線材，是利用線徑15-50微米的金屬線材將晶粒(Chip)及導線架(Lead Frame)連接起來的技術，使微小的晶片得以與外面的電路做溝通，而不需要增加太多的面積；被動元件(40)係為被動元件(Passive components)，又稱無源器件，可以指消耗但不產生能量的電子元件，或者指無法產生增益的電子元件；該模製化合物(50)為半導體封裝材料，一般使用高分子樹脂作為電子元件及晶粒(Chip)的封裝材料。
請再參閱圖3所示，可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間透過第一金屬線(30)電性連結，使外部訊號與電源得以與晶粒(20)電性導通，並將訊號傳遞出去；再，晶粒(20)與接地腳(12)間透過第三金屬線(32)電性連結，接地腳(12)作為電位的參考點，為 整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器(quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；實務上，可再搭配記憶體元件等。
請再參照圖2a及圖4a所示，為本發明一種系統級封裝之第二實施型態；第二實施型態與第一實施型態的主要差異在於本實施型態變更晶粒(20)與接地腳(12)間改由導電膠(51)電性連結；請先參考圖2a所示，該些晶粒(20,20`)透過一導電膠(51)與該銅支架(10)之該資訊連結腳(11)電性連接。
實際而言，導電膠(51)係具備固定物件及導電特性之膠狀物，在質變後呈固化狀，並維持固定物件及導電特性。
實務來說，晶粒(20)與接地腳(12)間可部分由導電膠(51)電性連結，並可部分同第一實施型態之晶粒(20)透過第三金屬線(32)與該接地腳(12)電性連接；實際製作過程可先設置絕緣膠(52)於銅支架(10)之該頂面(13)上，再設置導電膠(51)於絕緣膠(52)固化後表面。
請再參閱圖4a所示，可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間透過第一金屬線(30)電性連結，使外部訊號與電源得以與晶粒(20)電性導通，並將訊號傳遞出去；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器 (quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；再，被動元件(40)與接地腳(12)間透過一導電膠(51)電性連結，接地腳(12)作為電位的參考點，為整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；實務上，可再搭配記憶體元件等。
請再參照圖2b及圖4b所示，為本發明一種系統級封裝之第三實施型態；第三實施型態與第一實施型態的主要差異在於本實施型態增加導電膠(51)電性連結；請先參考圖2b所示，晶粒(20)透過一導電膠(51)與該銅支架(10)之該資訊連結腳(11)電性連接。
請再參閱圖4b所示，可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間可部分透過第一金屬線(30)電性連結，且晶粒(20)部分透過導電膠(51)與銅支架(10)之該資訊連結腳(11)電性連接，使外部訊號與電源得以與晶粒(20)電性導通，並將訊號傳遞出去；再，晶粒(20)與接地腳(12)間透過第三金屬線(32)電性連結，接地腳(12)作為電位的參考點，為整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器(quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；實務上，可再搭配記憶體元件等。
請再參照圖2c及圖4c所示，為本發明一種系統級封裝之第四實施型態；第四實施型態與第一實施型態的主要差異在於本實施型態增加 導電膠(51)電性連結；請先參考圖2c所示，該被動元件(40)透過一導電膠(51)與該銅支架(10)之該資訊連結腳(11)電性連接。
請再參閱圖4c所示可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間透過第一金屬線(30)電性連結，使外部訊號與電源得以與晶粒(20)電性導通，並將訊號傳遞出去；再，晶粒(20)與接地腳(12)間透過第三金屬線(32)電性連結，接地腳(12)作為電位的參考點，為整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；該被動元件(40)與該資訊連結腳(11)可部分透過導電膠(51)電性連接；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器(quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；實務上，可再搭配記憶體元件等。
請再參照圖2d及圖4d所示，為本發明一種系統級封裝之第五實施型態；第五實施型態與第一實施型態的主要差異在於本實施型態增加導電膠(51)；請先參考圖2d所示，該被動元件(40)透過一導電膠(51)與該銅支架(10)之該接地腳(12)電性連接。
具體而言，該被動元件(40)部分係為接地電阻器、接地電容器等，因此需增加該被動元件(40)與接地腳(12)的電性連結。
請再參閱圖4d所示可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間透過第一金屬線(30)電性連結，使外部訊號與電源得以與晶 粒(20)電性導通，並將訊號傳遞出去；再，晶粒(20)與接地腳(12)間透過第三金屬線(32)電性連結，接地腳(12)作為電位的參考點，為整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；該被動元件(40)與該接地腳(12)透過導電膠(51)電性連接；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器(quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；實務上，可再搭配記憶體元件等。
請再參照圖2e及圖4e所示，為本發明一種系統級封裝之第六實施型態；第六實施型態與第三實施型態的主要差異在於本實施型態增加第四金屬線(33)電性連結；請先參考圖2e所示，該被動元件(40)透過至少一第四金屬線(33)與該銅支架(10)之該資訊連結腳(11)電性連接。
具體而言，第四金屬線(33)實為打線接合(Wire bonding)的金屬線材，是利用線徑15-50微米的金屬線材將晶粒(Chip)及導線架(Lead Frame)連接起來的技術，使微小的晶片得以與外面的電路做溝通，而不需要增加太多的面積。
請再參閱圖4e所示，可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間透過第一金屬線(30)電性連結，且晶粒(20)透過導電膠(51)與銅支架(10)之該資訊連結腳(11)電性連接，使外部訊號與電源得以與晶粒(20)電性導通，並將訊號傳遞出去；該被動元件(40)與該資訊 連結腳(11)可部分透過第四金屬線(33)電性連接；再，晶粒(20)與接地腳(12)間透過第三金屬線(32)電性連結，接地腳(12)作為電位的參考點，為整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器(quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；實務上，可再搭配記憶體元件等。
請再參照圖2f及圖4f所示，為本發明一種系統級封裝之第七實施型態；第七實施型態與第三實施型態的主要差異在於本實施型態增加第五金屬線(34)電性連結；請先參考圖2f所示，該被動元件(40)，透過至少一第五金屬線(34)與該銅支架(10)之該接地腳(12)電性連接。
具體而言，第五金屬線(34)實為打線接合(Wire bonding)的金屬線材，是利用線徑15-50微米的金屬線材將晶粒(Chip)及導線架(Lead Frame)連接起來的技術，使微小的晶片得以與外面的電路做溝通，而不需要增加太多的面積。
請再參閱圖4f所示，可見晶粒(20)分別對資訊連結腳(11)、接地腳(12)及被動元件(40)電性連結；其中，晶粒(20)與資訊連結腳(11)間透過第一金屬線(30)電性連結，且晶粒(20)透過導電膠(51)與銅支架(10)之該資訊連結腳(11)電性連接，使外部訊號與電源得以與晶粒(20)電性導通，並將訊號傳遞出去；該被動元件(40)與該接地腳(12)可部分透過第五金屬線(34)電性連接；再，晶粒(20)與接地腳(12)間透過第三金屬線(32)電性連結，接地腳(12)作為電位的參 考點，為整個電路提供一個基準電位，以接地腳(12)上電壓為0V，以統一整個電路電位；再，晶粒(20)與被動元件(40)間透過第二金屬線(31)電性連結，在此被動元件(40)可為石英振盪器(quartz crystal unit或，Xtal)、電阻器、電容器、電感器等，輔助晶粒(20)運行；實務上，可再搭配記憶體元件等。
因此本發明之功效有別一般半導體封裝結構，此於半導體封裝當中實屬首創，符合發明專利要件，爰依法俱文提出申請。
惟，需再次重申，以上所述者僅為本發明之較佳實施型態，舉凡應用本發明說明書、申請專利範圍或圖式所為之等效變化，仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10:銅支架
11:資訊連結腳
12:接地腳
13:頂面
20:晶粒
20`:晶粒
30:第一金屬線
31:第二金屬線
32:第三金屬線
40:被動元件
50:模製化合物
52:絕緣膠

Claims (9)

  1. 一種薄型系統級封裝，其為封裝結構中不具備印刷電路板者，其包含：一銅支架具有複數資訊連結腳及至少一接地腳；該銅支架之一頂面上之複數晶粒；該些晶粒與該銅支架之該資訊連結腳電性連接；該銅支架之該頂面上之至少一被動元件；該被動元件與該些晶粒電性連接，其中該被動元件透過一導電膠與該銅支架之該接地腳電性連接；該些晶粒及該被動元件透過一絕緣膠固定於該銅支架之該頂面上；該些晶粒電性連接於該銅支架之該接地腳；一模製化合物，其囊封該銅支架之該頂面上之該些晶粒及該被動元件。
  2. 如請求項1之封裝，其中該些晶粒，透過複數第一金屬線與該銅支架之該資訊連結腳電性連接。
  3. 如請求項1之封裝，其中該被動元件，透過複數第二金屬線與該晶粒電性連接。
  4. 如請求項1之封裝，其中該些晶粒，透過另一導電膠與該銅支架之該資訊連結腳電性連接。
  5. 如請求項1之封裝，其中該些晶粒，透過另一導電膠與該銅支架之該接地腳電性連接。
  6. 如請求項1之封裝，其中該些晶粒，透過複數第三金屬線與該銅支架之該接地腳電性連接。
  7. 如請求項1之封裝，其中該被動元件，透過另一導電膠與該銅支架之該資訊連結腳電性連接。
  8. 如請求項1之封裝，其中該被動元件，透過至少一第四金屬線與該銅支架之該資訊連結腳電性連接。
  9. 如請求項1之封裝，其中該被動元件，透過至少一第五金屬線與該銅支架之該接地腳電性連接。
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