CN115084119A - 薄型系统级封装 - Google Patents

薄型系统级封装 Download PDF

Info

Publication number
CN115084119A
CN115084119A CN202110661247.8A CN202110661247A CN115084119A CN 115084119 A CN115084119 A CN 115084119A CN 202110661247 A CN202110661247 A CN 202110661247A CN 115084119 A CN115084119 A CN 115084119A
Authority
CN
China
Prior art keywords
electrically connected
package
copper
crystal grain
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110661247.8A
Other languages
English (en)
Inventor
林俊荣
古瑞庭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Walton Advanced Engineering Inc
Original Assignee
Walton Advanced Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walton Advanced Engineering Inc filed Critical Walton Advanced Engineering Inc
Publication of CN115084119A publication Critical patent/CN115084119A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29393—Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4502—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)
  • Glass Compositions (AREA)
  • Structure Of Printed Boards (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

本发明涉及一种薄型系统级封装，其主要特征在于封装结构中无印刷电路板，其包含：一铜支架，所述铜支架具有多信息连接脚及至少一接地脚；所述铜支架的一顶面上设有多个晶粒；各所述晶粒与所述铜支架的所述信息连接脚电性连接；所述铜支架的所述顶面上设有至少一被动元件；所述被动元件与各所述晶粒电性连接；各所述晶粒及所述被动元件通过一绝缘胶固定于所述铜支架的所述顶面上；各所述晶粒电性连接于所述铜支架的所述接地脚；一模制化合物，其囊封所述铜支架的所述顶面上的各所述晶粒及所述被动元件。

Description

薄型系统级封装
技术领域
本发明涉及一种系统级封装，特别是指封装结构中不具备印刷电路板，并以绝缘胶固定元件，再以金属线或导电胶电性导通。
背景技术
目前在集成电路的封装技术中，多会将一个系统或子系统的全部或大部份电子功能组态在整合型基板内，而芯片以2D、3D的方式接合到整合型基板的封装手法，以上制程多以系统级封装(System in Package,SiP)称呼。
系统级封装(System in Package,SiP)不仅可以组合多个芯片，还可以作为一个专门的处理器、DRAM、闪存与被动元件结合电阻器和电容器、连接器、天线等，全部设置在同一基板上。这意味着，一个完整的功能单位可以建在一个多芯片封装，因此，需要添加少量的外部元件，使其工作。
系统级封装(System in Package,SiP)较单芯片系统(System on a Chip,SoC)降低系统成本，除了显著减小封装体积、重量，还可以降低功耗；然而，在系统级封装(Systemin Package,SiP)中，一个封装体里面可能有几十颗裸芯片，当中一个裸芯片坏了就会浪费整个封装体里面其他的裸芯片，而且厂商需要围绕系统级封装(System in Package,SiP)需求布置产线，或对原有的机台配比进行调整，并保证机台的利用效率。
关于系统级封装(System in Package,SiP)的文献，多个专利如下：
美国专利US 15/939,097描述系统级封装结构及组装的方法。在一实施例中，一系统级封装包括相对的电路板，各自包括安装元件与相对的该电路板的安装元件重叠。相对的各电路板之间的一间隙可以造模材料填充，该造模材料额外封装重叠的各安装元件。在一些实施例中，使用可提供机械或电连接的一或多个插置器将相对的各电路板彼此堆叠。
美国专利US 61/929,130揭示系统级封装模块包含一非内存芯片、一包裹式内存及一密封封装材料。非内存芯片具有多个衬垫。包裹式内存包含一第一内存晶粒和一第二内存晶粒，其中第一内存晶粒和第二内存晶粒并排形成在一基板之上，第一内存晶粒包含一第一组衬垫和第二内存晶粒包含一第二组衬垫。密封封装材料封装非内存芯片和包裹式内存，其中非内存芯片通过多个衬垫、第一组衬垫和第二组衬垫电耦接包裹式内存。第一组衬垫通过旋转一预定角度或镜像映射对应第二组衬垫。
中国台湾专利TW 201737452提出了一种系统级封装，包括一重布层(RDL)结构、一第一半导体晶粒，安装在重布层结构的第一侧上，第一半导体晶粒具有与重布层结构直接接触的主动面、多个导电指部，位于第一半导体晶粒周围的重布层结构的第一侧上、一第二半导体晶粒，直接堆叠在第一半导体晶粒上，第二半导体晶粒通过多个接合引线电连接至多个导电指部、以及一模盖，封住第一半导体晶粒、导电指部、第二半导体晶粒和重布层结构的第一侧。此外，此发明还提供了一种用于制造系统级封装的方法，可以提高布线灵活性。
但是，在越来严苛的市场竞争中，面对需要再次降低制程成本，并且进一步提供缩小封装体积及重量，使封装业者面临巨大压力，如何达成并保持可靠度将具有极高的难度。
发明内容
针对上述问题，本发明的主要目的在于提供一种系统级封装，主要利用封装结构中不具备印刷电路板，以达到大幅减少整体成本的效果。
因此，本发明的主要目的在于提供一种系统级封装，将印刷电路板移除，使封装厚度变薄。
本发明的再一目的在于提供一种系统级封装，因封装后变薄，在产品中更可增加更多层，而增加各类功能。
本发明的再一目的在于提供一种系统级封装，使用绝缘胶固定元件，可以降低设置成本及整体厚度。
本发明的再一目的在于提供一种系统级封装，利用导电胶导通元件，可以降低设置成本及提高电性效率。
本发明的再一目的在于提供一种系统级封装，通过金属线直连，可提高电性性能，并减少废热产出。
为达到上述目的，本发明所提供的一种薄型系统级封装，其特征在于：封装结构中无印刷电路板，其包含：一铜支架，所述铜支架具有多信息连接脚及至少一接地脚；所述铜支架的一顶面上设有多个晶粒；各所述晶粒与所述铜支架的所述信息连接脚电性连接；所述铜支架的所述顶面上设有至少一被动元件；所述被动元件与各所述晶粒电性连接；各所述晶粒及所述被动元件通过一绝缘胶固定于所述铜支架的所述顶面上；各所述晶粒电性连接于所述铜支架的所述接地脚；一模制化合物，其囊封所述铜支架的所述顶面上的各所述晶粒及所述被动元件。
上述本发明的技术方案中，各所述晶粒，通过多个第一金属线与所述铜支架的所述信息连接脚电性连接。
所述被动元件，通过多个第二金属线与所述晶粒电性连接。
各所述晶粒，通过一导电胶与所述铜支架的所述信息连接脚电性连接。
各所述晶粒，通过一导电胶与所述铜支架的所述接地脚电性连接。
各所述晶粒，通过多个第三金属线与所述铜支架的所述接地脚电性连接。
所述被动元件，通过一导电胶与所述铜支架的所述信息连接脚电性连接。
所述被动元件，通过一导电胶与所述铜支架的所述接地脚电性连接。
所述被动元件，通过至少一第四金属线与所述铜支架的所述信息连接脚电性连接。
所述被动元件，通过至少一第五金属线与所述铜支架的所述接地脚电性连接。
采用上述技术方案，相较于习知技术，本发明具有功效在于：(1)利用金属线打线取代印刷电路板，以达到大幅减少整体成本的效果；(2)使用绝缘胶固定元件，可以降低设置成本及整体厚度；(3)利用导电胶导通元件，可以降低设置成本及提高电性效率。
附图说明
图1是本发明第一实施型态的封装示意图；
图2a是本发明第二实施型态的封装示意图；
图2b是本发明第三实施型态的封装示意图；
图2c是本发明第四实施型态的封装示意图；
图2d是本发明第五实施型态的封装示意图；
图2e是本发明第六实施型态的封装示意图；
图2f是本发明第七实施型态的封装示意图；
图3是本发明第一实施型态的电性连接示意图；
图4a是本发明第二实施型态的电性连接示意图；
图4b是本发明第三实施型态的电性连接示意图；
图4c是本发明第四实施型态的电性连接示意图；
图4d是本发明第五实施型态的电性连接示意图；
图4e是本发明第六实施型态的电性连接示意图；
图4f是本发明第七实施型态的电性连接示意图。
具体实施方式
为了让本发明的目的、特征与功效更明显易懂，现举以下实施例并结合附图对本发明的结构、特征及功效进行详细说明。
如图1及图3所示，为本发明一种系统级封装的第一实施型态。如图1所示，一种薄型系统级封装，其封装结构中不具备印刷电路板，其包含：一铜支架10具有多信息连接脚11及至少一接地脚12；铜支架10的一顶面13上设有多个晶粒20、20`；各晶粒20、20`与铜支架10的信息连接脚11电性连接；铜支架10的顶面13上设有至少一被动元件40；被动元件40与各晶粒20、20`电性连接；各晶粒20、20`及被动元件40通过一绝缘胶52固定于铜支架10的顶面13上；各晶粒20、20`电性连接于铜支架10的接地脚12；一模制化合物50，其囊封铜支架10的顶面13上的各晶粒20、20`及被动元件40。
具体而言，其中晶粒20通过第一金属线30与铜支架10的信息连接脚11电性连接，而被动元件40通过第二金属线31与晶粒20电性连接，且晶粒20通过第三金属线32与铜支架10的接地脚12电性连接。
实际来说，晶粒20可部分通过多第一金属线30与信息连接脚11电性连接，另外，被动元件40可部分通过第二金属线31与晶粒20电性连接，且晶粒20可部分通过第三金属线32与接地脚12电性连接。
详细来说，铜支架10为导线架，其是晶粒(Die)封装内部的金属结构，用于将信号从晶粒(Die)传递到外部，其由不同的部分组成，通过结构连接将所有这些零件固定在框架结构内，这使得整个引线框架易于自动化处理；信息连接脚11的功效为提供晶粒20与外界的电性连接；接地脚12为在电路设计时的地线，地线则被广泛作为电位的参考点，为整个电路提供一个基准电位，以地在线电压为0V，以统一整个电路电位；绝缘胶52具备固定对象及不导电特性的胶状物，在质变后呈固化状，并维持固定对象及不导电特性。
接着，各晶粒20、20`是指晶粒(Die)是以半导体材料制作而成未经封装的一小块集成电路本体，主要来源为由晶圆切割分离；其中，第一金属线30、第二金属线31与第三金属线32实为打线接合(Wire bonding)的金属线材，是利用线径15-50微米的金属线材将晶粒(Chip)及导线架(Lead Frame)连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积；被动元件40为被动元件(Passive components)，又称无源器件，可以指消耗但不产生能量的电子元件，或者指无法产生增益的电子元件；模制化合物50为半导体封装材料，一般使用高分子树脂作为电子元件及晶粒(Chip)的封装材料。
请再参阅图3所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间通过第一金属线30电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；晶粒20与接地脚12间通过第三金属线32电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystal unit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；实际上，可再搭配内存元件等。
再如图2a及图4a所示，为本发明一种系统级封装的第二实施型态；第二实施型态与第一实施型态的主要差异在于本实施型态变更晶粒20与接地脚12间改由导电胶51电性连接；请先参考图2a所示，各晶粒20、20`通过一导电胶51与铜支架10的信息连接脚11电性连接。
实际而言，导电胶51是具备固定对象及导电特性的胶状物，在质变后呈固化状，并维持固定对象及导电特性。
实际来说，晶粒20与接地脚12间可部分由导电胶51电性连接，并可部分同第一实施型态的晶粒20通过第三金属线32与接地脚12电性连接；实际制作过程可先设置绝缘胶52于铜支架10的顶面13上，再设置导电胶51于绝缘胶52固化后表面。
再如图4a所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间通过第一金属线30电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystal unit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；被动元件40与接地脚12间通过一导电胶51电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；实际上，可再搭配内存元件等。
再如图2b及图4b所示，为本发明一种系统级封装的第三实施型态；第三实施型态与第一实施型态的主要差异在于本实施型态增加导电胶51电性连接；请先参考图2b所示，晶粒20通过一导电胶51与铜支架10的信息连接脚11电性连接。
再如图4b所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间可部分通过第一金属线30电性连接，且晶粒20部分通过导电胶51与铜支架10的信息连接脚11电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；晶粒20与接地脚12间通过第三金属线32电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystal unit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；实际上，可再搭配内存元件等。
再如图2c及图4c所示，为本发明一种系统级封装的第四实施型态；第四实施型态与第一实施型态的主要差异在于本实施型态增加导电胶51电性连接；请先参考图2c所示，被动元件40通过一导电胶51与铜支架10的信息连接脚11电性连接。
再如图4c所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间通过第一金属线30电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；晶粒20与接地脚12间通过第三金属线32电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；被动元件40与信息连接脚11可部分通过导电胶51电性连接；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystalunit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；实际上，可再搭配内存元件等。
再如图2d及图4d所示，为本发明一种系统级封装的第五实施型态；第五实施型态与第一实施型态的主要差异在于本实施型态增加导电胶51；请先参考图2d所示，被动元件40通过一导电胶51与铜支架10的接地脚12电性连接。
具体而言，被动元件40部分为接地电阻器、接地电容器等，因此需增加被动元件40与接地脚12的电性连接。
请再参阅图4d所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间通过第一金属线30电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；晶粒20与接地脚12间通过第三金属线32电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；被动元件40与接地脚12通过导电胶51电性连接；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystal unit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；实际上，可再搭配内存元件等。
再如图2e及图4e所示，为本发明一种系统级封装的第六实施型态；第六实施型态与第三实施型态的主要差异在于本实施型态增加第四金属线33电性连接；请先参考图2e所示，被动元件40通过至少一第四金属线33与铜支架10的信息连接脚11电性连接。
具体而言，第四金属线33实为打线接合(Wire bonding)的金属线材，是利用线径15-50微米的金属线材将晶粒(Chip)及导线架(Lead Frame)连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积。
再如图4b所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间通过第一金属线30电性连接，且晶粒20通过导电胶51与铜支架10的信息连接脚11电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；被动元件40与信息连接脚11可部分通过第四金属线33电性连接；晶粒20与接地脚12间通过第三金属线32电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystal unit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；实际上，可再搭配内存元件等。
再如图2f及图4f所示，为本发明一种系统级封装的第七实施型态；第七实施型态与第三实施型态的主要差异在于本实施型态增加第五金属线34电性连接；请先参考图2e所示，被动元件40，通过至少一第五金属线34与铜支架10的接地脚12电性连接。
具体而言，第五金属线34实为打线接合(Wire bonding)的金属线材，是利用线径15-50微米的金属线材将晶粒(Chip)及导线架(Lead Frame)连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积。
再如图4b所示，可见晶粒20分别对信息连接脚11、接地脚12及被动元件40电性连接；其中，晶粒20与信息连接脚11间通过第一金属线30电性连接，且晶粒20通过导电胶51与铜支架10的信息连接脚11电性连接，使外部讯号与电源得以与晶粒20电性导通，并将讯号传递出去；被动元件40与接地脚12可部分通过第五金属线34电性连接；晶粒20与接地脚12间通过第三金属线32电性连接，接地脚12作为电位的参考点，为整个电路提供一个基准电位，以接地脚12上电压为0V，以统一整个电路电位；晶粒20与被动元件40间通过第二金属线31电性连接，在此被动元件40可为石英振荡器(quartz crystal unit或,Xtal)、电阻器、电容器、电感器等，辅助晶粒20运行；实际上，可再搭配内存元件等。
因此本发明的功效有别一般半导体封装结构，此于半导体封装当中实属首创。
但需再次重申的是，以上所述仅为本发明的较佳实施型态，凡应用本发明说明书、权利要求书或附图所做的等效变化，仍属本发明所保护的技术范畴，因此本发明的专利保护范围当以后附的权利要求书所界定的范围为准。

Claims (10)

1.一种薄型系统级封装，其特征在于：封装结构中无印刷电路板，其包含：一铜支架，所述铜支架具有多信息连接脚及至少一接地脚；所述铜支架的一顶面上设有多个晶粒；各所述晶粒与所述铜支架的所述信息连接脚电性连接；所述铜支架的所述顶面上设有至少一被动元件；所述被动元件与各所述晶粒电性连接；各所述晶粒及所述被动元件通过一绝缘胶固定于所述铜支架的所述顶面上；各所述晶粒电性连接于所述铜支架的所述接地脚；一模制化合物，其囊封所述铜支架的所述顶面上的各所述晶粒及所述被动元件。
2.如权利要求1所述的薄型系统级封装，其特征在于：各所述晶粒，通过多个第一金属线与所述铜支架的所述信息连接脚电性连接。
3.如权利要求1所述的薄型系统级封装，其特征在于：所述被动元件，通过多个第二金属线与所述晶粒电性连接。
4.如权利要求1所述的薄型系统级封装，其特征在于：各所述晶粒，通过一导电胶与所述铜支架的所述信息连接脚电性连接。
5.如权利要求1所述的薄型系统级封装，其特征在于：各所述晶粒，通过一导电胶与所述铜支架的所述接地脚电性连接。
6.如权利要求1所述的薄型系统级封装，其特征在于：各所述晶粒，通过多个第三金属线与所述铜支架的所述接地脚电性连接。
7.如权利要求1所述的薄型系统级封装，其特征在于：所述被动元件，通过一导电胶与所述铜支架的所述信息连接脚电性连接。
8.如权利要求1所述的薄型系统级封装，其特征在于：所述被动元件，通过一导电胶与所述铜支架的所述接地脚电性连接。
9.如权利要求1所述的薄型系统级封装，其特征在于：所述被动元件，通过至少一第四金属线与所述铜支架的所述信息连接脚电性连接。
10.如权利要求1所述的薄型系统级封装，其特征在于：所述被动元件，通过至少一第五金属线与所述铜支架的所述接地脚电性连接。
CN202110661247.8A 2021-03-12 2021-06-15 薄型系统级封装 Pending CN115084119A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW110108822A TWI791200B (zh) 2021-03-12 2021-03-12 薄型系統級封裝
TW110108822 2021-03-12

Publications (1)

Publication Number Publication Date
CN115084119A true CN115084119A (zh) 2022-09-20

Family

ID=83195069

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110661247.8A Pending CN115084119A (zh) 2021-03-12 2021-06-15 薄型系统级封装

Country Status (5)

Country Link
US (1) US11869876B2 (zh)
JP (1) JP7141498B1 (zh)
KR (1) KR102559874B1 (zh)
CN (1) CN115084119A (zh)
TW (1) TWI791200B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024040805A (ja) 2022-09-13 2024-03-26 株式会社ジャパンディスプレイ 表示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5161304A (en) * 1990-06-06 1992-11-10 Sgs-Thomson Microelectronics, Inc. Method for packaging an electronic circuit device
US5089877A (en) * 1990-06-06 1992-02-18 Sgs-Thomson Microelectronics, Inc. Zero power ic module
KR100190283B1 (ko) * 1996-08-20 1999-06-01 윤종용 반도체 패키지 구조
US7018721B2 (en) * 2000-07-12 2006-03-28 Rohm Co., Ltd. Structure for interconnecting conductors and connecting method
JP2005123542A (ja) * 2003-10-20 2005-05-12 Genusion:Kk 半導体装置のパッケージ構造およびパッケージ化方法
JP4489485B2 (ja) * 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置
US8187920B2 (en) * 2009-02-20 2012-05-29 Texas Instruments Incorporated Integrated circuit micro-module
US8945990B2 (en) * 2012-04-24 2015-02-03 Infineon Technologies Ag Chip package and method of forming the same
JP5837187B2 (ja) * 2012-05-18 2015-12-24 京セラ株式会社 半導体素子収納用パッケージ、半導体装置および実装構造体
TWI492335B (zh) * 2013-02-08 2015-07-11 矽品精密工業股份有限公司 電子裝置及其封裝結構
KR101546572B1 (ko) * 2013-07-16 2015-08-24 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
CN210778596U (zh) * 2019-10-12 2020-06-16 中山市东翔微电子有限公司 一种led驱动ic封装结构
CN211182190U (zh) * 2020-01-07 2020-08-04 广东美的制冷设备有限公司 绝缘栅双极型晶体管、智能功率模块及空调器
JP2022086775A (ja) * 2020-11-30 2022-06-09 有限会社Mtec Ｌｓｉ素子の熱伝構造及びその熱伝構造を備えるｌｓｉ素子の製造方法

Also Published As

Publication number Publication date
US20220293562A1 (en) 2022-09-15
JP2022145400A (ja) 2022-10-04
TW202236539A (zh) 2022-09-16
JP7141498B1 (ja) 2022-09-22
TWI791200B (zh) 2023-02-01
US11869876B2 (en) 2024-01-09
KR20220128240A (ko) 2022-09-20
KR102559874B1 (ko) 2023-07-25

Similar Documents

Publication Publication Date Title
US20220352084A1 (en) Semiconductor package with layer structures, antenna layer and electronic component
EP3147942B1 (en) Semiconductor package, semiconductor device using the same and manufacturing method thereof
US10692827B2 (en) Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
CN112447534A (zh) 封装体及其制备方法
US20240186293A1 (en) Semiconductor package having chip stack
US20120244662A1 (en) Board on chip package substrate and manufacturing method thereof
CN115084119A (zh) 薄型系统级封装
CN115084118A (zh) 系统级封装
US10269718B2 (en) Rectangular semiconductor package and a method of manufacturing the same
WO2007139132A1 (ja) 半導体装置
US10153221B1 (en) Face down dual sided chip scale memory package
US11967559B2 (en) Electronic package
CN220474621U (zh) 线路载板及电子封装体
CN113497022B (zh) 电子系统、晶粒组件及元件晶粒
EP4283671A2 (en) Semiconductor device and manufacturing method thereof
KR20080085453A (ko) 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination