JP2011142361A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2011142361A JP2011142361A JP2011095911A JP2011095911A JP2011142361A JP 2011142361 A JP2011142361 A JP 2011142361A JP 2011095911 A JP2011095911 A JP 2011095911A JP 2011095911 A JP2011095911 A JP 2011095911A JP 2011142361 A JP2011142361 A JP 2011142361A
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- semiconductor chip
- metal plate
- semiconductor
- semiconductor device
- power supply
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Abstract
【解決手段】半導体装置2のパッケージPA内には、パワーMOS・FETが形成された半導体チップ4PH,4PLと、その動作を制御する制御回路が形成された半導体チップ4Dとが内包されている。ハイサイド側の半導体チップ4PHのソース電極用のボンディングパッド12S1,12S2は、金属板8Aを通じてダイパッド7D2に電気的に接続されている。ロウサイド側の半導体チップ4PLのソース電極用のボンディングパッド15S1は、金属板8Bを通じてリード配線7LBに電気的に接続されている。金属板8Bは、半導体チップ4PLのボンディングパッド15S1に接する第1部分8B1と、その第1部分8B1の短辺からリード配線7LBまで延びる第2部分8B2と、第1部分8B2の長辺からリード配線7LBまで延びる第3部分8B3とを有している。
【選択図】図6
Description
前記第2金属板は、前記第2半導体チップのソース電極に接続された第1部分と、前記第2半導体チップの1つの角を挟んで交差する2つの辺のうちの一方の辺を跨いで延在する第2部分と、前記第2部分から分かれた状態で、前記2つの辺のうちの他方の辺を跨いで延在する第3部分とを一体的に有するものである。
図1は本実施の形態1の半導体装置を有する非絶縁型DC−DCコンバータ1の一例の回路図、図2は図1の非絶縁型DC−DCコンバータ1の基本動作波形図をそれぞれ示している。
本実施の形態2では、上記金属板8Bの構成が前記実施の形態1と異なる。それ以外の構成は、前記実施の形態1と同じである。
本実施の形態3では、上記金属板8Bに形成される応力緩和用の穴の形状が前記実施の形態2と異なる。それ以外の構成は、前記実施の形態1,2と同じである。
本実施の形態4では、上記金属板8Bに形態される応力緩和用の穴の外周に窪みを形成する例を説明する。それ以外の構成は、前記実施の形態1,2,3と同じである。
本実施の形態5では、金属板8Bに形態される応力緩和用の穴の配置が前記実施の形態3と異なる。それ以外の構成は、前記実施の形態1〜3と同じである。
本実施の形態6では、上記金属板の裏面に応力緩和用の凹みを形成する例を説明する。
本実施の形態7では、半導体チップの外周の厚さが半導体チップの中央よりも薄く形成されている例を説明する。
本実施の形態8では、ハイサイド用のパワーMOSQH1が形成された半導体チップ4PHに接合された金属板8Aの第2部分8A2が複数に分割されている例を説明する。
本実施の形態9では、上記金属板8A,8Bの裏面に突起を形成する例を説明する。
本実施の形態10では、ロウサイド用のパワーMOSQL1にショットキーバリアダイオード(Schottky Barrier Diode)SBDを並列に接続した例を説明する。
本実施の形態11では、ロウサイド用のパワーMOSが形成された半導体チップ4PLのゲート配線19Gの配置の変形例について説明する。
本実施の形態12では、本実施の形態1〜11で説明した半導体装置2の製造方法の一例を図77のフロー図に沿って説明する。なお、ここでは、前記実施の形態3で説明した半導体装置2の製造方法を一例として説明する。
本実施の形態13においては、上記接着層11a〜11cの材料として、上記半田ペーストに代えて銀ペーストを用いる場合の半導体装置の製造方法について説明する。
本実施の形態14では、半導体装置2の他の製造方法の一例を図77(または図82)の製造フロー図に沿って図85〜図94により説明する。
図95は図64の半導体装置2の他の例のパッケージPAの内部を透かして見せた全体平面図、図96は図95の金属板8A,8Bを外した状態のパッケージPAの内部を透かして見せた全体平面図、図97は図95の半導体装置2の半導体チップ4PLの最上層を示した全体平面図、図98は図97の半導体チップ4PLの最上の配線層を示した全体平面図である。
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
2 半導体装置
3 制御回路
4D 半導体チップ(第3半導体チップ)
4PH 半導体チップ(第1半導体チップ)
4PL 半導体チップ(第2半導体チップ)
4S 半導体基板
4S1 半導体層
4S2 エピタキシャル層
7 リードフレーム
7D1,7D2,7D3 ダイパッド(チップ搭載部)
7L,7L1,7L2,7L3,7L4,7L5 リード(外部端子)
7LB リード配線(配線部)
8 金属板フレーム
8A 金属板(第1金属板)
8A1 第1部分
8A2 第2部分
8A3 吊り部
8B 金属板(第2金属板)
8B1 第1部分
8B2 第2部分
8B3 第3部分
8B4 第4部分
8C 金属板
8D 金属板
8E 金属板
8E1 第1部分
8E2 第2部分
8E3 第3部分
8E4 第4部分
9 メッキ層
11a〜11c 接着層
12G ボンディングパッド
12S1,12S2 ボンディングパッド(第1ソース電極領域)
12S3 ボンディングパッド(第2ソース電極領域)
13A,13B,13C,13D,13E,13F ボンディングパッド
15G ボンディングパッド
15S1 ボンディングパッド(第3ソース電極領域)
15S2 ボンディングパッド(第4ソース電極領域)
18 保護膜
19G ゲート配線
19G1 ゲートパッド部
19G2,19G3 ゲートフィンガ部
19S ソース配線
20a〜20d 開口部
21,21a,21b 金属層
22G1,22G2 ゲート配線
22G3 ゲート電極
25 フィールド絶縁膜
26 半導体領域
27 半導体領域
30 溝
31 ゲート絶縁膜
32 絶縁膜
33a,33b,33c コンタクトホール
35 半導体領域
38 配線基板
39a〜39e 配線
40L リード
45 窪み
46 スリット
47A,47B,47C 穴
48A 凹み
48B 凹み
50 窪み
51 ダイシングテープ
52A ダイシングソー
52B ダイシングソー
53 突起
55A 金属板(第1金属板)
55B 金属板(第2金属板)
56A 金属板(第3金属板)
56B 金属板(第4金属板)
56C 金属板(第5金属板)
LD 負荷
QH1,QL1 パワーMOS・FET(パワートランジスタ)
Cin 入力コンデンサ
Cout 出力コンデンサ
L コイル
DR1,DR2 ドライバ回路
D ドレイン
S ソース
IM 位置決め用のテーパ
VIN 入力電源
ET1 端子(第1電源端子)
ET2 端子(第2電源端子)
N 出力ノード
Dp1,Dp2 寄生ダイオード
Ton パルス幅
T パルス周期
PA パッケージ(封止体)
PB,PC,PD,PE,PF,PG パッケージ
PWL1 p型ウエル
BE 裏面電極
WA ボンディングワイヤ
WB ボンディングワイヤ
CA,CB,CC チップ部品
SBD ショットキーバリアダイオード
LU 単位領域
MU 単位領域
Claims (10)
- 導電体からなる第1、第2、第3チップ搭載部と、
前記第1、第2、第3チップ搭載部の周囲に配置された複数の外部端子と、
第1電界効果トランジスタを含む第1半導体チップと、
第2電界効果トランジスタを含む第2半導体チップと、
前記第1、第2電界効果トランジスタを駆動する回路を含む第3半導体チップと、
前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部および前記第1、第2、第3半導体チップを覆う封止体とを備え、
前記第1、第2、第3半導体チップは、それぞれ前記第1、第2、第3チップ搭載部上に配置され、
前記複数の外部端子は、
前記第1電界効果トランジスタのドレインに第1電源を供給する第1電源端子と、
前記第2電界効果トランジスタのソースに、前記第1電源よりも電位の低い第2電源を供給する第2電源端子とを備え、
前記第1電界効果トランジスタのソースと、前記第2電界効果トランジスタのドレインとを電気的に接続する第1金属板と、
前記第2半導体チップ上から前記第2電源端子に向かって延びるように配置され、前記第2電界効果トランジスタのソースと、前記第2電源端子とを電気的に接続する第2金属板とを備え、
前記第2金属板に開口部が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2金属板に、複数の前記開口部が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2金属板は、前記第2半導体チップ上に配置され、前記第2半導体チップ上のソース電極に接続される第1部分、および前記第1部分から前記第2電源端子に向かって延びる第2部分を有し、
前記開口部は、前記第2金属板の前記第1部分に形成されていることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、前記第1部分には、複数の前記開口部が形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、
前記封止体は、第1側面と、前記第1側面に対向する第2側面と、前記第1側面および前記第2側面との間に設けられた第3側面と、前記第3側面に対向する第4側面とを有し、
前記第2電源端子の1つは、前記第1側面から露出し、
前記第2電源端子の他の1つは、前記第3側面から露出し、
前記第2金属板は、前記第2半導体チップ上に配置され、前記第2半導体チップ上のソース電極に接続される第1部分、前記第1部分から前記第2電源端子の1つに向かって延びる第2部分、および前記第1部分から前記第2電源端子の他の一つに向かって延びる第3部分を有し、
前記開口部は、前記第2金属板の前記第1部分に形成されていることを特徴とする半導体装置。 - 導電体からなる第1、第2、第3チップ搭載部と、
前記第1、第2、第3チップ搭載部の周囲に配置された複数の外部端子と、
第1電界効果トランジスタを含む第1半導体チップと、
第2電界効果トランジスタを含む第2半導体チップと、
前記第1、第2電界効果トランジスタを駆動する回路を含む第3半導体チップと、
前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部および前記第1、第2、第3半導体チップを覆う封止体とを備え、
前記第1、第2、第3半導体チップは、それぞれ前記第1、第2、第3チップ搭載部上に配置され、
前記複数の外部端子は、
前記第1電界効果トランジスタのドレインに第1電源を供給する第1電源端子と、
前記第2電界効果トランジスタのソースに、前記第1電源よりも電位の低い第2電源を供給する第2電源端子とを備え、
前記第1電界効果トランジスタのソースと、前記第2電界効果トランジスタのドレインとを電気的に接続する第1金属板と、
前記第2電界効果トランジスタのソースと、前記第2電源端子とを電気的に接続する第2金属板とを備え、
前記第2金属板は、前記第2半導体チップ上に配置され、前記第2半導体チップ上のソース電極に接続される第1部分、および前記第1部分から前記第2電源端子に向かって延びる第2部分を有し、
前記第2金属板の前記第2部分に、前記第2電源端子から前記第1部分に向かって延びるスリットが形成されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記封止体は、第1側面と、前記第1側面に対向する第2側面と、前記第1側面および前記第2側面との間に設けられた第3側面と、前記第3側面に対向する第4側面とを有し、
前記第2電源端子の1つは、前記第1側面から露出し、
前記第2電源端子の他の1つは、前記第3側面から露出し、
前記第2金属板の前記第2部分は、前記第2電源端子の1つに向かって延びており、
前記第2金属板は、前記第1部分から前記第2電源端子の他の1つに向かって延びる第3部分を有し、
前記第2金属板の前記第3部分に、前記第2電源端子の他の1つから前記第1部分に向かって延びるスリットが形成されていることを特徴とする半導体装置。 - 導電体からなる第1、第2、第3チップ搭載部と、
前記第1、第2、第3チップ搭載部の周囲に配置された複数の外部端子と、
第1電界効果トランジスタを含む第1半導体チップと、
第2電界効果トランジスタを含む第2半導体チップと、
前記第1、第2電界効果トランジスタを駆動する回路を含む第3半導体チップと、
前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部および前記第1、第2、第3半導体チップを覆う封止体とを備え、
前記第1、第2、第3半導体チップは、それぞれ前記第1、第2、第3チップ搭載部上に配置され、
前記複数の外部端子は、
前記第1電界効果トランジスタのドレインに第1電源を供給する第1電源端子と、
前記第2電界効果トランジスタのソースに、前記第1電源よりも電位の低い第2電源を供給する第2電源端子とを備え、
前記第1電界効果トランジスタのソースと、前記第2電界効果トランジスタのドレインとを電気的に接続する第1金属板と、
前記第2半導体チップ上から前記第2電源端子に向かって延びるように配置され、前記第2電界効果トランジスタのソースと、前記第2電源端子とを電気的に接続する第2金属板とを備え、
前記第2金属板には、前記第2半導体チップに対向する面に突起部が設けられていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記第2金属板は、導電性の接着層を介して前記第2半導体チップ上のソース電極に接続されていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記第2金属板には、前記第2半導体チップに対向する面に複数の前記突起部が形成されていることを特徴とする半導体装置。
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