JP2005101137A - 回路形成用支持基板と、半導体素子搭載用パッケージ基板及びその製造方法 - Google Patents
回路形成用支持基板と、半導体素子搭載用パッケージ基板及びその製造方法 Download PDFInfo
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- JP2005101137A JP2005101137A JP2003331046A JP2003331046A JP2005101137A JP 2005101137 A JP2005101137 A JP 2005101137A JP 2003331046 A JP2003331046 A JP 2003331046A JP 2003331046 A JP2003331046 A JP 2003331046A JP 2005101137 A JP2005101137 A JP 2005101137A
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- Prior art keywords
- copper foil
- manufacturing
- forming
- foil
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
【解決手段】コア基板は、プリプレグ2の両側に銅張積層板のキャリア銅箔3を接着した構成を有する。このコア基板を第1の回路基板10とし、極薄銅箔4上に配線導体を形成して第2の回路基板20とする。この配線導体上に絶縁樹脂層を形成して第3の回路基板30とし、コンフォーマルマスクを形成して第4の回路基板40とし、非貫通孔を形成して第5の回路基板50とする。非貫通孔を銅メッキして導通し、その上に配線をエッチングして第6の回路基板とする。キャリア銅箔を含む支持基板を除去して第7の回路基板とし、極薄銅箔を除去して第8の回路基板を得る。
【選択図】図2−1
Description
a.キャリア箔付き極薄銅箔のキャリア箔面に第1の絶縁樹脂を設けてなる回路形成用支持基板を形成する工程、
b.パターン電解銅めっきにより第1の配線導体を形成する工程、
c.第2の絶縁樹脂を、第1の配線導体と接するように配置し、加熱加圧して積層する工程、
d.第2の絶縁樹脂に、第1の配線導体に達する非貫通孔を形成し、該非貫通孔内壁を電解銅めっき又は無電解銅めっきによって接続させ第2の配線導体を形成する工程、
e.キャリア箔付支持基板を剥離する工程、
f.極薄銅箔を除去する工程。
請求項1の銅張積層板を回路形成用支持基板として、請求項2の工程により作製された半導体素子搭載用パッケージ基板は、必要最低限の層数で引回しが可能なことから、層数を低減させ、総板厚が従来よりも薄い半導体素子搭載用パッケージ基板の作製を可能にする。また、半導体素子搭載用パッケージ基板の配線密度を上げることも可能になる。
キャリア箔としては、回路基板の製造工程における作業中に、半完成状態の回路基板が付いた回路形成用支持基板全体を充分支持できる程に剛性の大きいもので、且つ、回路形成後キャリア箔と極薄銅箔の界面で剥離できるものであればよく、銅箔に限定されるものではないが、支持基板層を簡単に除去するためにキャリア銅箔にはピーラブル銅箔を使用することが望ましい。また、ピーラブル銅箔の構成は、キャリア銅箔に剥離層を有していることが好ましい。剥離層は有機/無機系材料の制約はないが、ニッケル又はクロム系の単層あるいは合金層が好ましい。キャリア銅箔の厚みは、極薄銅箔の厚みに対して、キャリア/薄銅=18〜75μmt/1〜5μmtがハンドリング上好ましい。なお、キャリア箔に銅箔を用いた場合、極薄銅箔との界面は、断面観察により容易に区別できる。
使用する絶縁樹脂層は、通常のガラスクロスに熱硬化性樹脂を含浸させたプリプレグ、フィルム材が望ましい。
本発明によれば、金属板の代わりに両面に銅箔の付いた基板を支持基板として用い、両面同時に回路パターンが形成できるため、生産性は金属板を支持層に使った場合の2倍となる。更に表裏に積層していくため、反りに関して基板全体のバランスが良く、安定して微細配線を形成することができる。
上述の熱可塑性樹脂をフィルム加工したものをコア基板の絶縁樹脂層として用いてもよく、図1におけるプリプレグ2の替わりに用いてもよい。
公称厚み0.06mmのプリプレグGEA−679F(日立化成工業株式会社製、商品名)を2枚重ね、その両側に、極薄銅箔厚3μmにキャリア銅箔厚35μmが貼り合わされたピーラブル銅箔FD−P3/35(古河サーキットフォイル株式会社製、商品名)を35μmの銅箔面が上記プリプレグと接着するように構成し、温度175±2℃、圧力2.5±0.2MPa、保持時間60分の条件にて真空プレスを実施し、表面が3μm銅箔の銅張積層板(MCL)を作製し、第1の回路基板10とした。
2 プリプレグ
3 キャリア銅箔
4 極薄銅箔
Claims (11)
- 絶縁樹脂層が、キャリア箔付き極薄銅箔のキャリア箔面に接着されてなる回路形成用支持基板。
- 以下のa、b、c、d、e、fの工程の順に製造される半導体素子搭載用パッケージ基板の製造方法。
a.キャリア箔付き極薄銅箔のキャリア箔面に第1の絶縁樹脂を設けてなる回路形成用支持基板を形成する工程、
b.パターン電解銅めっきにより第1の配線導体を形成する工程、
c.第2の絶縁樹脂を、第1の配線導体と接するように配置し、加熱加圧して積層する工程、
d.第2の絶縁樹脂に、第1の配線導体に達する非貫通孔を形成し、該非貫通孔内壁を電解銅めっき又は無電解銅めっきによって接続させ第2の配線導体を形成する工程、
e.キャリア箔付支持基板を剥離する工程、
f.極薄銅箔を除去する工程。 - 以下のa−1〜f−1の工程の順に製造される半導体素子搭載用パッケージ基板の製造方法。
a−1.キャリア箔付き極薄銅箔と絶縁樹脂層からなる回路形成用支持基板を形成する工程、
b−1.キャリア箔付き極薄銅箔の極薄銅箔側にめっきレジストをラミネートする工程、
b−2.フォトリソグラフィーにより、配線回路形成にめっきレジストパターンを形成する工程、
b−3.電解銅めっきにより第1の配線導体を形成する工程、
b−4.めっきレジストを除去する工程、
c−1.第1の配線導体表面に絶縁樹脂との密着力を得るための粗化処理をする工程、
c−2.絶縁樹脂を、工程c−1で粗化処理を施した第1の配線導体と接するように配置し、加熱加圧して積層する工程、
d−1.第2の絶縁樹脂に、第1の配線導体に達する非貫通孔を形成する工程、
d−2.該非貫通孔内壁を電解銅めっき又は無電解銅めっきにより接続させる工程、
d−3.第2の配線導体をサブトラクティブ工法またはセミアディティブ工法にて形成す
る工程、
e−1.キャリア箔付支持基板を剥離する工程、
f−1.極薄銅箔を除去する工程。 - 請求項3において、d−3工程後、c−1工程からd−3工程を繰り返し行い、ビルドアップ構造を有した半導体素子搭載用パッケージ基板の製造方法。
- 請求項2乃至4において、a−1工程における絶縁樹脂層が、厚さ0.03mm以上有する半導体素子搭載用パッケージ基板の製造方法。
- 請求項2乃至5において、a−1工程におけるキャリア銅箔付き極薄銅箔の極薄銅箔の厚さが7μm未満である半導体素子搭載用パッケージ基板の製造方法。
- 請求項2のd工程若しくは、請求項3乃至6のd−1工程における非貫通孔をレーザーによって形成する半導体素子搭載用パッケージ基板の製造方法。
- 請求項3乃至7のc−2工程〜d−2工程において、第1の配線導体上に金属バンプを形成し、金属バンプ付第1の配線導体上に接するように絶縁樹脂、キャリア箔付き極薄銅箔の順に配置し、加熱加圧することにより外層と第1の配線(内層)の接続を得た半導体素子搭載用パッケージ基板の製造方法。
- 請求項2のe工程若しくは、請求項3乃至8のe−1工程のキャリア箔付支持基板の剥離を物理的に剥離しておこなう半導体素子搭載用パッケージ基板の製造方法。
- 請求項2のf工程若しくは、請求項3乃至9のf−1工程における極薄銅箔の除去を硫酸/過酸化水素系エッチング液を用いて除去する半導体素子搭載用パッケージ基板の製造方法。
- 請求項2乃至10の製造方法によって作製された半導体素子搭載用パッケージ基板。
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