WO2022138238A1 - 配線基板及びそのトリミング方法、並びに多層配線板 - Google Patents
配線基板及びそのトリミング方法、並びに多層配線板 Download PDFInfo
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- WO2022138238A1 WO2022138238A1 PCT/JP2021/045561 JP2021045561W WO2022138238A1 WO 2022138238 A1 WO2022138238 A1 WO 2022138238A1 JP 2021045561 W JP2021045561 W JP 2021045561W WO 2022138238 A1 WO2022138238 A1 WO 2022138238A1
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- Prior art keywords
- wiring board
- region
- layer
- insulating
- boundary region
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09936—Marks, inscriptions, etc. for information
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
Definitions
- the present invention relates to a wiring board, a trimming method thereof, and a multilayer wiring board.
- multi-layered printed wiring boards In recent years, in order to increase the mounting density of printed wiring boards (wiring boards) and reduce the size, multi-layered printed wiring boards have become widespread. Such multi-layer printed wiring boards (multi-layer wiring boards) are used in many portable electronic devices for the purpose of weight reduction and miniaturization. Further, the multilayer printed wiring board is required to further reduce the thickness of the interlayer insulating layer and further reduce the weight of the wiring board.
- the coreless build-up method is a method in which an insulating layer and a wiring layer are alternately laminated (built-up) to form a multi-layered structure without using a so-called core substrate.
- the coreless build-up method it has been proposed to use a metal foil with a carrier so that the support and the multilayer printed wiring board can be easily peeled off.
- Patent Document 1 Japanese Unexamined Patent Publication No.
- an insulating resin layer is attached to the carrier surface of a copper foil with a carrier to form a support, and a photoresist process is performed on the ultrathin copper layer side of the copper foil with a carrier.
- Patent Document 1 In order to miniaturize the embedded circuit as shown in Patent Document 1, a metal foil with a carrier having a metal layer thickness of 1 ⁇ m or less is desired. Therefore, in order to reduce the thickness of the metal layer, it has been proposed to form the metal layer by a vapor phase method such as sputtering.
- a vapor phase method such as sputtering.
- Patent Document 2 International Publication No. 2017/150283
- a carrier in which a release layer, an antireflection layer, and an ultrathin copper layer for example, a film thickness of 300 nm
- the attached copper foil is disclosed.
- Patent Document 3 International Publication No.
- an intermediate layer for example, an adhesive metal layer and a peeling auxiliary layer
- a peeling layer and an ultrathin copper layer for example, a film thickness of 300 nm
- a carrier such as a glass sheet.
- an intermediate layer made of a predetermined metal is interposed to provide excellent stability of the mechanical peel strength of the carrier, and the antireflection layer exhibits a desirable dark color. It is also taught to improve visibility in inspections (eg, automated imaging inspection (AOI)).
- AOI automated imaging inspection
- Patent Document 4 Japanese Unexamined Patent Publication No. 2015-35551 describes the formation of a metal release layer on the main surface of a support made of glass or a silicon wafer, the formation of an insulating resin layer on the main surface, and the formation of an insulating resin layer on the main surface.
- methods of manufacturing semiconductor devices including forming solder bumps on the surface of a secondary mounting pad and secondary mounting.
- the trimmable wiring board includes, for example, a plurality of device regions in which wiring patterns for mounting semiconductor chips are present, and a peripheral region that surrounds and discards the peripheral regions around these device regions.
- the trimmable wiring board has a problem that cracks and warpage are likely to occur due to the non-uniformity of the wiring pattern density between the device region and the peripheral region.
- Patent Document 5 Japanese Unexamined Patent Publication No. 2016-724173 describes a semiconductor device including a device region formed on a semiconductor substrate and a peripheral region formed so as to surround the device region. It is disclosed that the region has an aperiodic pattern formed so as to surround the device region. Further, in Patent Document 6 (Japanese Patent Laid-Open No.
- Patent Document 7 Japanese Unexamined Patent Publication No. 2009-239149
- conductivity arranged in the scribe line region is provided. It is disclosed to have a sexual pattern.
- a step of peeling the wiring board from the carrier includes, for example, attaching a reinforcing sheet (second carrier) to the wiring board, trimming the wiring board and the like, and peeling the trimmed combination of the wiring board and the reinforcing sheet from the carrier.
- a reinforcing sheet second carrier
- peeling the trimmed combination of the wiring board and the reinforcing sheet from the carrier when the wiring board or the like is peeled off from the carrier, the wiring board cannot be peeled off according to the trimmed position, and an unintended crack (cracking, tearing, etc.) may occur in the wiring board.
- the wiring board in which such cracks are generated suffers from insulation destruction and wiring as a result of the penetration of etching liquid, desmear liquid, various plating liquids or their cleaning liquids, moisture in the air and dew condensation water derived from the cracks during the manufacturing process. Problems such as corrosion of parts are likely to occur.
- the present inventors have an insulating boundary having a winding shape capable of drawing a virtual straight line satisfying a predetermined condition between a device area and a peripheral area surrounding the device area. It was found that the mechanical strength, water resistance, moisture resistance and product yield at the time of trimming and after trimming can be improved by interposing the region for trimming.
- an object of the present invention is to provide a wiring board capable of improving mechanical strength, water resistance, moisture resistance and product yield at the time of trimming and thereafter.
- the device area where the main wiring pattern composed of the metal layer is embedded in the insulating layer A peripheral area surrounding the device area and having a dummy wiring pattern composed of a metal layer electrically independent of the main wiring pattern embedded in the insulating layer.
- a multilayer wiring board including the wiring board is provided.
- FIG. 1 conceptually shows the wiring board of the present invention
- FIG. 2A shows an enlarged view of a portion surrounded by a dotted line in FIG.
- the wiring board 10 of the present invention includes a device region D, a peripheral region P, and an insulating boundary region B.
- a main wiring pattern composed of a metal layer is embedded in the insulating layer.
- the peripheral area P is an area surrounding the device area D.
- a dummy wiring pattern composed of a metal layer electrically independent of the main wiring pattern is embedded in the insulating layer.
- the insulation boundary region B is a region that is interposed between the device region D and the peripheral region P and is composed of an insulating layer and does not have a metal layer. As shown in FIGS. 1 and 2A, the insulating boundary region B is parallel to the inner tangent line I of at least one side of the outer edge of the device region D when viewed in a plan view, and is an insulating boundary with the metal layer constituting the dummy wiring pattern. It has a winding shape capable of drawing a virtual straight line L that alternately traverses the insulating layer constituting the region B. Then, the device region D is completely separated from the virtual straight line L with the insulation boundary region B separated from the virtual straight line L when viewed in a plan view.
- the insulating boundary region B having a winding shape capable of drawing the predetermined virtual straight line L between the device region D and the peripheral region P surrounding the device region D.
- a step of peeling the wiring board from the carrier is performed.
- FIGS. 3A to 4B an example of the process of peeling the wiring board from the carrier.
- a wiring board 110 having a device region D, a peripheral region P, and an insulating boundary region B on a metal foil 100 with a carrier is known (for example).
- a carrier for example, having a carrier, a peeling layer, and a metal layer in this order
- it is formed by the build-up method described above (FIGS. 3A (i) and 3B (i)).
- the reinforcing sheet 120 (second carrier) is laminated on the wiring board 110 via an adhesive layer or the like (FIGS. 3A (ii) and 3B (ii)). Then, using the cutting tool T, a notch is made through the reinforcing sheet 120 and the wiring board 110 (FIG. 3A (iii)). At this time, by inserting the cut line C so as to cross the insulation boundary region B, the device region D of the wiring board 110 and the peripheral region P surrounding the device region P are divided (FIG. 3B (iii)). Then, the combination of the divided wiring board 110 (device region D portion) and the reinforcing sheet 120 is peeled off from the carrier-attached metal foil 100 (FIGS. 4A (iv) and 4B (iv)). In this way, the trimmed wiring board 110 is transferred to the reinforcing sheet 120 (FIGS. 4A (v) and 4B (v)).
- the conventional wiring board 210 is composed of an insulating layer interposed between the device region D and the peripheral region P, and the insulating boundary region B in which no metal layer is present has a linear shape. ing. Therefore, the cut line C for dividing the device region D and the peripheral region P continuously crosses the insulating layer constituting the insulating boundary region B. As a result, it is considered that the wiring board 210 is cracked during trimming or carrier peeling due to the low-strength insulating layer constituting the insulating boundary region B. Since the combination of the metal and the insulating material in the wiring board is generally determined, it is difficult to change the type of the insulating material constituting the insulating layer.
- the insulating boundary region B alternately traverses the metal layer constituting the dummy wiring pattern (of the peripheral region P) and the insulating layer constituting the insulating boundary region B. It has a winding shape that allows a straight line L to be drawn. Therefore, when the wiring board 10 is cut along the virtual straight line L, the insulating layer and the metal layer made of a metal having a higher strength than the insulating material constituting the insulating layer are formed at the cut portion (length). It will be present alternately (in the direction, the width direction and / or the thickness direction).
- the mechanical strength of the wiring board 10 is greatly improved as compared with the conventional wiring board 210 in which the insulating layer is continuously present at the cut portion.
- the device region D is completely separated from the virtual straight line L across the insulation boundary region B when viewed in a plan view. That is, even when the wiring board 10 is cut along the virtual straight line L, the device region D is surrounded by the insulation boundary region B. Therefore, the insulation boundary region B prevents moisture in the air and water such as dew condensation water derived from the etching liquid, desmear liquid, various plating liquids or their cleaning liquids from infiltrating into or near the circuit of the device region D. This can be effectively prevented, and the water resistance and moisture resistance of the wiring board 10 are improved.
- the wiring board 10 is cut along the virtual straight line L. That is, according to a preferred embodiment of the present invention, a method for trimming a wiring board 10 including a step of preparing a wiring board 10 and a step of cutting the wiring board 10 along a virtual straight line L and removing a peripheral region P. Is provided.
- the main wiring pattern in the device area and the dummy wiring pattern in the peripheral area so that a high-strength metal layer exists at the cut portion.
- the main wiring pattern of the device region D and the dummy wiring pattern of the peripheral region P are separated by the insulation boundary region B and are electrically independent. Therefore, for example, an electrical inspection for each device region D can be performed even at a stage before trimming or carrier peeling of the wiring board 10.
- the insulation boundary region B When viewed in a plan view, the insulation boundary region B constitutes an insulation boundary region B with a metal layer constituting a dummy wiring pattern on all sides of the outer edge of the device region D in parallel with the inscribed line I of each side. It is preferable to have a winding shape capable of drawing a virtual straight line L that alternately traverses the insulating layer.
- the device region D is preferably completely separated from the virtual straight line L for all the sides with the insulation boundary region B in the plan view. By doing so, the mechanical strength, water resistance, and moisture resistance of the wiring board 10 can be further improved.
- the winding shape of the insulation boundary region B is not limited to the shape shown in FIGS. 1 and 2A, and may be any shape including the shape shown in FIGS. 2B to 2H.
- the outer edge shape of the peripheral region P in contact with the insulating boundary region B and / or the outer edge shape of the device region D in contact with the insulating boundary region B is a comb shape (see, for example, FIG. 2A).
- Curved waveforms eg, see FIGS. 2B
- triangles see, eg, FIGS. 2C
- trapezoids see, eg, FIGS. 2E and 2H
- spindles eg, see FIGS.
- fasteners see, eg, FIGS. 2F and 2G or them. It is preferably configured to include a combination of, and more preferably a comb shape. By doing so, when the wiring board 10 is viewed in a plan view, the boundary between the metal layer constituting the dummy wiring pattern or the main wiring pattern and the insulating layer constituting the insulating boundary region B becomes a complicated shape, and as a result, at the time of trimming. And after that, it becomes possible to further improve the mechanical strength of the wiring board 10.
- the number of metal layers constituting the dummy wiring pattern crossed by the virtual straight line L and the number of insulating layers constituting the insulating boundary region B are 1 or more and 3000 or less per 1 mm with respect to the length of the virtual straight line L, respectively. It is preferable that the number is 4 or more and 1000 or less per 1 mm.
- the winding shape of the insulation boundary region B includes a wavy pattern.
- This wavy pattern can be a sine wave (eg, see FIG. 2B), a sawtooth wave, a square wave (eg, see FIG. 2A), a trapezoidal wave (eg, see FIGS. 2E and 2H), a triangular wave (see, eg, FIG. 2C), or a combination thereof. It preferably contains, more preferably a square wave.
- the sine wave, sawtooth wave, square wave, trapezoidal wave, and triangular wave may be partially or wholly deformed within the range of achieving the object of the present invention.
- 2D, 2F and 2G is included in these wavy patterns as a modification of a rectangular wave or a trapezoidal wave. Further, if the width of the insulation boundary region B is constant, it may be easier to design and manufacture, but at least a part thereof may not be constant within the range of achieving the object of the present invention.
- the width of the insulation boundary region B (that is, the separation distance between the device region D and the peripheral region P) is not particularly limited, but is typically 0.1 ⁇ m or more and 2000 ⁇ m or less, more typically 0.5 ⁇ m or more and 1000 ⁇ m or less, and further. It is preferably 1 ⁇ m or more and 250 ⁇ m or less.
- the width of the insulating boundary region B is preferably 0.02 times or more and 250 times or less, more preferably 0.10 times or more and 50 times or less the thickness t of the wiring board.
- the linear expansion coefficient of the metal constituting the metal layer of the main wiring pattern is preferably 0.10 times or more and 10 times or less the linear expansion coefficient of the resin constituting the insulating layer of the insulating boundary region B. , More preferably 0.20 times or more and 5 times or less, still more preferably 0.30 times or more and 3 times or less, and particularly preferably 0.50 times or more and 2 times or less. Within such a range, it is possible to effectively prevent moisture from entering from the interface between the device region D and the insulating boundary region B, and the water resistance and moisture resistance of the wiring board 10 are further improved. be able to.
- the size of the wiring board 10 is not particularly limited. When the substrate shape is rectangular, it is preferably 1.0 mm square or more and 150 cm square or less, and more preferably 3 mm square or more and 75 cm square or less.
- the number of device regions D included in the wiring board 10 is not particularly limited, but is preferably 1 or more and 5000 or less, and more preferably 4 or more and 2000 or less.
- the wiring board 10 may be manufactured by any method. For example, by preparing a metal leaf with a carrier having a release layer and a metal layer on the carrier and laminating a wiring layer and an insulating layer on the metal leaf with a carrier by using a known method, the above-mentioned predetermined device region A wiring board 10 having D, a peripheral region P, and an insulating boundary region B can be obtained. Therefore, the wiring board 10 may have a carrier and a peeling layer on the carrier, and may have a device region D, a peripheral region P, and an insulating boundary region B on the peeling layer. As described above, the wiring board 10 having such a configuration can be electrically inspected even before trimming or carrier peeling.
- the occurrence of cracks in the wiring board 10 during trimming or carrier peeling can be effectively suppressed, and desmear liquid, dew condensation water, moisture in the air, or the like infiltrates into the circuit of the device region D. Furthermore, it is possible to effectively prevent short circuits and migrations caused by these.
- the carrier may be made of any of glass, ceramics, silicon, resin, and metal, but is preferably a substrate or a glass substrate containing silicon.
- the substrate containing silicon may be any substrate as long as it contains Si as an element, and a SiO 2 substrate, a SiN substrate, a Si single crystal substrate, a Si polycrystalline substrate, or the like can be applied. More preferably, it is a glass carrier, a single crystal silicon substrate or a polycrystalline silicon substrate.
- the carrier is a glass carrier, it has surface flatness (coplanarity) that is advantageous for forming fine circuits, desmear in the wiring manufacturing process, and chemical resistance in various plating processes, and further, wiring. There is an advantage that a chemical separation method can be adopted when peeling the carrier from the substrate.
- the glass constituting the carrier include quartz glass, borosilicate glass, non-alkali glass, soda lime glass, aluminosilicate glass, and combinations thereof, and more preferably non-alkali glass, soda lime glass, and the like. It is a combination thereof, and particularly preferably non-alkali glass.
- Alkaline-free glass is mainly composed of silicon dioxide, aluminum oxide, boron oxide, and alkaline earth metal oxides such as calcium oxide and barium oxide, and further contains boric acid, and substantially does not contain alkali metal. It is glass.
- This non-alkali glass is stable with a low coefficient of thermal expansion in the range of 3 ppm / K or more and 5 ppm / K or less in a wide temperature range from 0 ° C to 350 ° C, so that warpage of the glass in a process involving heating is minimized. There is an advantage that it can be done.
- the thickness of the carrier is preferably 100 ⁇ m or more and 2000 ⁇ m or less, more preferably 300 ⁇ m or more and 1800 ⁇ m or less, and further preferably 400 ⁇ m or more and 1100 ⁇ m or less. When the carrier has a thickness within such a range, it is possible to reduce the thickness of the wiring and the warp that occurs when electronic components are mounted, while ensuring an appropriate strength that does not hinder handling.
- the surface of the carrier preferably has a maximum height Rz of less than 1.0 ⁇ m measured in accordance with JIS B 0601-2001, more preferably 0.001 ⁇ m or more and 0.5 ⁇ m or less, still more preferably 0.001 ⁇ m or more. It is 0.1 ⁇ m or less, more preferably 0.001 ⁇ m or more and 0.08 ⁇ m or less, particularly preferably 0.001 ⁇ m or more and 0.05 ⁇ m or less, and most preferably 0.001 ⁇ m or more and 0.02 ⁇ m or less.
- the smaller the maximum height Rz of the carrier surface the less desirable the maximum height Rz can be obtained on the outermost surface of the metal layer laminated on the carrier (that is, the surface opposite to the peeling layer).
- the wiring is highly miniaturized to the extent that the line / space (L / S) is 13 ⁇ m or less / 13 ⁇ m or less (for example, 12 ⁇ m / 12 ⁇ m to 2 ⁇ m / 2 ⁇ m). It will be suitable for forming a pattern.
- the peeling layer is a layer that enables or facilitates peeling of the carrier.
- the peeling layer may be peeled by a method of physically applying a force, or may be peeled by a method of peeling by a laser (laser lift-off, LLO). That is, the peeling layer may be made of a resin whose adhesive strength at the interface is lowered by irradiation with a laser beam after curing, or may be a layer such as silicon or silicon carbide modified by irradiation with a laser beam. Further, if the peeling is possible by a method of physically applying a force without irradiating with a laser, either an organic peeling layer or an inorganic peeling layer may be used.
- Examples of the organic component used in the organic exfoliation layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, and carboxylic acids.
- Examples of nitrogen-containing organic compounds include triazole compounds and imidazole compounds.
- examples of the inorganic component used in the inorganic release layer include at least one of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, and Mo. Examples thereof include metal oxides or metal oxynitrides including the above, carbon and the like.
- the peeling layer is preferably a layer containing carbon mainly from the viewpoint of ease of peeling and film forming property, more preferably a layer mainly composed of carbon or a hydrocarbon, and further preferably a hard carbon film. It is a layer made of a certain amorphous carbon.
- the exfoliated layer (that is, the carbon-containing layer) preferably has a carbon concentration of 60 atomic% or more, more preferably 70 atomic% or more, still more preferably 80 atomic% or more, and particularly preferably 85, as measured by XPS. Atomic% or more.
- the upper limit of the carbon concentration is not particularly limited and may be 100 atomic%, but 98 atomic% or less is realistic.
- the exfoliated layer may contain unavoidable impurities (eg, oxygen, carbon, hydrogen, etc. derived from the surrounding environment such as atmosphere). Further, due to the film forming method of the layer to be laminated later, a metal atom of a kind other than the metal contained as the peeling layer may be mixed in the peeling layer.
- a carbon-containing layer is used as the peeling layer, the mutual diffusivity and reactivity with the carrier are small, and even if the carrier is pressed at a temperature exceeding 300 ° C., the carrier can be easily peeled off and removed. can do.
- the peeling layer is preferably a layer formed by a vapor phase method such as sputtering, from the viewpoint of suppressing excessive impurities in the peeling layer and from the viewpoint of continuous productivity of other layers.
- the thickness is preferably 1 nm or more and 20 nm or less, and more preferably 1 nm or more and 10 nm or less. This thickness is a value measured by analyzing the layer cross section with an energy dispersive X-ray spectrophotometer (TEM-EDX) of a transmission electron microscope.
- TEM-EDX energy dispersive X-ray spectrophotometer
- the release layer may be a metal oxynitride-containing layer instead of such a carbon layer or the like.
- the surface of the metal oxynitride-containing layer opposite to the carrier preferably contains at least one metal oxynitride selected from the group consisting of TaON, NiON, TiON, NiWON and MoON. ..
- the surface of the metal oxynitride-containing layer on the carrier side is Cu, Ti, Ta, Cr, Ni, Al, Mo, Zn, W, TiN and TaN. It is preferable to include at least one selected from the group consisting of.
- the thickness of the metal oxynitride-containing layer is preferably 5 nm or more and 500 nm or less, more preferably 10 nm or more and 400 nm or less, further preferably 20 nm or more and 200 nm or less, and particularly preferably 30 nm or more and 100 nm or less. This thickness is a value measured by analyzing the layer cross section with an energy dispersive X-ray spectrophotometer (TEM-EDX) of a transmission electron microscope.
- TEM-EDX energy dispersive X-ray spectrophotometer
- the wiring board 10 includes the device area D, the peripheral area P, and the insulation boundary area B, the wiring board 10 includes layers other than the carrier and the peeling layer as long as the original functions of the wiring board 10 are not impaired. May be good.
- examples of such other layers include an intermediate layer and an antireflection layer (etching stopper) as shown in Patent Document 2 (International Publication No. 2017/150283) and Patent Document 3 (International Publication No. 2017/150284). Layer), ultra-thin copper layer (metal layer) and the like.
- the wiring board 10 of the present invention may be a multi-layer wiring board in which a wiring layer and an insulating layer are multi-layered. That is, according to a preferred embodiment of the present invention, a multilayer wiring board including the wiring board 10 described above is provided.
- a multilayer wiring board for example, a wiring layer and an insulating layer are alternately laminated on the surface of a metal leaf with a carrier by the above-mentioned build-up method to form a build-up layer, and then the metal leaf with a carrier is peeled off and removed. Therefore, it can be preferably produced.
- the predetermined device region D, the peripheral region P, and the insulation boundary region B are composed of any one or all of the multilayer wiring layer and the insulation layer.
- Example 1 A metal foil with a carrier in which a release layer (amorphous carbon layer) and a metal layer (copper layer) were formed by sputtering on the carrier was prepared.
- a wiring board was produced by laminating a wiring layer and an insulating layer on the surface of the copper layer of the metal foil with a carrier. The specific procedure is as follows.
- amorphous carbon layer (thickness 6 nm) and a copper layer (thickness) are placed on a glass sheet (material: soda lime glass) with a size of 350 mm ⁇ 350 mm and a thickness of 1.1 mm as a carrier.
- a metal foil with a carrier having a film thickness of 300 nm) formed by sputtering was prepared.
- a wiring layer including a main wiring pattern and a dummy wiring pattern was formed. Specifically, first, a photosensitive dry film was attached to the surface of the metal foil with a carrier on the copper layer side, exposed and developed to form a photoresist layer having a predetermined pattern. Next, the exposed surface of the copper layer (that is, the portion not masked by the photoresist layer) was subjected to pattern electrolytic copper plating to form the electrolytic copper plating layer, and then the photoresist layer was peeled off.
- the copper layer and the electrolytic copper plating layer were left in the main wiring pattern and the dummy wiring pattern, while the copper layer in the portion where these wiring patterns were not formed was exposed.
- the unnecessary portion of the exposed copper layer was removed with an etching solution to form a wiring layer in which the main wiring pattern and the dummy wiring pattern were electrically independent of each other.
- an insulating resin material photosensitive insulating material, AR-5100 manufactured by Showa Denko Materials Co., Ltd.
- An insulating layer was formed. In this way, a wiring board including the device region D, the peripheral region P, and the rectangular wavy insulating boundary region B as shown in FIG. 2A was produced.
- Example 2 (comparison) As shown in FIG. 5, the wiring board was manufactured in the same manner as in Example 1 except that the wiring layer and the insulating layer were formed so that the insulating boundary region B had a linear shape.
- a reinforcing sheet (prepreg, FR-4 manufactured by Panasonic Corporation, thickness 200 ⁇ m) is laminated on the surface of the wiring board opposite to the carrier, and then the carrier is manually pulled from the wiring board. It was done by peeling it off.
- FIG. 6 When the surface of the wiring board after the carrier was peeled off in the wiring board produced in Example 1 was photographed, the image shown in FIG. 6 was obtained. Further, when the periphery of the insulation boundary region B of the wiring board of Example 1 was observed with an optical microscope (60 times) after the carrier was peeled off, the image shown in FIG. 7 was obtained. Note that FIG. 7 also shows the position of the cut line C for cutting the wiring board. As shown in FIGS. 6 and 7, in the wiring board produced in Example 1, no cracks or tears were observed on the surface after the carrier was peeled off. Further, even after the wiring board was cut according to the cut line C, no crack or tear was observed on the surface of the wiring board.
- FIG. 8 shows the image shown in FIG. 8 when the surface of the wiring board in which delamination occurred at the boundary of the pattern in the wiring board produced in Example 2 was photographed. Further, when the periphery of the insulation boundary region B of the wiring board of Example 2 after the carrier peeling was observed with an optical microscope (60 times), the image shown in FIG. 9 was obtained. Note that FIG. 9 also shows the position of the cut line C for cutting the wiring board. As shown in FIGS. 8 and 9, in the wiring board produced in Example 2, it was confirmed that linear cracks were present on the surface after the carrier was peeled off.
- the wiring board having the insulating boundary region having a winding shape (rectangular wavy shape) produced in Example 1 has higher strength than the wiring board having the insulating boundary region having a linear shape produced in Example 2. It was hard to crack.
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Abstract
Description
金属層で構成される主配線パターンが絶縁層中に埋設されたデバイス領域と、
前記デバイス領域の周りを取り囲み、前記主配線パターンと電気的に独立した金属層で構成されるダミー配線パターンが絶縁層中に埋設された周辺領域と、
前記デバイス領域と前記周辺領域との間に介在し、絶縁層で構成される、金属層が存在しない絶縁境界領域と、
を備えた配線基板であって、
前記絶縁境界領域は、平面視した場合に、前記デバイス領域の外縁の少なくとも1辺の内接線と平行に、前記ダミー配線パターンを構成する金属層と前記絶縁境界領域を構成する絶縁層とを交互に横断する仮想直線を引くことが可能な、曲がりくねった形状を有しており、
前記デバイス領域は、平面視した場合に、前記仮想直線から前記絶縁境界領域を隔てて完全に離れている、配線基板が提供される。
前記配線基板を用意する工程と、
前記配線基板を前記仮想直線に沿って切断し、前記周辺領域を除去する工程と、
を含む、配線基板のトリミング方法が提供される。
図1に本発明の配線基板を概念的に示す一方、図2Aに図1において点線で囲まれた部分の拡大図を示す。図1に示されるように、本発明の配線基板10は、デバイス領域Dと、周辺領域Pと、絶縁境界領域Bとを備える。デバイス領域Dには、金属層で構成される主配線パターンが絶縁層中に埋設されている。周辺領域Pは、デバイス領域Dの周りを取り囲む領域である。周辺領域Pには、主配線パターンと電気的に独立した金属層で構成されるダミー配線パターンが絶縁層中に埋設されている。絶縁境界領域Bは、デバイス領域Dと周辺領域Pとの間に介在し、絶縁層で構成される、金属層が存在しない領域である。図1及び2Aに示されるように、絶縁境界領域Bは、平面視した場合に、デバイス領域Dの外縁の少なくとも1辺の内接線Iと平行に、ダミー配線パターンを構成する金属層と絶縁境界領域Bを構成する絶縁層とを交互に横断する仮想直線Lを引くことが可能な、曲がりくねった形状を有している。そして、デバイス領域Dは、平面視した場合に、仮想直線Lから絶縁境界領域Bを隔てて完全に離れている。このように、トリミングされるべき配線基板10において、デバイス領域Dとその周りを取り囲む周辺領域Pとの間に、上記所定の仮想直線Lを引くことが可能な曲がりくねった形状を有する絶縁境界領域Bをトリミング用に介在させることにより、トリミング時及びその後における機械強度、耐水性、耐湿性及び製品歩留まりを向上させることができる。なお、内接線Iと仮想直線Lとは幾何学的に平行(完全な平行)であることが好ましいが、本発明の目的を達する範囲内で実質的に平行(略平行)であれば足りる。
本発明の配線基板10は、配線層及び絶縁層が多層化された多層配線板であってもよい。すなわち、本発明の好ましい態様によれば、上述した配線基板10を含む多層配線板が提供される。かかる多層配線板は、例えば、キャリア付金属箔の表面に、上述したビルドアップ法により配線層と絶縁層とを交互に積層してビルドアップ層を形成した後、キャリア付金属箔を剥離除去することにより好ましく製造することができる。このとき、上記所定のデバイス領域D、周辺領域P、及び絶縁境界領域Bが、多層化された配線層及び絶縁層のいずれかの層又は全ての層により構成されるのが好ましい。
キャリア上に剥離層(アモルファスカーボン層)及び金属層(銅層)がスパッタリングにより成膜されたキャリア付金属箔を用意した。このキャリア付金属箔の銅層表面に配線層及び絶縁層を積層して、配線基板を作製した。具体的な手順は以下のとおりである。
キャリアとしての350mm×350mmのサイズで厚さ1.1mmのガラスシート(材質:ソーダライムガラス)上に、アモルファスカーボン層(厚さ6nm)及び銅層(厚さ300nm)がスパッタリングにより成膜されたキャリア付金属箔を用意した。
キャリア付金属箔の銅層側の表面に対してパターニングを施すことにより、主配線パターン及びダミー配線パターンを含む配線層を形成した。具体的には、まず、キャリア付金属箔の銅層側の表面に感光性ドライフィルムを貼り付け、露光及び現像を行い、所定パターンのフォトレジスト層を形成した。次いで、銅層の露出表面(すなわちフォトレジスト層でマスキングされていない部分)にパターン電解銅めっきを行い、電解銅めっき層を形成した後、フォトレジスト層を剥離した。こうすることで、銅層及び電解銅めっき層を主配線パターン及びダミー配線パターン状に残す一方、これらの配線パターンを形成しない部分の銅層を露出させた。その後、露出した銅層の不要部分をエッチング液で除去することにより、主配線パターン及びダミー配線パターンが互いに電気的に独立した配線層を形成した。さらに、キャリア付金属箔の配線層側に、絶縁樹脂材料(感光性絶縁材料、昭和電工マテリアルズ株式会社製AR-5100)を積層し、230℃で60分間の熱硬化処理を行うことにより、絶縁層を形成した。こうして、デバイス領域Dと、周辺領域Pと、図2Aに示されるような矩形波状の絶縁境界領域Bとを備えた配線基板を作製した。
図5に示されるように、絶縁境界領域Bが直線形状を有するように配線層及び絶縁層を形成したこと以外は、例1と同様にして配線基板の作製を行った。
例1及び2で作製された配線基板からキャリアを剥離除去した後、キャリアを剥離した側の配線基板表面の状態を観察した。キャリアの剥離は、配線基板のキャリアと反対側の表面に接着層を介して補強シート(プリプレグ、パナソニック株式会社製FR-4、厚さ200μm)を積層した後、キャリアを配線基板から手で引き剥がすことにより行った。
Claims (10)
- 金属層で構成される主配線パターンが絶縁層中に埋設されたデバイス領域と、
前記デバイス領域の周りを取り囲み、前記主配線パターンと電気的に独立した金属層で構成されるダミー配線パターンが絶縁層中に埋設された周辺領域と、
前記デバイス領域と前記周辺領域との間に介在し、絶縁層で構成される、金属層が存在しない絶縁境界領域と、
を備えた配線基板であって、
前記絶縁境界領域は、平面視した場合に、前記デバイス領域の外縁の少なくとも1辺の内接線と平行に、前記ダミー配線パターンを構成する金属層と前記絶縁境界領域を構成する絶縁層とを交互に横断する仮想直線を引くことが可能な、曲がりくねった形状を有しており、
前記デバイス領域は、平面視した場合に、前記仮想直線から前記絶縁境界領域を隔てて完全に離れている、配線基板。 - 前記絶縁境界領域は、平面視した場合に、前記デバイス領域の外縁の全ての辺について、それらの各辺の内接線と平行に、前記ダミー配線パターンを構成する金属層と前記絶縁境界領域を構成する絶縁層とを交互に横断する仮想直線を引くことが可能な、曲がりくねった形状を有しており、前記デバイス領域は、平面視した場合に、前記全ての辺についての仮想直線から前記絶縁境界領域を隔てて完全に離れている、請求項1に記載の配線基板。
- 前記曲がりくねった形状は、前記絶縁境界領域と接する前記周辺領域の外縁形状、及び/又は前記絶縁境界領域と接する前記デバイス領域の外縁形状が、くし形、曲線からなる波形、三角形、台形、紡錘形及びファスナー形からなる群から選択される少なくとも1種を含むように構成される、請求項1又は2に記載の配線基板。
- 前記曲がりくねった形状が、波状パターンを含む、請求項1~3のいずれか一項に記載の配線基板。
- 前記波状パターンが、正弦波、のこぎり波、矩形波、台形波及び三角波からなる群から選択される少なくとも1種の形状を含む、請求項4に記載の配線基板。
- 前記主配線パターンの金属層を構成する金属の線膨張係数が、前記絶縁境界領域の絶縁層を構成する樹脂の線膨張係数の0.10倍以上10倍以下である、請求項1~5のいずれか一項に記載の配線基板。
- 前記配線基板が、キャリア、及び前記キャリア上の剥離層を有しており、前記剥離層上に前記デバイス領域、前記周辺領域、及び前記絶縁境界領域を備えている、請求項1~6のいずれか一項に記載の配線基板。
- 前記キャリアがガラスキャリアである、請求項7に記載の配線基板。
- 請求項1~8のいずれか一項に記載の配線基板を含む、多層配線板。
- 請求項1~8のいずれか一項に記載の配線基板を用意する工程と、
前記配線基板を前記仮想直線に沿って切断し、前記周辺領域を除去する工程と、
を含む、配線基板のトリミング方法。
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CN202180085992.0A CN116635979A (zh) | 2020-12-23 | 2021-12-10 | 布线基板和其裁切方法、以及多层布线板 |
JP2022572142A JPWO2022138238A1 (ja) | 2020-12-23 | 2021-12-10 | |
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