WO2018199003A1 - 支持体及びそれを用いた半導体素子実装基板の製造方法 - Google Patents
支持体及びそれを用いた半導体素子実装基板の製造方法 Download PDFInfo
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- WO2018199003A1 WO2018199003A1 PCT/JP2018/016410 JP2018016410W WO2018199003A1 WO 2018199003 A1 WO2018199003 A1 WO 2018199003A1 JP 2018016410 W JP2018016410 W JP 2018016410W WO 2018199003 A1 WO2018199003 A1 WO 2018199003A1
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Definitions
- the present invention relates to a support capable of improving the handling of a substrate when mounting a semiconductor element, and a method for manufacturing a semiconductor element mounting substrate using the same.
- a printed wiring board and a package substrate for mounting a semiconductor element are manufactured by laminating a layer to be a circuit pattern (hereinafter also simply referred to as “wiring conductor”) and an insulating material on a supporting substrate.
- a pattern electrolytic copper plating is performed using a support substrate for circuit formation in which a first insulating resin is provided on a carrier foil surface of an ultrathin copper foil with a carrier foil.
- a method of forming a first wiring conductor, laminating a second insulating resin, and then forming a second wiring conductor see, for example, Patent Document 1).
- a package substrate for mounting a semiconductor element has been thinned, and a three-layer coreless substrate (ETS) having a thickness of about 90 ⁇ m has been mass-produced.
- ETS three-layer coreless substrate
- the thickness will be further reduced, and it is expected that a substrate having a thickness of about 60 ⁇ m will be distributed within a few years.
- the handling property is also deteriorated, which makes it difficult to mount the semiconductor element on the substrate.
- an object of the present invention is to provide a support that can improve the handling of a package substrate and facilitate mounting of a semiconductor element. Furthermore, it aims at providing the manufacturing method of the semiconductor element mounting board
- the present inventors have found that the above problem can be solved by a support including a heat-resistant film layer and a resin layer, and the resin layer is in a semi-cured state (B stage), thereby completing the present invention. I let you.
- the present invention is as follows.
- a support including a heat-resistant film layer and a resin layer, The heat-resistant film layer is laminated on at least one surface (first surface) of the resin layer, The support body whose said resin layer is a semi-hardened state (B stage).
- B stage The support according to [1], wherein a copper foil is further laminated on a surface (second surface) opposite to the surface on which the heat-resistant film layer of the resin layer is laminated.
- the said heat-resistant film layer is a support body as described in said [1] or [2] containing 1 or more types of resin selected from the group which consists of a polyimide resin, a polyamideimide resin, a nylon resin, and a fluorine resin.
- the heat-resistant film layer is a heat-resistant film layer with an adhesive layer, and the adhesive layer is selected from the group consisting of a phenol resin, an epoxy resin, a cyanate resin, a maleimide resin, an isocyanate resin, a benzocyclobutene resin, and a vinyl resin.
- thermosetting resin includes one or more resins selected from the group consisting of phenol resins, epoxy resins, cyanate resins, maleimide resins, bismaleimide triazine resins, isocyanate resins, benzocyclobutene resins, and vinyl resins, The support according to [6].
- [10] The method for manufacturing a semiconductor element mounting substrate according to [9], including the following steps.
- (A) The process of forming the support substrate for circuit formation which contains a 1st insulating resin layer, a peeling layer, and copper foil in this order
- (b) On the said copper foil of the said support substrate for circuit formation, A step of forming a first wiring conductor
- (c) a step of placing a second insulating resin layer in contact with the first wiring conductor and laminating the second insulating resin layer by heating and pressing
- (d) ) A non-through hole reaching the first wiring conductor is formed in the second insulating resin layer, and an inner wall of the non-through hole is connected by electrolytic copper plating and / or electroless copper plating to form a second wiring
- a step of forming a conductor ;
- (e) a step of peeling the first insulating resin layer from the circuit forming substrate on which the first and second wiring conductors are formed; and (f) the peeling layer
- the insulating resin layer laminating step and the wiring conductor forming step are repeatedly performed on the circuit forming substrate on which the first and second wiring conductors are formed.
- the method for manufacturing a semiconductor element mounting substrate according to [10] further including a step of forming an up structure.
- the method for manufacturing a semiconductor element mounting substrate according to [10] or [11] further including a step of forming a solder resist layer between the step (f) and the step (g).
- the method for manufacturing a semiconductor element mounting substrate according to [12] further including a step of forming a gold plating layer after the step of forming the solder resist layer.
- [16] The method for manufacturing a semiconductor element mounting substrate according to [9], including the following steps.
- A) The process of forming the support substrate for circuit formation which contains a 1st insulating resin layer, a peeling layer, and copper foil in this order
- a step of forming a first wiring conductor (c) a step of placing a second insulating resin layer in contact with the first wiring conductor and laminating the second insulating resin layer by heating and pressing (d) )
- a non-through hole reaching the first wiring conductor is formed in the second insulating resin layer, and an inner wall of the non-through hole is connected by electrolytic copper plating and / or electroless copper plating to form a second wiring
- a step of forming a conductor (j) a step of pressing and laminating the support on a circuit forming substrate on which the first and second wiring conductors are formed; (k) from a circuit forming substrate on which the support is laminated; (1) peeling the first
- the insulating resin layer laminating step and the wiring conductor forming step are repeatedly performed on the circuit forming substrate on which the first and second wiring conductors are formed.
- the method for manufacturing a semiconductor element mounting substrate according to [16] further including a step of forming an up structure.
- the method for manufacturing a semiconductor element mounting substrate according to [16] or [17] further including a step of forming a solder resist layer between the step (l) and the step (h).
- the method for manufacturing a semiconductor element mounting substrate according to [18] further including a step of forming a gold plating layer after the step of forming the solder resist layer.
- the handling property of the package substrate for mounting the semiconductor element is improved, and the mounting of the semiconductor element on the substrate and the application of the solder resist are facilitated.
- FIG. 3 is a diagram (FIGS. 1A to 1D) schematically showing a manufacturing method of the first embodiment.
- FIG. 2 is a diagram (FIGS. 1E to 1H) schematically showing the manufacturing method of the first embodiment.
- FIG. 2 is a diagram (FIGS. 1I to 1K) schematically showing the manufacturing method of the first embodiment.
- FIG. 3 is a diagram (FIGS. 2A to 2D) schematically showing a manufacturing method of Embodiment 2.
- the support in this embodiment is A support including a heat-resistant film layer and a resin layer, The heat-resistant film layer is laminated on at least one surface (first surface) of the resin layer, The resin layer is in a semi-cured state (B stage).
- the resin layer is not particularly limited, and the same resin layer as the first and second insulating resin layers described later can be used. Among them, the glass cloth is heated from the viewpoint of the heat resistance and dimensional stability of the substrate. It is preferable to include a prepreg impregnated with a curable resin.
- the glass cloth is not particularly limited, and examples thereof include glass fiber and plain glass cloth. These glass cloths may be used alone or in combination of two or more.
- the thermosetting resin include phenol resin, epoxy resin, cyanate resin, maleimide resin, bismaleimide triazine resin (also referred to as “BT resin”), isocyanate resin, benzocyclobutene resin, and vinyl resin. These thermosetting resins may be used alone or in combination of two or more. Among these thermosetting resins, bismaleimide triazine resin, epoxy resin, cyanate resin and maleimide resin are preferable from the viewpoint of heat resistance and dimensional stability of the substrate, and bismaleimide triazine resin is more preferable. Specific examples of the phenol resin, epoxy resin, cyanate resin, maleimide resin, isocyanate resin, benzocyclobutene resin, and vinyl resin are as described in the thermosetting resin used in the resin composition of the insulating material described later. .
- the degree of curing of the resin layer is a semi-cured state (B stage).
- B stage The degree of curing of the resin layer is a semi-cured state.
- the followability of the support with respect to the substrate for mounting the semiconductor element is improved, and at the same time, the support is easily peeled off by physical force after mounting the semiconductor element.
- a commercially available product can be used as the prepreg, for example, GHPL-830NS (product name) manufactured by Mitsubishi Gas Chemical Co., Ltd. can be used.
- the heat-resistant film layer is laminated
- the heat-resistant film layer is not particularly limited as long as it is a film made of a heat-resistant resin, and examples of the heat-resistant resin include a polyimide resin, a polyamideimide resin, a nylon resin, and a fluorine resin. These heat resistant resins may be used alone or in combination of two or more. Among these heat resistant resins, polyimide resins and fluorine resins are preferable from the viewpoint of heat resistance.
- the polyimide resin is not particularly limited, and examples thereof include polyamideimide, polypyromellitdiimide, bismaleimide, and polyetherimide. These polyimide resins may be used alone or in combination of two or more.
- the polyamideimide resin is not particularly limited, and for example, trimellitic anhydride, benzophenonetetracarboxylic anhydride and vitorylene diisocyanate in a solvent of N-methyl-2-pyrrolidone and / or N, N-dimethylacetamide.
- a resin obtained by heating at a temperature such as N-methyl-2-pyrrolidone and / or N, N-dimethylacetamide
- a resin obtained by heating at a temperature trimellitic anhydride, diphenylmethane diisocyanate, and carboxyl group-terminated (meth) acrylonitrile-butadiene rubber What is obtained by heating with is mentioned.
- These polyamideimide resins may be used alone or in combination of two or more.
- the nylon resin is not particularly limited, and examples thereof include nylon 6, nylon 6,6 and aramid. These nylon resins may be used alone or in combination of two or more.
- the fluororesin is not particularly limited, and examples thereof include polytetrafluoroethylene, polyvinylidene fluoride, and polychlorotrifluoroethylene. These fluororesins may be used alone or in combination of two or more.
- the heat resistant film layer may be a heat resistant film layer with an adhesive layer.
- the adhesive layer surface is disposed so as to be in contact with the insulating resin layer.
- the resin constituting the adhesive layer is not particularly limited, and examples thereof include phenol resins, epoxy resins, cyanate resins, maleimide resins, isocyanate resins, benzocyclobutene resins, bismaleimide triazine resins, and vinyl resins.
- One type of resin constituting these adhesive layers may be used alone, or two or more types may be mixed and used.
- thermosetting resin used in the resin composition of the insulating material described later.
- a commercial item can also be used as a heat resistant film with an adhesive layer, for example, CISV (product name) manufactured by Nikkan Kogyo Co., Ltd. can be used.
- copper foil As for the support body in this embodiment, copper foil may be further laminated
- the thickness of the support is not particularly limited, but is preferably 10 ⁇ m or more, more preferably 50 ⁇ m or more, and further preferably 100 ⁇ m or more from the viewpoint of improving the handling properties of the substrate.
- the upper limit of the thickness of the support is not particularly limited, but it is preferably 400 ⁇ m or less, more preferably 300 ⁇ m or less, and even more preferably 200 ⁇ m or less because it tends to be inferior in transportability or mass productivity if it is too thick. It is.
- the surface area of the heat-resistant film layer may be smaller than the surface area of the resin layer.
- the adhesive force between the support and the circuit forming substrate can be increased, and the laminated substrate can be easily cut into a package size before mounting the semiconductor element. Has the advantage of becoming.
- the method for producing the support is not particularly limited.
- a heat-resistant film layer is disposed on at least one surface of the resin layer, and a copper foil is provided on the surface opposite to the surface on which the heat-resistant film layer is laminated as necessary
- the manufacturing method of the semiconductor element mounting substrate in the present embodiment is a manufacturing method using the support, and the support is pressed and laminated on the circuit forming substrate on which the first and second wiring conductors are formed. And a step of mounting a semiconductor element on the wiring conductor. Since the manufacturing method of the semiconductor element mounting substrate of this embodiment can improve the handling property of the substrate by using the support, even when the substrate is extremely thin, the mounting of the semiconductor element and the solder resist Application becomes easy. Hereinafter, a more specific manufacturing method will be described.
- the manufacturing method of the semiconductor element mounting substrate in the first embodiment (Embodiment 1) for carrying out the present invention includes the following steps.
- a step of forming a first wiring conductor (c) a step of placing a second insulating resin layer in contact with the first wiring conductor and laminating the second insulating resin layer by heating and pressing (d) )
- a non-through hole reaching the first wiring conductor is formed in the second insulating resin layer, and an inner wall of the non-through hole is connected by electrolytic copper plating and / or electroless copper plating to form a second wiring
- Step (a) in the present embodiment is a step of forming a circuit-forming support substrate that includes the first insulating resin layer, the release layer, and the copper foil in this order.
- the peeling layer and the copper foil may be disposed only on one side, but it is preferable that these layers are disposed on both sides of the first insulating resin layer.
- the circuit-forming support substrate in the present embodiment is preferably a two-layer core substrate with a release layer.
- the configuration of the circuit-forming support substrate (two-layer core substrate with a release layer) 1 will be described with reference to FIG.
- the circuit-forming support substrate 1 includes a release layer 3 and a copper foil 4 on both sides of a first insulating resin layer (for example, prepreg) 2. They are provided in order from the surface side.
- the support substrate for circuit formation it can be formed by forming a release layer on a copper foil and disposing it on the first insulating resin layer, but is not limited to this forming method. If it is the method by which a peeling layer and copper foil are laminated
- a copper foil having a fixed thickness on which a release layer is formed (hereinafter also referred to as “copper foil with a release layer”) is disposed so that the release layer surface is in contact with a first insulating resin layer such as a prepreg.
- the release layer and the copper foil can be formed on the first insulating resin layer by heating and pressurizing and laminating.
- the first insulating resin layer, the release layer, and the copper foil are applied by performing a known process such as an etching process so that the copper foil has a desired thickness as needed.
- the release layer-attached copper foil is not particularly limited.
- a copper foil having a release layer formed on a copper foil having a thickness of 1 ⁇ m to 20 ⁇ m can be used.
- a release layer may be formed on the first insulating resin layer, and then a copper foil may be disposed to form a circuit-forming support substrate.
- the lamination method and conditions are not particularly limited, but for example, for circuit formation by performing vacuum pressing under conditions of a temperature of 220 ⁇ 2 ° C., a pressure of 5 ⁇ 0.2 MPa, and a holding time of 60 minutes.
- a support substrate can be formed.
- the first insulating resin layer in the step (a) is not particularly limited.
- a base material such as a glass cloth is impregnated with an insulating resin material (insulating material) such as a thermosetting resin.
- insulating material such as a thermosetting resin.
- a prepreg or an insulating film material can be used.
- the “prepreg” is obtained by impregnating or coating a base material with an insulating material such as a resin composition. It does not specifically limit as a base material, The well-known thing used for the laminated board for various electrical insulation materials can be used suitably.
- a material which comprises a base material the inorganic fiber of E glass, D glass, S glass, and Q glass; The organic fiber of a polyimide, polyester, and tetrafluoro erylene; and those mixtures are mentioned, for example.
- a base material is not specifically limited, For example, what has the shape of a woven fabric, a nonwoven fabric, a robink, a chopped strand mat, and a surfacing mat can be used suitably.
- the material and shape of the base material are selected depending on the intended use and performance of the molded article, and may be used alone or in combination of two or more types as required.
- the thickness of the substrate is not particularly limited, but a substrate having a thickness of usually 0.02 to 0.50 mm can be used.
- a substrate having a thickness of usually 0.02 to 0.50 mm can be used as the base material.
- these base materials are from the viewpoint of heat resistance, moisture resistance, and workability. Is preferred.
- the insulating material is not particularly limited, and a known resin composition used as an insulating material for a printed wiring board can be appropriately selected and used.
- a thermosetting resin having good heat resistance and chemical resistance can be used as a base.
- the thermosetting resin is not particularly limited, and examples thereof include phenol resin, epoxy resin, cyanate resin, maleimide resin, bismaleimide triazine resin, isocyanate resin, benzocyclobutene resin, and vinyl resin. These thermosetting resins may be used alone or in combination of two or more.
- the phenol resin is not particularly limited, and generally known resins can be used as long as they are phenol resins having two or more hydroxy groups in one molecule.
- phenol resins having two or more hydroxy groups in one molecule.
- bisphenol A type phenol resin bisphenol E type phenol resin, bisphenol F type phenol resin, bisphenol S type phenol resin, phenol novolac resin, bisphenol A novolac type phenol resin, glycidyl ester type phenol resin, aralkyl novolac type phenol resin, biphenyl Aralkyl type phenolic resin, cresol novolac type phenolic resin, polyfunctional phenolic resin, naphthol resin, naphthol novolak resin, polyfunctional naphthol resin, anthracene type phenolic resin, naphthalene skeleton modified novolak type phenolic resin, phenolaralkyl type phenolic resin, naphthol aralkyl type Phenol resin, dicyclopentadiene type
- thermosetting resins epoxy resins are excellent in heat resistance, chemical resistance and electrical properties, and are relatively inexpensive, and therefore can be suitably used as insulating materials.
- the epoxy resin is not particularly limited.
- bisphenol A type epoxy resin bisphenol F type epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, phenol novolac type epoxy resin, cresol.
- Novolac type epoxy resin bisphenol A novolac type epoxy resin, diglycidyl etherified product of biphenol, diglycidyl etherified product of naphthalenediol, diglycidyl etherified product of phenol, diglycidyl etherified product of alcohol, and these Examples include alkyl-substituted products, halides, and hydrogenated products.
- These epoxy resins may be used alone or in combination of two or more.
- the curing agent used together with the epoxy resin can be used without limitation as long as it cures the epoxy resin.
- polyfunctional phenols, polyfunctional alcohols, amines, imidazole compounds, acid anhydrides, organic Examples thereof include phosphorus compounds and halides thereof.
- These epoxy resin curing agents may be used alone or in combination of two or more.
- the cyanate resin is a resin that generates a cured product having a triazine ring as a repeating unit by heating, and the cured product has excellent dielectric properties. For this reason, it is suitable especially when high frequency characteristics are required.
- the cyanate resin is not particularly limited, and for example, 2,2-bis (4-cyanatophenyl) propane, bis (4-cyanatophenyl) ethane, 2,2-bis (3,5dimethyl-4-silane) Anatophenyl) methane, 2,2- (4-cyanatophenyl) -1,1,1,3,3,3-hexafluoropropane, ⁇ , ⁇ '-bis (4-cyanatophenyl) -m-diisopropyl Examples include cyanate esterified products of benzene, phenol novolac and alkylphenol novolac.
- cyanate resins may be used alone or in combination of two or more.
- the cyanate ester compound may be partially oligomerized in advance to a trimer or a pentamer.
- 2,2-bis (4-cyanatophenyl) propane is preferable because it has a particularly good balance between the dielectric properties and curability of the cured product and is inexpensive.
- a curing catalyst or a curing accelerator can be used in combination with the cyanate resin.
- the curing catalyst for example, metals such as manganese, iron, cobalt, nickel, copper, and zinc can be used.
- organometallic salts such as 2-ethylhexanoate and octylate, and acetylacetone complexes.
- organometallic complexes such as These curing catalysts may be used alone or in combination of two or more.
- Phenols are preferably used as curing accelerators, and monofunctional phenols such as nonylphenol and paracumylphenol, bifunctional phenols such as bisphenol A, bisphenol F, and bisphenol S, or phenol novolacs, cresol novolacs, and the like. Functional phenol or the like can be used.
- monofunctional phenols such as nonylphenol and paracumylphenol
- bifunctional phenols such as bisphenol A, bisphenol F, and bisphenol S
- phenol novolacs such as cresol novolacs, and the like.
- Functional phenol or the like can be used.
- These curing accelerators may be used alone or in combination of two or more.
- maleimide compound generally known compounds can be used as long as they have one or more maleimide groups in one molecule.
- the isocyanate resin is not particularly limited, and examples thereof include an isocyanate resin obtained by a dehydrohalogenation reaction between phenols and a halogenated cyanide.
- examples of the isocyanate resin include 4,4'-diphenylmethane diisocyanate MDI, polymethylene polyphenyl polyisocyanate, tolylene diisocyanate, and hexamethylene diisocyanate. These isocyanate resins may be used alone or in combination of two or more.
- the benzocyclobutene resin is not particularly limited as long as it contains a cyclobutene skeleton.
- divinylsiloxane-bisbenzocyclobutene manufactured by Dow Chemical Co.
- These benzocyclobutene resins may be used alone or in combination of two or more.
- the vinyl resin is not particularly limited as long as it is a polymer or copolymer of vinyl monomers.
- the vinyl monomer is not particularly limited, and examples thereof include (meth) acrylic acid ester derivatives, vinyl ester derivatives, maleic acid diester derivatives, (meth) acrylamide derivatives, styrene derivatives, vinyl ether derivatives, vinyl ketone derivatives, olefin derivatives, maleimide derivatives, (Meth) acrylonitrile is mentioned. These vinyl resins may be used alone or in combination of two or more.
- the resin composition used as the insulating material can be blended with a thermoplastic resin in consideration of dielectric properties, impact resistance, film processability, and the like.
- the thermoplastic resin is not particularly limited, and examples thereof include fluororesin, polyphenylene ether, modified polyphenylene ether, polyphenylene sulfide, polycarbonate, polyetherimide, polyetheretherketone, poly (meth) acrylate, polyamide, polyamideimide, and polybutadiene. Can be mentioned. These thermoplastic resins may be used alone or in combination of two or more.
- the fluororesin is not particularly limited, and examples thereof include polytetrafluoroethylene, polychlorotrifluoroethylene, polyvinylidene fluoride, and polyvinyl fluoride. These fluororesins may be used alone or in combination of two or more.
- thermoplastic resins it is useful to blend and use polyphenylene ether and / or modified polyphenylene ether from the viewpoint that the dielectric properties of the cured product can be improved.
- the polyphenylene ether and the modified polyphenylene ether are not particularly limited.
- polystyrene Alloyed polymers of the following: Alloyed polymers of poly (2,6dimethyl-1,4-phenylene) ether and styrene-butadiene copolymers, poly (2,6-dimethyl-1,4-phenylene) ether and styrene-anhydrous maleic Alloyed polymer of acid copolymer, alloyed polymer of poly (3,6-dimethyl-1,4-phenylene) ether and polyamide, poly (2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene- Examples include alloyed polymers with (meth) acrylonitrile copolymers.These polyphenylene ethers and modified polyphenylene ethers may be used alone or in combination of two or more.
- functional groups such as amine groups, epoxy groups, carboxylic groups, and styryl groups are introduced at the ends of the polymer chains, or amine groups and epoxy groups are added to the side chains of the polymer chains
- Functional groups such as a group, a carboxyl group, a styryl group, and a methacryl group may be introduced.
- Polyphenylene sulfide is a polymer in which an aromatic ring is a sulfide bond, and examples thereof include branched or straight-chain polyphenylene sulfide and copolymers thereof. For example, it has paraphenylene sulfide, metaphenylene sulfide and their polymers, and ether units, sulfone units, biphenyl units, naphthyl units, substituted phenyl sulfide units, trifunctional phenyl sulfide units, etc. that can be copolymerized with these in the molecule. A copolymer is mentioned. These polyphenylene sulfides may be used alone or in combination of two or more.
- the polycarbonate is not particularly limited, and examples thereof include brominated polycarbonate oligomers.
- the molecular weight of the brominated polycarbonate oligomer is not particularly limited, but those having a weight average molecular weight of 500 to 3500 are preferred.
- the polyetherimide is not particularly limited.
- These polyetherimides may be used alone or in combination of two or more.
- a commercially available product may be used as the polyetherimide, and examples thereof include “Ultem (registered trademark)” 1000, 5000 and 6000 series manufactured by GE Plastics.
- the polyether ether ketone is not particularly limited, and examples thereof include a copolymer of 4,4'-difluorobenzophenone and hydroquinone. These polyether ether ketones may be used alone or in combination of two or more.
- the poly (meth) acrylate is not particularly limited, and examples thereof include tris (2- (meth) acryloyloxyethyl) isocyanurate. These poly (meth) acrylates may be used alone or in combination of two or more.
- the polyamide is not particularly limited, and examples thereof include polyamide 12, polyamide 11, polyamide 6, polyamide 6,6, and polyamide 6/12 copolymer. These polyamides may be used alone or in combination of two or more.
- polyamideimide resin is useful from the viewpoint of excellent moisture resistance and a good adhesive to metal.
- the raw material of the polyamideimide resin is not particularly limited, and examples of the acidic component include trimellitic anhydride and trimellitic anhydride monochloride.
- the amine component is not particularly limited, and metaphenylenediamine, paraphenylenediamine, 4,4′-diaminodiphenyl ether, 4,4′-diaminodiphenylmethane, bis [4- (aminophenoxy) phenyl] sulfone, 2,2 ′ -Bis [4- (4-aminophenoxy) phenyl] propane.
- the polyamide-imide resin may be modified with siloxane in order to improve the drying property.
- siloxane diamine can be used as an amino component.
- Polyamideimide resin may be used individually by 1 type, and may mix and use 2 or more types.
- the polybutadiene is not particularly limited, and examples thereof include 1,4-polybutadiene, 1,2-polybutadiene, terminal (meth) acrylate-modified polybutadiene, and terminal urethane methacrylate-modified polybutadiene. These polybutadienes may be used alone or in combination of two or more.
- thermoplastic resin has been described as an insulating material mainly used for a prepreg, but these thermoplastic resins are not limited to use as a prepreg.
- thermoplastic resin film material
- thermoplastic resin film material
- An inorganic filler may be mixed in the resin composition used as the insulating material.
- the inorganic filler is not particularly limited, and examples thereof include alumina, aluminum hydroxide, magnesium hydroxide, clay, talc, antimony trioxide, antimony pentoxide, zinc oxide, fused silica, glass powder, quartz powder, and shirasu balloon. . These inorganic fillers may be used alone or in combination of two or more.
- the resin composition used as the insulating material may contain an organic solvent.
- the organic solvent is not particularly limited, and examples thereof include aromatic hydrocarbon solvents such as benzene, toluene, xylene, and trimethylbenzene; ketone solvents such as acetone, methyl ethyl ketone, and methyl inobutyl ketone; ethers such as tetrahydrofuran.
- solvents can be used alone or in admixture as desired.
- amount of solvent in the varnish when preparing the prepreg is preferably in the range of 40 to 80% by mass relative to the entire resin composition.
- the viscosity of the varnish is preferably in the range of 20 to 100 cP (20 to 100 mPa ⁇ s).
- the resin composition used as an insulating material may contain a flame retardant.
- the flame retardant is not particularly limited, and examples thereof include bromine compounds such as decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, and tribromophenol, triphenyl phosphate, trixylel phosphate, cresyl diphenyl phosphate.
- Phosphorus compounds such as magnesium hydroxide, metal hydroxides such as aluminum hydroxide, red phosphorus and modified products thereof, antimony compounds such as antimony trioxide and antimony pentoxide, and triazine compounds such as melamine, cyanuric acid and melamine cyanurate
- antimony compounds such as antimony trioxide and antimony pentoxide
- triazine compounds such as melamine, cyanuric acid and melamine cyanurate
- flame retardants may be used alone or in combination of two or more.
- additives and fillers may be further added. These additives and fillers may be used alone or in combination of two or more.
- the prepreg includes, for example, a resin composition (including a varnish) so that the amount of the resin composition attached to the substrate is 20 to 90% by mass in terms of the resin content in the dried prepreg. After impregnating or coating the substrate, it can be obtained by heating and drying at a temperature of 100 to 200 ° C. for 1 to 30 minutes to obtain a prepreg in a semi-cured state (B stage state).
- a commercially available product can be used, for example, GHPL-830NS (product name) manufactured by Mitsubishi Gas Chemical Co., Ltd. can be used.
- step (a) in this embodiment for example, 1 to 20 sheets of this prepreg are stacked so as to have a desired insulating resin layer thickness, and a copper foil such as a release layer-attached copper foil is formed on both surfaces thereof.
- Heating and pressurization can be performed in a configuration in which the foils are in contact with each other.
- a general technique of copper-clad laminate can be applied. For example, using a multistage press, a multistage vacuum press, continuous molding, an autoclave molding machine, etc., the temperature is usually 100 to 250 ° C., and the pressure is 2 to 100 kg.
- the first insulating resin layer a metal foil-clad laminate that is commercially available as a copper clad laminate (CCL) or the like obtained by removing the copper foil from the CCL is used. Can do.
- the thickness of the first insulating resin layer is not particularly limited because it is appropriately set as desired, but can be 0.02 mm to 2.0 mm, preferably 0.03 mm to 0.2 mm, and 0.04 mm. More preferable is 0.15 mm.
- the circuit-forming support substrate in the present embodiment includes a release layer.
- the release layer preferably contains at least a silicon compound.
- the “peeling layer” preferably contains at least a silicon compound, is located between the first insulating resin layer and the copper foil, and has a peel strength (x between at least the first insulating resin layer and the peeling layer). ) Means a layer having a relationship of x ⁇ y with respect to the peel strength (y) between the copper foil and the first wiring conductor.
- the release layer can contain a resin composition as required in addition to the silicon compound.
- the said thermosetting resin can be used, for example.
- the peel strength (z) between the release layer and the copper foil preferably has a relationship of x ⁇ z in relation to the peel strength (x).
- the silicon compound is not particularly limited, and for example, a silane compound represented by the following formula (1), a hydrolysis product thereof or a condensation product of the hydrolysis product (hereinafter collectively referred to as “silane compound”). May be used). These silane compounds may be used alone or in combination of two or more.
- the release layer can be formed, for example, by applying a silicon compound composed of a single silane compound or a combination of a plurality of silane compounds on a copper foil or an ultrathin copper foil.
- the means to provide a silicon compound is not specifically limited, For example, well-known means, such as application
- R 1 is an alkoxy group or a halogen atom
- R 2 is a hydrocarbon group selected from the group consisting of an alkyl group, a cycloalkyl group and an aryl group
- R 3 and R 4 are each independently A halogen atom, an alkoxy group, or a hydrocarbon group selected from the group consisting of an alkyl group, a cycloalkyl group, and an aryl group.
- one or more hydrogen atoms may be substituted with a halogen atom.
- R 1 to R 4 may independently be the same or different.
- the silane compound represented by the formula (1) preferably has at least one alkoxy group from the viewpoint of preventing the adhesiveness with the copper foil from being excessively lowered. From the same viewpoint, the silane compound represented by the formula (1) preferably has at least one hydrocarbon group selected from the group consisting of an alkyl group, a cycloalkyl group, and an aryl group.
- the silane compound represented by the formula (1) is a carbonization selected from the group consisting of three alkoxy groups, alkyl groups, cycloalkyl groups, and aryl groups. It preferably has one hydrogen group.
- R 3 and R 4 are alkoxy groups.
- the alkoxy group is not particularly limited, and examples thereof include linear, branched, or cyclic alkoxy groups having 1 to 20, preferably 1 to 10, and more preferably 1 to 5 carbon atoms.
- alkoxy groups include methoxy, ethoxy, n- or iso-propoxy, n-, iso- or tert-butoxy, n-, iso- or neo-pentoxy, n-hexoxy, cyclohexiso
- Examples thereof include a xy group, an n-heptoxy group, and an n-octoxy group.
- halogen atom examples include a fluorine atom, a chlorine atom, a bromine atom and an iodine atom.
- the alkyl group is not particularly limited, and examples thereof include linear or branched alkyl groups having 1 to 20, preferably 1 to 10, and more preferably 1 to 5 carbon atoms.
- Examples of the alkyl group include a methyl group, ethyl group, n- or iso-propyl group, n-, iso- or tert-butyl group, n-, iso- or neo-pentyl group, n-hexyl group, n- Examples include an octyl group and an n-decyl group.
- the cycloalkyl group is not particularly limited, and examples thereof include a cycloalkyl group having 3 to 10 carbon atoms, preferably 5 to 7 carbon atoms.
- Examples of the cycloalkyl group include a cyclopropyl group, a cyclobutyl group, a cyclopentyl group, a cyclohexyl group, a cycloheptyl group, and a cyclooctyl group.
- the aryl group is not particularly limited, and examples thereof include an aryl group having 6 to 20 carbon atoms, preferably 6 to 14 carbon atoms.
- Examples of the aryl group include a phenyl group substituted with an alkyl group such as a phenyl group, a tolyl group, and a xylyl group, a 1- or 2-naphthyl group, and an anthryl group.
- one or more hydrogen atoms may be substituted with a halogen atom, and may be substituted with, for example, a fluorine atom, a chlorine atom, or a bromine atom.
- silane compound examples are not particularly limited, but compounds other than the silicone compound are preferable.
- dimethyldimethoxysilane, n-propyltrimethoxysilane, phenyltrimethoxysilane, hexyltrimethoxysilane, methyltriethoxysilane, dimethyldiethoxysilane, (3, 3, 3- (Trifluoropropyl) trimethoxysilane and dimethyldichlorosilane are preferred, dimethyldimethoxysilane, n-propyltrimethoxysilane, methyltriethoxysilane, dimethyldiethoxysilane, (3,3,3-trifluoropropyl) trimethoxysilane, More preferred is dimethyldichlorosilane.
- a commercially available product may be used as such a silane compound used as a silicon compound and a release layer formed on a copper foil or an ultrathin copper foil.
- a commercially available product for example, a release layer containing at least one selected from the group consisting of dimethyldimethoxysilane, n-propyltrimethoxysilane, phenyltrimethoxysilane, and hexyltrimethoxysilane as a silicon compound is formed on a copper foil. What was formed can be used, for example, "PCS" (product name) by JX Nippon Mining & Metals Co., Ltd. is mentioned.
- the peel strength (x) between the release layer and the first insulating resin layer is not particularly limited, and in the manufacturing method of the present embodiment, the first insulating resin layer is formed in a step before the peeling step (e). From the viewpoint of physically peeling the first insulating resin layer in the peeling step (e) while preventing peeling, it is preferably 3 to 20 N ⁇ m, more preferably 5 to 15 N ⁇ m, and more preferably 8 to 12 N ⁇ m. m is more preferable. For example, when the peel strength (x) is within the above range, the first insulating resin layer is physically peeled by a human hand or the like in the peeling step (e) while being not peeled off during transport or processing. Can be easily peeled off.
- Difference (y ⁇ x) is, for example, preferably 50 N ⁇ m or more, more preferably 100 N ⁇ m or more, and further preferably 200 N ⁇ m or more.
- peel strength (x) and / or peel strength (y) for example, for the peel strength (x), the type of the silicon compound in the release layer and the coating amount of the silicon compound are adjusted, or the peel strength (y). Can be adjusted to the above range by adjusting the press conditions, plating thickness, material, and conditions in the roughening treatment.
- the thickness of the release layer is not particularly limited, but is preferably 5 nm to 100 nm, more preferably 10 nm to 80 nm, and still more preferably 20 nm to 60 nm.
- the copper foil is not particularly limited, but is usually an ultrathin copper foil having a thickness of 1 ⁇ m to 5 ⁇ m, preferably 2 ⁇ m to 4 ⁇ m, and more preferably 2.5 ⁇ m to 3.5 ⁇ m.
- the copper foil is not particularly limited, but the 10-point average roughness (Rzjis) shown in JIS B0601: 2001 is preferably 0.3 ⁇ m to 3.0 ⁇ m on both sides, more preferably 0.5 ⁇ m to 2.0 ⁇ m, More preferably, the thickness is 0.7 ⁇ m to 1.5 ⁇ m.
- a bumpy electrodeposit layer (sometimes referred to as “burnt plating”) can be formed, or roughened by oxidation treatment, reduction treatment, or etching.
- the production conditions of the copper foil are not particularly limited, and in the case of a copper sulfate bath, sulfuric acid 50-100 g / L, copper 30-100 g / L, liquid temperature 20-80 ° C., current density 0.5-100 A / dm 2 Conditions: In the case of a copper pyrophosphate bath, the following conditions are generally used: potassium pyrophosphate 100 to 700 g / L, copper 10 to 50 g / L, liquid temperature 30 to 60 ° C., pH 8 to 12, current density 0.5 to 10 A / dm 2. Often used. Various additives may be added to the copper bath in consideration of the physical properties and smoothness of copper.
- the copper foil can be formed using, for example, a peelable type or using a copper foil having a certain thickness.
- the peelable type copper foil is a copper foil having a carrier, and the carrier is, for example, a peelable copper foil.
- the carrier is peeled off from the copper foil in the step (a).
- an ultrathin copper foil is formed using a certain thickness of copper foil in the step (a)
- a peeling layer is formed on the copper foil having a certain thickness to obtain a copper foil with a peeling layer.
- the means for forming the release layer on the copper foil is not particularly limited.
- the release layer can be formed by applying the silicon compound to the copper foil by a known method such as coating.
- a commercial item can also be used, for example, using the above-mentioned "PCS" (product name) by JX Nippon Mining & Metals Co., Ltd. as a peeling layer layered copper foil.
- the thickness of the fixed thickness copper foil (that is, the copper foil portion of the peelable layer-attached copper foil) is not particularly limited, but a desired thickness (for example, 1 ⁇ m to 5 ⁇ m) by a thickness reducing means such as etching as necessary. From the viewpoint of removing unnecessary parts, it is preferably 1 ⁇ m or more, more preferably 1 ⁇ m to 20 ⁇ m. However, when the thickness of the copper foil having a certain thickness is 1 ⁇ m to 5 ⁇ m, the processing by the thickness reducing means may be unnecessary.
- the thickness reducing means a known method can be appropriately applied, and examples thereof include an etching process.
- the etching treatment is not particularly limited, and can be performed by etching using a perhydrosulfuric acid based soft etching solution, for example.
- a copper foil with a release layer in which the release layer is formed on a copper foil having a thickness of 1 ⁇ m to 20 ⁇ m is used. be able to.
- an ultrathin copper foil can be formed from a certain thickness of copper foil in the step (a).
- the manufacturing method of this embodiment is not limited to this aspect, for example, when a 12 ⁇ m copper foil is used, a release layer is formed by coating or the like, and then laminated and pressed with the first insulating resin layer
- a circuit-forming support substrate By performing soft etching of the copper foil and adjusting the thickness of the copper foil to, for example, 3 ⁇ m to obtain an ultrathin copper foil, a circuit-forming support substrate can be produced.
- the etching treatment is not particularly limited, and can be performed after heating and pressurizing the peel-off layer-attached copper foil to the first insulating resin layer.
- a rust prevention process can be given to the adhesion surface with the peeling layer of copper foil (rust prevention process layer is formed).
- the rust prevention treatment can be performed using any of nickel, tin, zinc, chromium, molybdenum, cobalt, or an alloy thereof.
- a thin film is formed on a copper foil by sputtering, electroplating or electroless plating, but electroplating is preferable from the viewpoint of cost.
- plating is performed using a chemical solution containing one or more metal salts selected from the group consisting of nickel, tin, zinc, chromium, morbden, and cobalt as the plating layer.
- a complexing agent such as citrate, tartrate or sulfamic acid may be added to the plating solution in a required amount.
- the plating solution is usually used in an acidic region and is plated at a temperature of room temperature to 80 ° C.
- the plating is appropriately selected from the range of a normal current density of 0.1 to 10 A / dm 2 and a normal time of 1 to 60 seconds, preferably 1 to 30 seconds.
- the amount of metal used for the rust prevention treatment varies depending on the type of metal and is not particularly limited, but a total of 10 to 2000 ⁇ g / dm 2 is preferable.
- the thickness of the rust-proofing layer if it is too thick, it may cause etching inhibition and deterioration of electrical characteristics, and if it is too thin, it may cause a decrease in peel strength with the resin.
- a chromate treatment layer is formed on the rust prevention treatment layer, it is useful because it can suppress a decrease in adhesive strength with the release layer. Specifically, it is performed using an aqueous solution containing hexavalent chromium ions.
- the chromate treatment is not particularly limited. For example, a simple dipping treatment is possible, but a cathode treatment is preferably performed. Cathodic treatment is performed under the conditions of sodium dichromate 0.1-50 g / L, pH 1-13, bath temperature 0-60 ° C., current density 0.1-5 A / dm 2 , current time 0.1-100 seconds. It is preferable. Instead of sodium dichromate, chromic acid or potassium dichromate can be used.
- a coupling agent is further adsorbed on the antirust treatment layer.
- the silane coupling agent is not particularly limited. For example, 3-glycidoxypropyltrimethoxysilane, 2- (3,4-epoxycyclohexyl) ethyltrimethoxysilane epoxy-functional silane, 3-aminopropyltrimethoxy Silane, N-2- (aminoethyl) -3-aminopropyltrimethoxysilane, N-2- (aminoethyl) -3-aminopropylmethyldimethoxysilane, amine functional silane, vinyltrimethoxysilane, vinylphenyltrimethoxy Silane, vinyltris (2-methoxyethoxy) silane olefin functional silane, 3- (meth) acryloxypropyltrimethoxysilane (meth) acrylic functional silane, 3-mercaptopropyltrimethoxysilane mer
- silane coupling agents may be used alone or in combination of two or more. These coupling agents are dissolved in a solvent such as water at a concentration of 0.1 to 15 g / L and applied to a metal foil at a temperature of room temperature to 50 ° C. or electrodeposited to be adsorbed. These silane coupling agents form a film by condensation bonding with a hydroxyl group of a rust-proof metal on the copper foil surface. After the silane coupling treatment, a stable bond is formed by heating, ultraviolet irradiation or the like. If heating, dry at a temperature of 80 to 200 ° C. for 2 to 60 seconds. In the case of ultraviolet irradiation, it is performed in the range of 200 to 400 nm and 200 to 2500 mJ / dm 2 .
- Step (b) is a step of forming a first wiring conductor on the copper foil of the circuit-forming support substrate.
- the first wiring conductor 5 is formed on the copper foil 4 of the circuit forming support substrate 1 as shown in FIG. 1C.
- the means for forming the first wiring conductor is not particularly limited.
- the first wiring conductor can be formed by the following steps.
- step (b) for example, a plating resist is laminated on the copper foil (step (b-1)), and a wiring circuit pattern is formed on the plating resist by photolithography (step (b-2)).
- a first wiring conductor is formed by pattern electrolytic copper plating on the copper foil in which a wiring circuit pattern is formed on the plating resist (step (b-3)), and the plating resist is removed (step) (B-4))
- the first wiring conductor can be formed on the copper foil.
- the plating resist laminated on the copper foil can be exposed and developed by photolithography to form a wiring circuit pattern on the plating resist.
- the first wiring conductor can be formed of plated copper by performing pattern electrolytic copper plating on the copper foil having the wiring circuit pattern formed on the plating resist. After forming the first wiring conductor, the plating resist is removed in step (b-4).
- the plating resist is not particularly limited, and for example, a known one such as a commercially available dry film resist can be appropriately selected and used.
- photolithography including exposure, development, and removal of the resist
- a well-known method can be used suitably.
- the pattern width of the first wiring conductor is not particularly limited, and the width can be appropriately selected according to the application.
- the width can be 5 to 100 ⁇ m, and preferably 10 to 30 ⁇ m. it can.
- Step (c) is a step of disposing a second insulating resin layer so as to be in contact with the first wiring conductor, and laminating the second insulating resin layer by heating and pressing.
- the step (c) may be a step in which a metal layer is further disposed on the second insulating resin layer, and the second insulating resin layer and the metal layer are laminated by heating and pressing.
- the second insulating resin layer 6 and the metal layer 7 can be laminated so as to be in contact with the first wiring conductor 5 as shown in FIG. 1D.
- FIG. 1D although the aspect which provided the metal layer is carried out, this invention is not limited to the said aspect.
- the same material (for example, prepreg) as the first insulating resin layer can be used.
- the thickness of the second insulating resin layer is not particularly limited because it is appropriately set as desired.
- the thickness can be 0.02 mm to 2.0 mm, and 0.03 mm to 0.2 mm. Is preferable, and 0.04 mm to 0.15 mm is more preferable.
- the thing similar to the said copper foil can be used, for example.
- the copper foil for example, an ultrathin copper foil with a carrier copper foil can be used.
- the carrier is peeled off after placing the ultrathin copper foil in contact with the second insulating resin layer, laminating by heating and pressing.
- a commercially available product can be used as the ultrathin copper foil with carrier copper foil, for example, MTex (product name) manufactured by Mitsui Mining & Smelting Co., Ltd. can be used.
- MTex product name
- the second insulating resin layer a commercially available product can be used.
- CRS-381 NSI product name manufactured by Mitsubishi Gas Chemical Co., Ltd. can be used.
- the heating and pressurizing conditions for the second insulating resin layer and the metal layer are not particularly limited.
- vacuum pressing is performed under the conditions of a temperature of 220 ⁇ 2 ° C., a pressure of 2.5 ⁇ 0.2 MPa, and a holding time of 60 minutes.
- the second insulating resin layer and the metal layer can be laminated.
- Step (c) is not particularly limited, and for example, the second insulating resin layer and the metal layer can be laminated by the following steps.
- a roughening process is performed on the surface of the first wiring conductor to obtain an adhesive force with the second insulating resin layer (step (c-1)), and the second insulation is performed.
- a resin layer is disposed in contact with the first wiring conductor subjected to the roughening treatment, a metal layer is further disposed on the second insulating resin layer, heated and pressurized, and the second layer An insulating resin layer and the metal layer can be laminated (step (c-2)).
- the said roughening process is not specifically limited, A well-known means can be used suitably, For example, the means using a copper surface roughening liquid is mentioned.
- Step (d) In the step (d), a non-through hole reaching the first wiring conductor is formed in the second insulating resin layer, and an inner wall of the non-through hole is connected by electrolytic copper plating and / or electroless copper plating. In this step, the second wiring conductor is formed.
- the first wiring conductor 5 and the metal layer 7 are: They are electrically connected through plated copper formed on the inner wall of the non-through hole.
- the second wiring conductor 8 can be formed on the second insulating resin layer 6 by patterning the metal layer 7.
- the means for forming the non-through hole is not particularly limited, and for example, a known means such as a laser such as a carbon dioxide laser or a drill can be used.
- the non-through hole is formed in the second insulating resin layer via the metal layer, and is provided to electrically connect the second wiring conductor and the first wiring conductor formed in this step.
- the number and size of the non-through holes can be appropriately selected as desired.
- a desmear process can be performed using sodium permanganate aqueous solution.
- electrolytic copper plating and / or electroless copper plating is performed to form a copper plating film on the inner wall of the non-through hole, and the first wiring conductor and the second wiring conductor are formed. Electrically connect to the wiring conductor.
- the method of performing electrolytic copper plating and / or electroless plating is not particularly limited, and a known method can be employed.
- the copper plating may be either electrolytic copper plating or electroless plating, but it is preferable to perform both electrolytic copper plating and electroless plating.
- Step (d) forms a second wiring conductor after electrolytic and / or electroless copper plating.
- the method for forming the second wiring conductor is not particularly limited, and for example, known means such as a subtractive method or a semi-additive method can be appropriately employed.
- the step (d) is not particularly limited.
- a non-through hole reaching the first wiring conductor is formed in the second insulating resin layer (step (d-1)), and the inner wall of the non-through hole is formed.
- steps (d-2) are connected by electrolytic copper plating and / or electroless copper plating (step (d-2)), and the second wiring conductor is formed by a subtractive method or a semi-additive method (step (d-3)).
- step (d-3) is not particularly limited.
- the surface of the metal layer is adjusted, a dry film resist or the like is laminated, a negative mask is pasted, and a circuit pattern is formed by an exposure machine.
- An etching resist can be formed by developing the dry film resist by baking or developing solution. Thereafter, an etching process is performed, and after removing the copper having no etching resist with a ferric chloride aqueous solution or the like, the resist is removed, whereby the second wiring conductor can be formed.
- an interlayer connection method applicable in the present embodiment, a method of applying chemical copper plating to a known laser-formed blind via portion (forming a wiring circuit by laser processing and then patterning by chemical copper plating) , A method for performing interlayer connection), a method for performing interlayer connection by piercing the entire insulating layer with a metal bump (preferably a copper bump) formed by plating or etching a metal foil in a portion to be a connection portion in advance, After a bump paste is printed on a specified location by screen printing, etc., with a metal paste containing a metal filler such as solder, silver or copper in the insulating resin, the paste is cured by drying, and electrical conduction between the inner and outer layers is ensured by heating and pressing. What to do can be applied.
- a metal bump preferably a copper bump
- Step (e) is a step of peeling off the first insulating resin layer from the circuit forming substrate on which the first and second wiring conductors are formed. After the step (e), as shown in FIG. 1G, the first insulating resin layer is peeled off at the interface with the peeling layer 3, and the first wiring conductor 5 is placed on the peeling layer 3 and the copper foil 4. A laminated body in which the second insulating resin layer 6 and the second wiring conductor 8 are laminated is formed.
- the first insulating resin layer is peeled off at the interface between the first insulating resin layer and the peeling layer.
- a part of the peeling layer is the first insulating resin. It may be peeled off with the layer.
- the aspect by which a 1st insulating resin layer is peeled with a peeling layer in the interface of a peeling layer and copper foil is also contained.
- a means for peeling off the first insulating resin layer either physical means or chemical means can be adopted.
- the first insulating resin layer is physically applied by applying physical force to the peeling layer. Is preferably peeled off.
- Step (f) is a step of removing the release layer 3 and / or the copper foil 4 from the circuit forming substrate.
- the first wiring conductor 5 (inner layer) is embedded in the second insulating resin layer 6, and the first wiring conductor 5 (inner layer) and the first wiring conductor 5
- the circuit forming substrate 10 for mounting a semiconductor element in which the two wiring conductors 8 (outer layer) are electrically joined can be formed.
- the peeling layer and / or the copper foil preferably, an ultrathin copper foil
- the step (e) when the first insulating resin layer is peeled off at the interface with the release layer, and the release layer is broken and part of the release layer is peeled off together with the first insulating resin layer.
- the whole or part of the peeling layer and the copper foil are removed.
- the first insulating resin layer is peeled off at the interface between the release layer and the copper foil together with the release layer in the step (e)
- only the copper foil is removed in the removal step (f).
- the sulfuric acid-based or hydrogen peroxide-based etching solution is not particularly limited, and those used in the art can be appropriately selected and used.
- the circuit forming substrate 10 is a package substrate for mounting a semiconductor element having a two-layer structure.
- the present embodiment is not limited to this, and a three-layer structure is used.
- a semiconductor device mounting package substrate having a build-up structure of a structure or more (three-layer structure, four-layer structure,... N-layer structure) can be formed. That is, in the method for manufacturing a semiconductor element mounting substrate in the present embodiment, the circuit forming substrate on which the first and second wiring conductors are formed between the step (d) and the step (e).
- the insulating resin layer lamination step and the wiring conductor forming step may be repeated to further include a step of forming a build-up structure.
- the insulating resin layer laminating step and the wiring conductor forming step are performed by the same procedure as the step (c) and the step (d), respectively.
- the method for manufacturing a semiconductor element mounting substrate in the present embodiment may further include a step of forming a solder resist layer on the circuit forming substrate on which the second wiring conductor is formed. This step may be performed, for example, between step (d) and step (e) or between step (f) and step (g) described below.
- the solder resist layer is not particularly limited, and can be formed by, for example, a laminator or hot press.
- Step (g) is a step of pressing and laminating the above support on the circuit forming substrate. Specifically, the heat-resistant film layer 11 of the support is placed in contact with the surface on which the second wiring conductor 8 of the circuit forming substrate is formed, and then pressed. After step (g), as shown in FIG. 1I, a laminate 20 is formed in which a support is laminated on the surface of the circuit formation substrate on which the second wiring conductor is formed.
- the figure shown to FIG. 1I shows a laminated body at the time of apply
- a structure in which the step (g) is directly performed from the step (f) may be used without forming the structure in which the solder resist layer is formed on both sides or the solder resist layer 9.
- the method of pressing the support is not particularly limited. For example, after the heat-resistant film layer of the support is placed in contact with the surface on which the second wiring conductor of the circuit forming substrate is formed, the temperature is 120 to 200 ° C. Then, vacuum pressing is performed under the conditions of a pressure of 1 to 4 MPa and a holding time of 30 to 120 minutes.
- Step (h) is a step of mounting a semiconductor element on the wiring conductor of the circuit forming substrate. After step (h), as shown in FIG. 1J, a stacked body on which semiconductor elements are mounted is formed. In FIG. 1J, a pair chip 14 is mounted on a first wiring conductor via a solder ball 13 and further sealed with a mold resin 15.
- the semiconductor element can be mounted on the wiring conductor via a bonding material.
- a bonding material is further formed on the gold plating layer. It is mounted and reflowed at about 260 ° C. to produce a multilayer printed wiring board on which a bonding material is formed.
- a gold plating layer is not specifically limited, For example, it can form by electrolysis, electrolessness, and a paste.
- the bonding material is not particularly limited as long as it has a conductive means. For example, solder (for example, solder balls, solder paste) can be used.
- the reflow temperature is appropriately selected depending on the melting point of the bonding material, but is preferably 260 ° C. or higher, for example.
- the semiconductor element is not particularly limited, and a desired element can be appropriately used.
- a bare chip in which a gold bump is formed on the aluminum electrode portion by a gold wire ball bonding method can be used.
- the mold resin a known resin used for sealing material can be appropriately selected and used.
- a step of forming a gold plating layer on the opening is performed before mounting the semiconductor element, after forming a solder resist layer having an opening on the wiring conductor. For example, it may be performed between the step (d) and the step (e) or between the step (f) and the step (g).
- Step (i) is a step of peeling the support from the circuit forming substrate. After step (i), as shown in FIG. 1K, the support is peeled from the stacked body on which the semiconductor elements are mounted, and the semiconductor element mounting substrate 30 can be obtained. Either a physical means or a chemical means can be adopted as the means for peeling off the support. For example, it is preferable to physically peel the support by applying a physical force to the heat-resistant film layer.
- the manufacturing method of the semiconductor element mounting substrate in the second embodiment (Embodiment 2) for carrying out the present invention includes the following steps.
- a non-through hole reaching the first wiring conductor is formed in the second insulating resin layer, and an inner wall of the non-through hole is connected by electrolytic copper plating and / or electroless copper plating to form a second wiring
- a step of forming a conductor (j) a step of pressing and laminating the support on a circuit forming substrate on which the first and second wiring conductors are formed; (k) from a circuit
- a package substrate for mounting a semiconductor element having a build-up structure having a three-layer structure or more is formed. May be. That is, between the step (d) and the step (e), the insulating resin layer stacking step and the wiring conductor forming step are repeatedly performed on the circuit forming substrate on which the first and second wiring conductors are formed.
- the method may further include a step of forming a build-up structure.
- Step (j) is a step of pressing and laminating the support on the circuit forming substrate (FIG. 2A) on which the first and second wiring conductors are formed. Specifically, the heat-resistant film layer 11 of the support is placed in contact with the surface on which the second wiring conductor 8 of the circuit forming substrate is formed, and then pressed. After step (j), as shown in FIG. 2B, a laminated body is formed in which a support is laminated on the surface of the circuit forming substrate on which the second wiring conductor is formed. In addition, the figure shown to FIG.
- step (j) may be performed directly from step (d).
- the method for forming the solder resist layer is as described above.
- the method for pressing the support is the same as in step (g) described above.
- Step (k) is a step of peeling the first insulating resin layer from the circuit forming substrate on which the support is laminated. After the step (k), as shown in FIG. 2C, the first insulating resin layer is peeled off at the interface with the peeling layer 3, and the first wiring conductor 5 is placed on the peeling layer 3 and the copper foil 4. Then, the second insulating resin layer 6 and the second wiring conductor 8 are laminated, and a laminated body is formed in which the support is laminated on the surface on which the second wiring conductor is formed.
- the first insulating resin layer is peeled off at the interface between the first insulating resin layer and the peeling layer.
- a part of the peeling layer is the first insulating resin. It may be peeled off with the layer.
- the aspect by which a 1st insulating resin layer is peeled with a peeling layer in the interface of a peeling layer and copper foil is also contained.
- a means for peeling off the first insulating resin layer either physical means or chemical means can be adopted.
- the first insulating resin layer is physically applied by applying physical force to the peeling layer. Is preferably peeled off.
- Step (l) is a step of removing the release layer and / or the copper foil from the circuit forming substrate.
- the first wiring conductor 5 (inner layer) is embedded in the second insulating resin layer 6, and the first wiring conductor 5 (inner layer) and the first wiring conductor 5
- a laminated body 20 in which a support body is laminated on a circuit formation substrate for mounting a semiconductor element in which two wiring conductors 8 (outer layers) are electrically joined can be formed.
- the peeling layer and / or the ultrathin copper foil can be removed using a sulfuric acid-based or hydrogen peroxide-based etching solution.
- the step (k) when the first insulating resin layer is peeled off at the interface with the release layer, and when the release layer is broken, a part thereof is peeled off together with the first insulating resin layer. In some cases, the entire peeling layer or a part thereof and the copper foil are removed in the removing step (l).
- the first insulating resin layer is peeled off at the interface between the peeling layer and the copper foil together with the peeling layer in the step (k), only the copper foil is removed in the removing step (l).
- the sulfuric acid-based or hydrogen peroxide-based etching solution is not particularly limited, and those used in the art can be appropriately selected and used.
- a step of forming a gold plating layer in the opening is performed. May be performed, for example, between the step (l) and the step (h).
- Embodiment 1 performs an electrical test using a circuit formation board
- this invention is not specifically limited to these embodiment, The embodiment other than above-described Embodiment 1 and Embodiment 2 is also included.
- Example 1 ⁇ Production of support> On one side of a prepreg (thickness 0.100 mm: manufactured by Mitsubishi Gas Chemical Co., Ltd., product name: GHPL-830NS ST56) made by impregnating a glass cloth (glass fiber) with bismaleimide triazine resin (BT resin) into a B stage.
- a prepreg thickness 0.100 mm: manufactured by Mitsubishi Gas Chemical Co., Ltd., product name: GHPL-830NS ST56
- BT resin bismaleimide triazine resin
- a polyimide film with an adhesive layer having a thickness of 27 ⁇ m (adhesive layer thickness: 15 ⁇ m, manufactured by Nikkan Kogyo Co., Ltd., product name: CISV) is placed so that the adhesive layer surface is in contact with the insulating resin layer,
- a 18 ⁇ m thick copper foil (product name: 3EC-VLP, manufactured by Mitsui Mining & Smelting Co., Ltd.) is placed and vacuum pressed under conditions of a temperature of 80 ⁇ 2 ° C, a pressure of 1.0 ⁇ 0.2 MPa, and a holding time of 3 minutes. Then, a support (a) (thickness: 145 ⁇ m) was produced.
- the thickness of the copper foil is adjusted to 3 ⁇ m by etching using a perhydrosulfuric acid based soft etching solution, and a release layer and a copper foil are provided in this order on both surfaces of the first insulating resin layer.
- a circuit-forming support substrate was prepared.
- the dry film resist was developed using a 1% aqueous sodium carbonate solution to form a resist pattern for plating.
- pattern electrolytic copper plating electrolytic copper plating
- a copper sulfate plating line having a copper sulfate concentration of 60 to 80 g / L and a sulfuric acid concentration of 150 to 200 g / L, thereby forming a first wiring conductor.
- the dry film resist was peeled and removed using an amine resist stripping solution.
- ⁇ Step (c)> In order to obtain adhesion with the insulating resin, the surface of the first wiring conductor (copper pattern) was subjected to a roughening treatment using a copper surface roughening solution CZ-8100 (product name, manufactured by MEC Co., Ltd.). Next, a prepreg (thickness: 0.100 mm) having a B-stage by impregnating glass cloth (glass fiber) with bismaleimide triazine resin (BT resin) on both surfaces of the circuit-forming support substrate on which the first wiring conductor is formed. : Mitsubishi Gas Chemical Co., Ltd., product name: GHPL-830NS ST56).
- an ultrathin copper foil with a carrier copper foil having a thickness of 18 ⁇ m on the prepreg (ultrathin copper foil (metal layer); thickness 2 ⁇ m: manufactured by Mitsui Mining & Smelting Co., Ltd., product name: MTEx), and the carrier copper foil side being a prepreg
- a pressure of 2.5 ⁇ 0.2 MPa, a temperature of 220 ⁇ 2 ° C., and a holding time of 60 minutes
- the carrier copper foil having a thickness of 18 ⁇ m was peeled off to obtain a circuit-forming support substrate in which the second insulating resin layer and the ultrathin copper foil having a thickness of 2 ⁇ m were laminated on the first wiring conductor.
- a beam irradiation diameter of ⁇ 0.21 mm, a frequency of 500 Hz, a pulse width of 10 ⁇ s, and the number of irradiations of 7 shots one hole at a time, and the first insulating resin layer through the metal layer. A non-through hole reaching the wiring conductor was formed.
- a desmear treatment is performed on the support substrate for circuit formation in which non-through holes are formed using a sodium permanganate aqueous solution at a temperature of 80 ⁇ 5 ° C. and a concentration of 55 ⁇ 10 g / L, and further by electroless copper plating.
- plating with a thickness of 0.4 to 0.8 ⁇ m plating with a thickness of 15 to 20 ⁇ m was performed by electrolytic copper plating.
- the inner wall of the non-through hole is connected by plating, and the first wiring conductor (inner layer) and the metal layer (outer layer) are electrically connected by plating of the inner wall of the non-through hole.
- a dry film resist NIT225 product name, manufactured by Nichigo Morton Co., Ltd.
- the circuit pattern was baked using a parallel exposure machine, and the dry film resist was developed using a 1% sodium carbonate aqueous solution to form an etching resist.
- the dry film resist was removed with an aqueous sodium hydroxide solution to form a second wiring conductor.
- the first insulating resin layer (prepreg layer) was peeled from the circuit-forming support substrate on which was formed to form a set of laminates.
- Step (f)> In the peeling step (e), after peeling off the first insulating resin layer (prepreg layer), the ultrathin copper foil and the release layer were removed using a perhydrosulfuric acid-based soft etching solution. Thereafter, a 10 ⁇ m solder resist was formed and gold plating was performed.
- ⁇ Process (g)> In the removal step (f), a solder resist of 10 ⁇ m is formed, and one side of the circuit-formed substrate that has been subjected to gold plating is placed so that the polyimide layer of the support (a) is in contact with it, temperature 160 ⁇ 2 ° C., pressure 3 Vacuum pressing was performed under the conditions of 0.0 ⁇ 0.2 MPa and a holding time of 60 minutes, to produce a laminate.
- Step (h) and step (i)> The laminated body obtained in the step (g) was cut into a package size to obtain a package substrate for mounting a semiconductor element.
- solder balls were mounted on the gold plating layer and reflowed at about 260 ° C. to produce a multilayer printed wiring board on which the solder balls were formed.
- the obtained multilayer printed wiring board was aligned with a bare chip in which gold bumps were formed by a gold wire ball bonding method on the aluminum electrode portion, and the bare chip was mounted on the multilayer printed wiring board.
- the multilayer printed wiring board on which the bare chip was mounted was reflowed at about 260 ° C. and soldered, and then washed and sealed with a mold resin. Thereafter, a physical force was applied to the boundary between the solder resist layer and the polyimide layer, and the support (a) was peeled from the multilayer printed wiring board to produce a semiconductor element mounting substrate.
- Example 2 ⁇ Process (c)> Step (a) and step (b) in Example 1 are performed, and in order to obtain adhesion with the insulating resin layer, the surface of the first wiring conductor (copper pattern) is coated with a copper surface roughening solution CZ-8100 (MEC Co., Ltd.). Roughening treatment was performed using a product name manufactured by company.
- bismaleimide triazine resin BT resin
- BT resin bismaleimide triazine resin
- an ultrathin copper foil ultrathin copper foil (ultrathin copper foil (metal layer)
- carrier copper foil having a thickness of 18 ⁇ m.
- Thickness 2 ⁇ m Copper foil with resin applied to B-stage by applying to Mitsui Metals Mining Co., Ltd. (product name: MTEx) (thickness 15 ⁇ m: manufactured by Mitsubishi Gas Chemical Co., Ltd., product name: CRS-381 NSI) was placed under vacuum and pressure was pressed under the conditions of pressure 2.5 ⁇ 0.2 MPa, temperature 220 ⁇ 2 ° C. and holding time 60 minutes. Thereafter, the carrier copper foil having a thickness of 18 ⁇ m was peeled off to obtain a circuit-forming support substrate in which the second insulating resin layer and the ultrathin copper foil having a thickness of 2 ⁇ m were laminated on the first wiring conductor.
- a beam irradiation diameter of ⁇ 0.21 mm, a frequency of 500 Hz, a pulse width of 10 ⁇ s, and the number of irradiations of 7 shots one hole at a time, and the first insulating resin layer through the metal layer. A non-through hole reaching the wiring conductor was formed.
- a desmear treatment is performed on the support substrate for circuit formation in which non-through holes are formed using a sodium permanganate aqueous solution at a temperature of 80 ⁇ 5 ° C. and a concentration of 55 ⁇ 10 g / L, and further by electroless copper plating.
- plating with a thickness of 0.4 to 0.8 ⁇ m plating with a thickness of 15 to 20 ⁇ m was performed by electrolytic copper plating.
- the inner wall of the non-through hole is connected by plating, and the first wiring conductor (inner layer) and the metal layer (outer layer) are electrically connected by plating of the inner wall of the non-through hole.
- a dry film resist NIT225 product name, manufactured by Nichigo Morton Co., Ltd.
- a circuit pattern was baked using a parallel exposure machine, and then a dry film resist was developed using a 1% sodium carbonate aqueous solution to form an etching resist.
- the dry film resist was removed with an aqueous sodium hydroxide solution to form a second wiring conductor.
- ⁇ Process (e)> After forming the second wiring conductor, a 10 ⁇ m solder resist is formed on the second wiring conductor, and a physical force is applied to the boundary between the peeling layer-attached copper foil and the first insulating resin layer (prepreg layer). In addition, the first insulating resin layer (prepreg layer) was peeled from the circuit-forming support substrate on which the first wiring conductor and the second wiring conductor were formed to form a set of laminated bodies.
- Step (f)> In the peeling step (e), after peeling off the first insulating resin layer (prepreg layer), the ultrathin copper foil and the release layer were removed using a perhydrosulfuric acid-based soft etching solution. Thereafter, a 10 ⁇ m solder resist was formed and gold plating was performed.
- ⁇ Process (g)> In the removal step (f), a solder resist of 10 ⁇ m is formed, and one side of the circuit-formed substrate that has been subjected to gold plating is placed so that the polyimide part of the support (a) is in contact with it, temperature 160 ⁇ 2 ° C., pressure 3 Vacuum pressing was performed under the conditions of 0.0 ⁇ 0.2 MPa and a holding time of 60 minutes, to produce a laminate.
- Step (h) and step (i)> The laminated body obtained in the step (g) was cut into a package size to obtain a package substrate for mounting a semiconductor element.
- solder balls were mounted on the gold plating layer and reflowed at about 260 ° C. to produce a multilayer printed wiring board on which the solder balls were formed.
- the obtained multilayer printed wiring board was aligned with a bare chip in which gold bumps were formed by a gold wire ball bonding method on the aluminum electrode portion, and the bare chip was mounted on the multilayer printed wiring board.
- the multilayer printed wiring board on which the bare chip was mounted was reflowed at about 260 ° C. and soldered, and then washed and sealed with a mold resin. Thereafter, a physical force was applied to the boundary between the solder resist layer and the polyimide layer, and the support (a) was peeled from the multilayer printed wiring board to produce a semiconductor element mounting substrate.
- Example 3 ⁇ Process (j)> Step (a) to step (d) in Example 2 were sequentially performed, a 10 ⁇ m solder resist was formed on the second wiring conductor, and gold plating was performed. After that, one side of the circuit-forming support substrate is placed so that the polyimide part of the support (a) is in contact with it, and vacuum pressing is performed under conditions of a temperature of 160 ⁇ 2 ° C., a pressure of 3.0 ⁇ 0.2 MPa, and a holding time of 60 minutes. Was carried out to produce a laminate.
- Steps (k) and (l)> In the peeling step, after peeling off the first insulating resin layer (prepreg layer) from the laminate, the ultrathin copper foil and the release layer were removed using a perhydrosulfuric acid based soft etching solution. Thereafter, a 10 ⁇ m solder resist was formed.
- Step (h) and step (i)> The stacked body obtained in the step (l) was cut into a package size to obtain a package substrate for mounting a semiconductor element.
- solder balls were mounted on the gold plating layer and reflowed at about 260 ° C. to produce a multilayer printed wiring board on which the solder balls were formed.
- the obtained multilayer printed wiring board was aligned with a bare chip in which gold bumps were formed by a gold wire ball bonding method on the aluminum electrode portion, and the bare chip was mounted on the multilayer printed wiring board.
- the multilayer printed wiring board on which the bare chip was mounted was reflowed at about 260 ° C. to perform solder connection, then washed and sealed with a mold resin. Thereafter, a physical force was applied to the boundary between the solder resist layer and the polyimide layer, and the support (a) was peeled from the multilayer printed wiring board to produce a semiconductor element mounting substrate.
- Example 1 Without using the support (a), the steps (a) to (f), (h) and (i) in Example 1 were sequentially performed to produce a package substrate for mounting a semiconductor element (thickness 60 ⁇ m). ). After that, solder balls were mounted on the gold plating layer and reflowed at about 260 ° C., but the substrate was damaged because the substrate was thin and rigid.
- the support in the present embodiment has industrial applicability as a support for a package substrate for mounting a semiconductor when a semiconductor element mounting substrate is manufactured.
- SYMBOLS 1 Support substrate for circuit formation 2 ... 1st insulating resin layer 3 ... Stripping layer 4 ... Copper foil 5 ... 1st wiring conductor 6 ... 2nd insulating resin Layer 7 ... Metal layer 8 ... Second wiring conductor 9 ... Solder resist layer 10 ... Circuit forming substrate 11 ... Heat-resistant film layer 12 ... Resin layer 13 ... Solder ball 14 ... Bare chip 15 ... Mold resin 20 ... Laminated body 30 ... Semiconductor element mounting substrate
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Abstract
Description
更には、その支持体を用いた半導体素子実装基板の製造方法を提供することを目的とする。
[1]
耐熱フィルム層と、樹脂層と、含む支持体であって、
前記樹脂層の少なくとも一方の面(第1の面)に前記耐熱フィルム層が積層されており、
前記樹脂層が半硬化状態(Bステージ)である、支持体。
[2]
前記樹脂層の前記耐熱フィルム層が積層された面とは反対側の面(第2の面)に、銅箔が更に積層された、前記[1]に記載の支持体。
[3]
前記耐熱フィルム層は、ポリイミド樹脂、ポリアミドイミド樹脂、ナイロン樹脂及びフッ素系樹脂からなる群から選択される1種以上の樹脂を含む、前記[1]又は[2]に記載の支持体。
[4]
前記耐熱フィルム層は接着層付き耐熱フィルム層であって、前記接着層は、フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂からなる群から選択される1種以上の樹脂を含む、前記[1]~[3]のいずれかに記載の支持体。
[5]
10~400μmの厚さを有する、前記[1]~[4]のいずれかに記載の支持体。
前記樹脂層はガラスクロスに熱硬化性樹脂を含浸させたプリプレグを含む、前記[1]~[5]のいずれかに記載の支持体。
[7]
前記熱硬化性樹脂は、フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、ビスマレイミドトリアジン樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂からなる群から選択される1種以上の樹脂を含む、前記[6]に記載の支持体。
[8]
前記耐熱フィルム層は前記樹脂層よりも表面積が小さい、前記[1]~[7]のいずれかに記載の支持体。
[9]
前記[1]~[8]のいずれかに記載の支持体を用いた半導体素子実装基板の製造方法であって、
第1及び第2の配線導体が形成された回路形成基板に前記支持体をプレスして積層した後、前記配線導体上に半導体素子を実装する工程を含む、製造方法。
以下の工程を含む、前記[9]に記載の半導体素子実装基板の製造方法。
(a)第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程
(b)前記回路形成用支持基板の前記銅箔上に、第1の配線導体を形成する工程
(c)前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程
(d)前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて第2の配線導体を形成する工程
(e)前記第1及び第2の配線導体が形成された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程
(f)前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程
(g)前記回路形成基板に前記支持体をプレスして積層する工程
(h)前記回路形成基板の前記配線導体上に半導体素子を実装する工程
(i)前記回路形成基板から前記支持体を剥離する工程
前記工程(d)と前記工程(e)の間に、前記第1及び第2の配線導体が形成された回路形成基板に対して、絶縁樹脂層積層工程及び配線導体形成工程を繰り返し行い、ビルドアップ構造を形成する工程を更に含む、前記[10]に記載の半導体素子実装基板の製造方法。
[12]
前記工程(f)と前記工程(g)の間に、ソルダーレジスト層を形成する工程を更に含む、前記[10]又は[11]に記載の半導体素子実装基板の製造方法。
[13]
前記ソルダーレジスト層を形成する工程の後、金めっき層を形成する工程を更に含む、前記[12]に記載の半導体素子実装基板の製造方法。
[14]
前記工程(d)と前記工程(e)の間に、ソルダーレジスト層を形成する工程を含む、前記[10]又は[11]に記載の半導体素子実装基板の製造方法。
[15]
前記ソルダーレジスト層を形成する工程の後、金めっき層を形成する工程を更に含む、前記[14]に記載の半導体素子実装基板の製造方法。
以下の工程を含む、前記[9]に記載の半導体素子実装基板の製造方法。
(a)第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程
(b)前記回路形成用支持基板の前記銅箔上に、第1の配線導体を形成する工程
(c)前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程
(d)前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて第2の配線導体を形成する工程
(j)前記第1及び第2の配線導体が形成された回路形成基板に前記支持体をプレスして積層する工程
(k)前記支持体が積層された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程
(l)前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程
(h)前記回路形成基板の前記配線導体上に半導体素子を実装する工程
(i)前記回路形成基板から前記支持体を剥離する工程
前記工程(d)と前記工程(e)の間に、前記第1及び第2の配線導体が形成された回路形成基板に対して、絶縁樹脂層積層工程及び配線導体形成工程を繰り返し行い、ビルドアップ構造を形成する工程を更に含む、前記[16]に記載の半導体素子実装基板の製造方法。
[18]
前記工程(l)と前記工程(h)の間に、ソルダーレジスト層を形成する工程を更に含む、前記[16]又は[17]に記載の半導体素子実装基板の製造方法。
[19]
前記ソルダーレジスト層を形成する工程の後、金めっき層を形成する工程を更に含む、前記[18]に記載の半導体素子実装基板の製造方法。
なお、本実施形態において、「(メタ)アクリロ」とは「アクリロ」及びそれに対応する「メタクリロ」の両方を意味し、「(メタ)アクリル」とは「アクリル」及びそれに対応する「メタクリル」の両方を意味し、「(メタ)アクリレート」とは「アクリレート」及びそれに対応する「メタクリレート」の両方を意味する。
本実施形態における支持体は、
耐熱フィルム層と、樹脂層と、含む支持体であって、
前記樹脂層の少なくとも一方の面(第1の面)に前記耐熱フィルム層が積層されており、
前記樹脂層が半硬化状態(Bステージ)である。
樹脂層としては、特に限定されず、後述する第1及び第2の絶縁樹脂層と同様のものを用いることができるが、中でも、基板の耐熱性や寸法安定性の観点から、ガラスクロスに熱硬化性樹脂を含浸させたプリプレグを含むことが好ましい。
熱硬化性樹脂としては、例えば、フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、ビスマレイミドトリアジン樹脂(「BT樹脂」とも称す)、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂が挙げられる。これらの熱硬化性樹脂は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。これらの熱硬化性樹脂の中でも、基板の耐熱性や寸法安定性の観点から、ビスマレイミドトリアジン樹脂、エポキシ樹脂、シアネート樹脂及びマレイミド樹脂が好ましく、ビスマレイミドトリアジン樹脂がより好ましい。フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂のそれぞれの具体例は、後述の絶縁材料の樹脂組成物に用いられる熱硬化性樹脂に記載のとおりである。
プリプレグとしては、市販品を用いることもでき、例えば、三菱ガス化学(株)製のGHPL-830NS(製品名)を使用することができる。
本実施形態における支持体は、樹脂層の少なくとも一方の面に耐熱フィルム層が積層されている。耐熱フィルム層としては、耐熱性樹脂からなるフィルムであれば特に限定されず、耐熱性樹脂としては、例えば、ポリイミド樹脂、ポリアミドイミド樹脂、ナイロン樹脂及びフッ素系樹脂が挙げられる。これらの耐熱性樹脂は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。これらの耐熱性樹脂の中でも、耐熱性の観点から、ポリイミド樹脂、フッ素系樹脂が好ましい。
ポリアミドイミド樹脂としては、特に限定されず、例えば、トリメリット酸無水物、ベンゾフェノンテトラカルボン酸無水物及びビトリレンジイソシアネートをN-メチル-2-ピロリドン及び/又はN,N-ジメチルアセトアミドの溶剤中で加熱することで得られる樹脂や、トリメリット酸無水物、ジフェニルメタンジイソシアネート及びカルボキシル基末端(メタ)アクリロニトリル-ブタジエンゴムをN-メチル-2-ピロリドン及び/又はN,N-ジメチルアセトアミドなどの溶剤中で加熱することで得られるものが挙げられる。これらのポリアミドイミド樹脂は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。
ナイロン樹脂としては、特に限定されず、例えば、ナイロン6、ナイロン6,6及びアラミドが挙げられる。これらのナイロン樹脂は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。
フッ素系樹脂としては、特に限定されず、例えば、ポリテトラフルオロエチレン、ポリビニリデンフルオライド及びポリクロロトリフルオロエチレンが挙げられる。これらのフッ素系樹脂は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。
接着層を構成する樹脂としては、特に限定されず、例えば、フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂、ビスマレイミドトリアジン樹脂及びビニル樹脂が挙げられる。これらの接着層を構成する樹脂は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂のそれぞれの具体例は、後述の絶縁材料の樹脂組成物に用いられる熱硬化性樹脂に記載のとおりである。
接着層付き耐熱フィルムとしては、市販品を用いることもでき、例えば、ニッカン工業(株)製のCISV(製品名)を使用することができる。
本実施形態における支持体は、前記絶縁樹脂層の前記耐熱フィルム層が積層された面とは反対側の面(第2の面)に、銅箔が更に積層されていてもよい。樹脂層の第2の面に銅箔が更に積層されていることにより、基板の剛性を高めることができるという利点を有する。
銅箔としては、後述する銅箔と同様のものを用いることができる。
本実施形態における半導体素子実装基板の製造方法は、前記支持体を用いた製造方法であって、第1及び第2の配線導体が形成された回路形成基板に前記支持体をプレスして積層した後、前記配線導体上に半導体素子を実装する工程を含む。本実施形態の半導体素子実装基板の製造方法は、前記支持体を用いることによって基板のハンドリング性を向上させることができるため、基板が極めて薄い場合であっても、半導体素子の実装やソルダーレジストの塗布が容易となる。
以下、より具体的な製造方法について説明する。
本発明を実施するための第1の形態(実施形態1)における半導体素子実装基板の製造方法は、以下の工程を含む。
(a)第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程
(b)前記回路形成用支持基板の前記銅箔上に、第1の配線導体を形成する工程
(c)前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程
(d)前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて第2の配線導体を形成する工程
(e)前記第1及び第2の配線導体が形成された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程
(f)前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程
(g)前記回路形成基板に前記支持体をプレスして積層する工程
(h)前記回路形成基板の前記配線導体上に半導体素子を実装する工程
(i)前記回路形成基板から前記支持体を剥離する工程
本実施形態における工程(a)は、第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程である。
第1の絶縁樹脂層には、片面のみに剥型層と銅箔が配置されていてもよいが、これらの層が第1の絶縁樹脂層の両面に配置されていることが好ましい。すなわち、本実施形態における回路形成用支持基板は、剥型層付き2層コア基板であることが好ましい。図1を用いて回路形成用支持基板(剥型層付き2層コア基板)1の構成について説明する。図1Bに示すように、回路形成用支持基板1は、第1の絶縁樹脂層(例えば、プリプレグ)2の両面に、剥型層3と銅箔4とが、第1の絶縁樹脂層2の表面側から順に設けられている。
積層の方法や条件は、特に限定されるものではないが、例えば、温度220±2℃、圧力5±0.2MPa、保持時間60分間の条件にて真空プレスを実施することで、回路形成用支持基板を形成することができる。
工程(a)における第1の絶縁樹脂層としては、特に限定されるものではないが、例えば、ガラスクロスなどの基材に熱硬化性樹脂などの絶縁性の樹脂材料(絶縁材料)を含浸させたプリプレグや、絶縁性のフィルム材などを用いることができる。
硬化触媒としては、例えば、マンガン、鉄、コバルト、ニッケル、銅、亜鉛の金属類を用いることができ、具体的には、2-エチルヘキサン酸塩、オクチル酸塩などの有機金属塩やアセチルアセトン錯体などの有機金属錯体を挙げることができる。これらの硬化触媒は、1種類を単独で用いてもよいし、2種類以上を混合して用いてもよい。
第1の絶縁樹脂層の厚さは、所望に応じて適宜設定するので特に限定されないが、0.02mm~2.0mmとすることができ、0.03mm~0.2mmが好ましく、0.04mm~0.15mmがより好ましい。
本実施形態における回路形成用支持基板は、剥型層を含む。剥型層は、ケイ素化合物を少なくとも含むことが好ましい。
銅箔は、特に限定されないが、通常、厚さが1μm~5μmであり、好ましくは2μm~4μmであり、更に好ましくは2.5μm~3.5μmの極薄銅箔である。銅箔は、特に限定されないが、JISB0601:2001に示す10点の平均粗さ(Rzjis)が両面とも0.3μm~3.0μmであることが好ましく、0.5μm~2.0μmがより好ましく、0.7μm~1.5μmが更に好ましい。
工程(b)は、前記の回路形成用支持基板の銅箔上に、第1の配線導体を形成する工程である。工程(b)を経ることで、図1Cに示すように、回路形成用支持基板1の銅箔4上に第1の配線導体5が形成される。第1の配線導体の形成手段は、特に限定されず、例えば、以下の工程によって第1の配線導体を形成することができる。
工程(c)は、前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程である。工程(c)は、前記第2の絶縁樹脂層上に金属層を更に配置し、加熱及び加圧して、前記第2の絶縁樹脂層と前記金属層とを積層する工程であってもよい。工程(c)を経ることで、図1Dに示すように、第1の配線導体5と接するように第2の絶縁樹脂層6と金属層7とを積層させることができる。なお、図1Dにおいては、金属層を設けた態様をしているが本発明は当該態様に限定されるものではない。
第2の絶縁樹脂層としては、市販品を用いることもでき、例えば、三菱ガス化学(株)製のCRS-381 NSI(製品名)を使用することができる。
工程(d)は、前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて、第2の配線導体を形成する工程である。第2の配線導体形成工程(d)においては、電解銅めっき及び/又は無電解銅めっきが施されることにより、図1Eに示すように、第1の配線導体5と金属層7とが、非貫通孔の内壁に形成されためっき銅を通じて電気的に接続される。その後、図1Fに示すように、金属層7をパターニングすることにより、第2の絶縁樹脂層6上に第2の配線導体8を形成することができる。
工程(e)は、前記第1及び第2の配線導体が形成された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程である。工程(e)を経ると、図1Gに示すように、剥型層3との界面において第1の絶縁樹脂層が剥離され、剥型層3と銅箔4上に、第1の配線導体5、第2の絶縁樹脂層6及び第2の配線導体8が積層した積層体が形成される。
工程(f)は、前記回路形成基板から前記剥型層3及び/又は前記銅箔4を除去する工程である。工程(f)を経ると、図1Hに示すように、第1の配線導体5(内層)が第2の絶縁樹脂層6中に埋設されており、第1の配線導体5(内層)と第2の配線導体8(外層)とが電気的に接合された半導体素子搭載用の回路形成基板10を形成することができる。工程(f)においては、例えば、前記剥型層及び/又は前記銅箔(好ましくは、極薄銅箔)の除去を硫酸系又は過酸化水素系エッチング液を用いて除去することができる。例えば、工程(e)において、第1の絶縁樹脂層が剥型層との界面において剥離された場合、及び、剥型層が破壊されてその一部が第1の絶縁樹脂層と共に剥離された場合には、除去工程(f)において剥型層の全体又はその一部及び銅箔が除去される。また、工程(e)において第1の絶縁樹脂層が剥型層と共に剥型層と銅箔との界面で剥離された場合、除去工程(f)においては銅箔のみが除去されることとなる。硫酸系又は過酸化水素系エッチング液は、特に限定されず、当業界で使用されているものを適宜選択して使用することができる。
工程(g)は、前記回路形成基板に前記した支持体をプレスして積層する工程である。具体的には、回路形成基板の第2の配線導体8が形成された面に、支持体の耐熱フィルム層11が接するように配置した後、プレスする。工程(g)を経ると、図1Iに示すように、回路形成基板の第2の配線導体が形成された面に支持体が積層された積層体20が形成される。なお、図1Iに示した図は、回路形成基板の片面にソルダーレジストを塗布してソルダーレジスト層9を形成した後、支持体をプレスして積層した場合の積層体を示すが、回路形成基板の両面にソルダーレジスト層が形成された構造体又はソルダーレジスト層9を形成せずに、工程(f)から直接工程(g)を実施した構造体を使用してもよい。
工程(h)は、前記回路形成基板の配線導体上に半導体素子を実装する工程である。工程(h)を経ると、図1Jに示すように、半導体素子が実装された積層体が形成される。図1Jは、第1の配線導体上に、はんだボール13を介してペアチップ14が実装され、更に、モールド樹脂15によって樹脂封止されている。
工程(i)は、前記回路形成基板から前記支持体を剥離する工程である。工程(i)を経ると、図1Kに示すように、半導体素子が実装された積層体から支持体が剥離され、半導体素子実装基板30を得ることができる。支持体を剥離する手段は物理的手段又は化学的手段のいずれも採用することができるが、例えば、耐熱フィルム層に物理的な力を加えて、物理的に支持体を剥離することが好ましい。
本発明を実施するための第2の形態(実施形態2)における半導体素子実装基板の製造方法は、以下の工程を含む。
(a)第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程
(b)前記回路形成用支持基板の前記銅箔上に、第1の配線導体を形成する工程
(c)前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程
(d)前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて第2の配線導体を形成する工程
(j)前記第1及び第2の配線導体が形成された回路形成基板に前記支持体をプレスして積層する工程
(k)前記支持体が積層された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程
(l)前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程
(h)前記回路形成基板の前記配線導体上に半導体素子を実装する工程
(i)前記回路形成基板から前記支持体を剥離する工程
ここで、工程(a)~(d)、(h)、(i)は、前記した実施形態1における各工程と同様であるので、説明を省略する。
なお、実施形態2においても、実施形態1と同様に、3層構造以上(3層構造、4層構造、・・・n層構造)のビルドアップ構造を有する半導体素子搭載用パッケージ基板を形成してもよい。すなわち、前記工程(d)と前記工程(e)の間に、前記第1及び第2の配線導体が形成された回路形成基板に対して、絶縁樹脂層積層工程及び配線導体形成工程を繰り返し行い、ビルドアップ構造を形成する工程を更に含んでいてもよい。
工程(j)は、前記第1及び第2の配線導体が形成された回路形成基板(図2A)に前記支持体をプレスして積層する工程である。具体的には、回路形成基板の第2の配線導体8が形成された面に、支持体の耐熱フィルム層11が接するように配置した後、プレスする。工程(j)を経ると、図2Bに示すように、回路形成基板の第2の配線導体が形成された面に支持体が積層された積層体が形成される。なお、図2Bに示した図は、回路形成基板にソルダーレジストを塗布してソルダーレジスト層9を形成した後、支持体をプレスして積層した場合の積層体を示すが、ソルダーレジスト層を形成せずに、工程(d)から直接工程(j)を実施してもよい。ソルダーレジスト層の形成する方法は、前記のとおりである。
支持体をプレスする方法としては、前記した工程(g)と同様である。
工程(k)は、前記支持体が積層された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程である。工程(k)を経ると、図2Cに示すように、剥型層3との界面において第1の絶縁樹脂層が剥離され、剥型層3と銅箔4上に、第1の配線導体5、第2の絶縁樹脂層6及び第2の配線導体8が積層し、第2の配線導体が形成された面に支持体が積層された積層体が形成される。
工程(l)は、前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程である。工程(l)を経ると、図2Dに示すように、第1の配線導体5(内層)が第2の絶縁樹脂層6中に埋設されており、第1の配線導体5(内層)と第2の配線導体8(外層)とが電気的に接合された半導体素子搭載用の回路形成基板に支持体が積層された積層体20を形成することができる。工程(l)においては、例えば、前記剥型層及び/又は前記極薄銅箔の除去を硫酸系又は過酸化水素系エッチング液を用いて除去することができる。例えば、工程(k)において、第1の絶縁樹脂層が剥型層との界面において剥離された場合、及び、剥型層が破壊されてその一部が第1の絶縁樹脂層と共に剥離された場合には、除去工程(l)において剥型層の全体又はその一部及び銅箔が除去される。また、工程(k)において第1の絶縁樹脂層が剥型層と共に剥型層と銅箔との界面で剥離された場合、除去工程(l)においては銅箔のみが除去されることとなる。硫酸系又は過酸化水素系エッチング液は、特に限定されず、当業界で使用されているものを適宜選択して使用することができる。
なお、本発明はこれらの実施形態に特に限定されることはなく、前記した実施形態1及び実施形態2以外のその実施形態も包含する。
<支持体の作製>
ビスマレイミドトリアジン樹脂(BT樹脂)をガラスクロス(ガラス繊維)に含浸させてBステージとしたプリプレグ(厚さ0.100mm:三菱ガス化学(株)製、製品名:GHPL-830NS ST56)の片面に、厚さ27μmの接着層付きポリイミドフィルム(接着層の厚さ:15μm、ニッカン工業株式会社製、製品名:CISV)を、接着層面が絶縁樹脂層と接するように配置し、もう一方の面に厚さ18μmの銅箔(三井金属鉱業株式会社製、製品名:3EC-VLP)を配置し、温度80±2℃、圧力1.0±0.2MPa、保持時間3分間の条件にて真空プレスを実施し、支持体(a)(厚さ145μm)を作製した。
ビスマレイミドトリアジン樹脂(BT樹脂)をガラスクロス(ガラス繊維)に含浸させてBステージとしたプリプレグ(厚さ0.100mm:三菱ガス化学(株)製、製品名:GHPL-830NS ST56)の両面に、厚さ12μmの銅箔にシラン化合物で構成された剥型層が塗布により形成された剥型層付銅箔(JX日鉱日石金属株式会社製、製品名:PCS)を、剥型層面が前記プリプレグと接するように配置し、温度220±2℃、圧力5±0.2MPa、保持時間60分間の条件にて真空プレスを実施した。その後、過水硫酸系のソフトエッチング液を用いたエッチングにより前記銅箔の厚さを3μmに調整して、第1の絶縁樹脂層の両面に剥型層と銅箔とがこの順で設けられた回路形成用支持基板を作製した。
回路形成用支持基板に、日立ビアメカニクス株式会社製のルータ加工機を用いてガイド穴を形成し、その後、過水硫酸系のソフトエッチング液を用いて表面を1~2μmエッチングした。次いで、温度110±10℃、圧力0.50±0.02MPaの条件で、ドライフィルムレジストNIT225(ニチゴー・モートン株式会社製、製品名)をラミネートした。ドライフィルムレジストへの回路パターンの焼付けを、前記ガイド穴を基準として平行露光機にて実施した後、1%炭酸ナトリウム水溶液を用いてドライフィルムレジストを現像し、めっき用レジストパターンを形成した。次いで、硫酸銅濃度60~80g/L、硫酸濃度150~200g/Lの硫酸銅めっきラインにて15~20μmほどのパターン電解銅めっき(電解銅めっき)を施し、第1の配線導体を形成した。その後、アミン系のレジスト剥離液を用いてドライフィルムレジストを剥離除去した。
絶縁樹脂との密着力を得るため、第1の配線導体(銅パターン)表面を、銅表面粗化液CZ-8100(メック株式会社製、製品名)を用いて粗化処理を施した。次いで、第1の配線導体が形成された回路形成用支持基板の両面に、ビスマレイミドトリアジン樹脂(BT樹脂)をガラスクロス(ガラス繊維)に含浸させてBステージとしたプリプレグ(厚さ0.100mm:三菱ガス化学(株)製、製品名:GHPL-830NS ST56)を配置した。次いで、プリプレグ上に厚さ18μmのキャリア銅箔付極薄銅箔(極薄銅箔(金属層);厚さ2μm:三井金属鉱業株式会社製、製品名:MTEx)を、キャリア銅箔側がプリプレグと接するように配置し、圧力2.5±0.2MPa、温度220±2℃、保持時間60分間の条件で、真空プレスした。その後、厚さ18μmのキャリア銅箔を剥離して、第1の配線導体上に第2の絶縁樹脂層と厚さ2μmの極薄銅箔とが積層された回路形成用支持基板を得た。
第1の配線導体上に第2の絶縁樹脂層と金属層とが積層された回路形成用支持基板の両面に、炭酸ガスレーザー加工機LC-1C/21(日立ビアメカニクス株式会社製、製品名)を用いて、ビーム照射径Φ0.21mm、周波数500Hz、パルス幅10μs、照射回数7ショットの条件にて1穴ずつ加工し、金属層を介して第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成した。
第2の配線導体を形成した後、剥型層付銅箔と第1の絶縁樹脂層(プリプレグ層)の境界部に物理的な力を加えて、第1の配線導体及び第2の配線導体が形成された回路形成用支持基板から、第1の絶縁樹脂層(プリプレグ層)を剥離し、一組の積層体とした。
剥離工程(e)において、第1の絶縁樹脂層(プリプレグ層)を剥離した後、極薄銅箔と剥型層とを、過水硫酸系のソフトエッチング液を用いて除去した。その後、10μmのソルダーレジストを形成し、金めっき仕上げを行った。
除去工程(f)において、10μmのソルダーレジストを形成し、金めっき仕上げを行った回路形成基板の片側を支持体(a)のポリイミド層が接するように配置し、温度160±2℃、圧力3.0±0.2MPa、保持時間60分間の条件にて真空プレスを実施し、積層体を作製した。
工程(g)において得られた積層体をパッケージサイズに切断加工し、半導体素子搭載用パッケージ基板を得た。次いで金めっき層上に半田ボールを搭載して約260℃にてリフローを行い、半田ボールが形成された多層プリント配線板を作製した。その後、得られた多層プリント配線板とアルミ電極部に金ワイヤのボールボンディング法によって金バンプを形成したベアチップとを位置合せし、多層プリント配線板上にベアチップをマウントした。次いで、ベアチップをマウントした多層プリント配線板を約260℃でリフローしてはんだ接続を行った後、洗浄し、モールド樹脂にて樹脂封止を行った。その後、ソルダーレジスト層とポリイミド層の境界部に物理的な力を加えて、多層プリント配線板から支持体(a)を剥離して、半導体素子実装基板を作製した。
<工程(c)>
実施例1における工程(a)及び工程(b)を行い、絶縁樹脂層との密着力を得るため、第1の配線導体(銅パターン)表面を、銅表面粗化液CZ-8100(メック株式会社製、製品名)を用いて粗化処理を施した。次いで、第1の配線導体が形成された回路形成用支持基板の両面に、ビスマレイミドトリアジン樹脂(BT樹脂)を厚さ18μmのキャリア銅箔付極薄銅箔(極薄銅箔(金属層);厚さ2μm:三井金属鉱業株式会社製、製品名:MTEx)に塗布してBステージ化した樹脂付き銅箔(厚さ15μm:三菱ガス化学(株)製、製品名:CRS-381 NSI)を配置し、圧力2.5±0.2MPa、温度220±2℃、保持時間60分間の条件で、真空プレスした。その後、厚さ18μmのキャリア銅箔を剥離して、第1の配線導体上に第2の絶縁樹脂層と厚さ2μmの極薄銅箔とが積層された回路形成用支持基板を得た。
第1の配線導体上に第2の絶縁樹脂層と金属層とが積層された回路形成用支持基板の両面に、炭酸ガスレーザー加工機LC-1C/21(日立ビアメカニクス株式会社製、製品名)を用いて、ビーム照射径Φ0.21mm、周波数500Hz、パルス幅10μs、照射回数7ショットの条件にて1穴ずつ加工し、金属層を介して第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成した。
次いで非貫通孔が形成された回路形成用支持基板に対し、温度80±5℃、濃度55±10g/Lの過マンガン酸ナトリウム水溶液を用いてデスミア処理を施し、更に、無電解銅めっきにて0.4~0.8μmの厚みのめっきを実施した後、電解銅めっきにて15~20μmの厚みのめっきを実施した。これにより、非貫通孔の内壁がめっきによって接続され、第1の配線導体(内層)と金属層(外層)とが、非貫通孔内壁のめっきによって電気的に接続されたことになる。
次に、基板表面(金属層)の整面を実施し、温度110±10℃、圧力0.50±0.02MPaの条件でドライフィルムレジストNIT225(ニチゴー・モートン株式会社製、製品名)をラミネートした。その後、ネガ型マスクを張り合わせた後、平行露光機を用いて回路パターンを焼付け、その後、1%炭酸ナトリウム水溶液を用いてドライフィルムレジストを現像してエッチングレジストを形成した。次いで、エッチングレジストのない部分の銅を塩化第二鉄水溶液で除去した後、水酸化ナトリウム水溶液を用いてドライフィルムレジストを除去し、第2の配線導体を形成した。
第2の配線導体を形成した後、第2の配線導体上に10μmのソルダーレジストを形成し、剥型層付銅箔と第1の絶縁樹脂層(プリプレグ層)の境界部に物理的な力を加えて、第1の配線導体及び第2の配線導体が形成された回路形成用支持基板から、第1の絶縁樹脂層(プリプレグ層)を剥離し、一組の積層体とした。
剥離工程(e)において、第1の絶縁樹脂層(プリプレグ層)を剥離した後、極薄銅箔と剥型層とを、過水硫酸系のソフトエッチング液を用いて除去した。その後、10μmのソルダーレジストを形成し、金めっき仕上げを行った。
除去工程(f)において、10μmのソルダーレジストを形成し、金めっき仕上げを行った回路形成基板の片側を支持体(a)のポリイミド部が接するように配置し、温度160±2℃、圧力3.0±0.2MPa、保持時間60分間の条件にて真空プレスを実施し、積層体を作製した。
工程(g)において得られた積層体をパッケージサイズに切断加工し、半導体素子搭載用パッケージ基板を得た。次いで金めっき層上に半田ボールを搭載して約260℃にてリフローを行い、半田ボールが形成された多層プリント配線板を作製した。その後、得られた多層プリント配線板とアルミ電極部に金ワイヤのボールボンディング法によって金バンプを形成したベアチップとを位置合せし、多層プリント配線板上にベアチップをマウントした。次いで、ベアチップをマウントした多層プリント配線板を約260℃でリフローしてはんだ接続を行った後、洗浄し、モールド樹脂にて樹脂封止を行った。その後、ソルダーレジスト層とポリイミド層の境界部に物理的な力を加えて、多層プリント配線板から支持体(a)を剥離して、半導体素子実装基板を作製した。
<工程(j)>
実施例2における工程(a)から工程(d)までを順次行い、第2の配線導体上に10μmのソルダーレジストを形成し、金めっき仕上げを行った。その後、回路形成用支持基板の片側を支持体(a)のポリイミド部が接するように配置し、温度160±2℃、圧力3.0±0.2MPa、保持時間60分間の条件にて真空プレスを実施し、積層体を作製した。
剥離工程において、積層体から第1の絶縁樹脂層(プリプレグ層)を剥離した後、極薄銅箔と剥型層とを、過水硫酸系のソフトエッチング液を用いて除去した。その後、10μmのソルダーレジストを形成した。
工程(l)において得られた積層体をパッケージサイズに切断加工し、半導体素子搭載用パッケージ基板を得た。次いで金めっき層上に半田ボールを搭載して約260℃にてリフローを行い、半田ボールが形成された多層プリント配線板を作製した。その後、得られた多層プリント配線板とアルミ電極部に金ワイヤのボールボンディング法によって金バンプを形成したベアチップとを位置合せし、多層プリント配線板上にベアチップをマウントした。次いで、ベアチップをマウントした多層プリント配線板を約260℃でリフローしてはんだ接続をおこなった後、洗浄し、モールド樹脂にて樹脂封止を行った。その後、ソルダーレジスト層とポリイミド層の境界部に物理的な力を加えて、多層プリント配線板から支持体(a)を剥離して、半導体素子実装基板を作製した。
支持体(a)を用いずに、実施例1における工程(a)から工程(f)、工程(h)及び工程(i)までを順次行い、半導体素子搭載用パッケージ基板を作製した(厚み60μm)。その後、金めっき層上に半田ボールを搭載して約260℃にてリフローを行ったが、基板が薄く剛性も小さいため、基板が破損してしまった。
2・・・第1の絶縁樹脂層
3・・・剥型層
4・・・銅箔
5・・・第1の配線導体
6・・・第2の絶縁樹脂層
7・・・金属層
8・・・第2の配線導体
9・・・ソルダーレジスト層
10・・・回路形成基板
11・・・耐熱フィルム層
12・・・樹脂層
13・・・はんだボール
14・・・ベアチップ
15・・・モールド樹脂
20・・・積層体
30・・・半導体素子実装基板
Claims (19)
- 耐熱フィルム層と、樹脂層と、含む支持体であって、
前記樹脂層の少なくとも一方の面(第1の面)に前記耐熱フィルム層が積層されており、
前記樹脂層が半硬化状態(Bステージ)である、支持体。 - 前記樹脂層の前記耐熱フィルム層が積層された面とは反対側の面(第2の面)に、銅箔が更に積層された、請求項1に記載の支持体。
- 前記耐熱フィルム層は、ポリイミド樹脂、ポリアミドイミド樹脂、ナイロン樹脂及びフッ素系樹脂からなる群から選択される1種以上の樹脂を含む、請求項1又は2に記載の支持体。
- 前記耐熱フィルム層は接着層付き耐熱フィルム層であって、前記接着層は、フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂からなる群から選択される1種以上の樹脂を含む、請求項1~3のいずれか一項に記載の支持体。
- 10~400μmの厚さを有する、請求項1~4のいずれか一項に記載の支持体。
- 前記樹脂層はガラスクロスに熱硬化性樹脂を含浸させたプリプレグを含む、請求項1~5のいずれか一項に記載の支持体。
- 前記熱硬化性樹脂は、フェノール樹脂、エポキシ樹脂、シアネート樹脂、マレイミド樹脂、ビスマレイミドトリアジン樹脂、イソシアネート樹脂、ベンゾシクロブテン樹脂及びビニル樹脂からなる群から選択される1種以上の樹脂を含む、請求項6に記載の支持体。
- 前記耐熱フィルム層は前記樹脂層よりも表面積が小さい、請求項1~7のいずれか一項に記載の支持体。
- 請求項1~8のいずれか一項に記載の支持体を用いた半導体素子実装基板の製造方法であって、
第1及び第2の配線導体が形成された回路形成基板に前記支持体をプレスして積層した後、前記配線導体上に半導体素子を実装する工程を含む、製造方法。 - 以下の工程を含む、請求項9に記載の半導体素子実装基板の製造方法。
(a)第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程
(b)前記回路形成用支持基板の前記銅箔上に、第1の配線導体を形成する工程
(c)前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程
(d)前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて第2の配線導体を形成する工程
(e)前記第1及び第2の配線導体が形成された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程
(f)前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程
(g)前記回路形成基板に前記支持体をプレスして積層する工程
(h)前記回路形成基板の前記配線導体上に半導体素子を実装する工程
(i)前記回路形成基板から前記支持体を剥離する工程 - 前記工程(d)と前記工程(e)の間に、前記第1及び第2の配線導体が形成された回路形成基板に対して、絶縁樹脂層積層工程及び配線導体形成工程を繰り返し行い、ビルドアップ構造を形成する工程を更に含む、請求項10に記載の半導体素子実装基板の製造方法。
- 前記工程(f)と前記工程(g)の間に、ソルダーレジスト層を形成する工程を更に含む、請求項10又は11に記載の半導体素子実装基板の製造方法。
- 前記ソルダーレジスト層を形成する工程の後、金めっき層を形成する工程を更に含む、請求項12に記載の半導体素子実装基板の製造方法。
- 前記工程(d)と前記工程(e)の間に、ソルダーレジスト層を形成する工程を含む、請求項10又は11に記載の半導体素子実装基板の製造方法。
- 前記ソルダーレジスト層を形成する工程の後、金めっき層を形成する工程を更に含む、請求項14に記載の半導体素子実装基板の製造方法。
- 以下の工程を含む、請求項9に記載の半導体素子実装基板の製造方法。
(a)第1の絶縁樹脂層と、剥型層と、銅箔と、をこの順で含む回路形成用支持基板を形成する工程
(b)前記回路形成用支持基板の前記銅箔上に、第1の配線導体を形成する工程
(c)前記第1の配線導体と接するように第2の絶縁樹脂層を配置し、前記第2の絶縁樹脂層を加熱及び加圧して積層する工程
(d)前記第2の絶縁樹脂層に、前記第1の配線導体に達する非貫通孔を形成し、前記非貫通孔の内壁を電解銅めっき及び/又は無電解銅めっきによって接続させて第2の配線導体を形成する工程
(j)前記第1及び第2の配線導体が形成された回路形成基板に前記支持体をプレスして積層する工程
(k)前記支持体が積層された回路形成基板から、前記第1の絶縁樹脂層を剥離する工程
(l)前記回路形成基板から前記剥型層及び/又は前記銅箔を除去する工程
(h)前記回路形成基板の前記配線導体上に半導体素子を実装する工程
(i)前記回路形成基板から前記支持体を剥離する工程 - 前記工程(d)と前記工程(e)の間に、前記第1及び第2の配線導体が形成された回路形成基板に対して、絶縁樹脂層積層工程及び配線導体形成工程を繰り返し行い、ビルドアップ構造を形成する工程を更に含む、請求項16に記載の半導体素子実装基板の製造方法。
- 前記工程(l)と前記工程(h)の間に、ソルダーレジスト層を形成する工程を更に含む、請求項16又は17に記載の半導体素子実装基板の製造方法。
- 前記ソルダーレジスト層を形成する工程の後、金めっき層を形成する工程を更に含む、請求項18に記載の半導体素子実装基板の製造方法。
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