DE69833743D1 - Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen - Google Patents

Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen

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Publication number
DE69833743D1
DE69833743D1 DE69833743T DE69833743T DE69833743D1 DE 69833743 D1 DE69833743 D1 DE 69833743D1 DE 69833743 T DE69833743 T DE 69833743T DE 69833743 T DE69833743 T DE 69833743T DE 69833743 D1 DE69833743 D1 DE 69833743D1
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DE
Germany
Prior art keywords
manufacturing
high voltage
semiconductor devices
edge structure
voltage semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69833743T
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English (en)
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DE69833743T2 (de
Inventor
Ferruccio Frisina
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STMicroelectronics SRL
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STMicroelectronics SRL
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Publication of DE69833743D1 publication Critical patent/DE69833743D1/de
Publication of DE69833743T2 publication Critical patent/DE69833743T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69833743T 1998-12-09 1998-12-09 Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen Expired - Lifetime DE69833743T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98830739A EP1011146B1 (de) 1998-12-09 1998-12-09 Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen

Publications (2)

Publication Number Publication Date
DE69833743D1 true DE69833743D1 (de) 2006-05-04
DE69833743T2 DE69833743T2 (de) 2006-11-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE69833743T Expired - Lifetime DE69833743T2 (de) 1998-12-09 1998-12-09 Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen

Country Status (4)

Country Link
US (2) US6300171B1 (de)
EP (1) EP1011146B1 (de)
JP (1) JP4597293B2 (de)
DE (1) DE69833743T2 (de)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69833743T2 (de) * 1998-12-09 2006-11-09 Stmicroelectronics S.R.L., Agrate Brianza Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen
JP4447065B2 (ja) * 1999-01-11 2010-04-07 富士電機システムズ株式会社 超接合半導体素子の製造方法
JP2001119022A (ja) * 1999-10-20 2001-04-27 Fuji Electric Co Ltd 半導体装置及びその製造方法
JP4765012B2 (ja) * 2000-02-09 2011-09-07 富士電機株式会社 半導体装置及びその製造方法
US6642558B1 (en) * 2000-03-20 2003-11-04 Koninklijke Philips Electronics N.V. Method and apparatus of terminating a high voltage solid state device
DE10061310A1 (de) * 2000-12-08 2002-06-27 Infineon Technologies Ag Halbleiterbauelement mit erhöhter Durchbruchspannung sowie dazugehöriges Herstellungsverfahren
JP4785335B2 (ja) 2001-02-21 2011-10-05 三菱電機株式会社 半導体装置およびその製造方法
JP3731520B2 (ja) * 2001-10-03 2006-01-05 富士電機デバイステクノロジー株式会社 半導体装置及びその製造方法
US20030099997A1 (en) * 2001-10-24 2003-05-29 Bestor Timothy H. Method for gene identification based on differential DNA methylation
GB0214618D0 (en) * 2002-06-25 2002-08-07 Koninkl Philips Electronics Nv Semiconductor device with edge structure
US7037814B1 (en) * 2003-10-10 2006-05-02 National Semiconductor Corporation Single mask control of doping levels
US7166890B2 (en) * 2003-10-21 2007-01-23 Srikant Sridevan Superjunction device with improved ruggedness
US20050259368A1 (en) * 2003-11-12 2005-11-24 Ted Letavic Method and apparatus of terminating a high voltage solid state device
US20050110038A1 (en) * 2003-11-21 2005-05-26 Hamerski Roman J. High voltage semiconductor device having current localization region
KR20070038945A (ko) * 2003-12-19 2007-04-11 써드 디멘존 세미컨덕터, 인코포레이티드 수퍼 접합 장치의 제조 방법
WO2005065140A2 (en) * 2003-12-19 2005-07-21 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
JP4999464B2 (ja) * 2003-12-19 2012-08-15 サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド 広いメサを備えた超接合ディバイスの製造方法
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
JP4417962B2 (ja) * 2003-12-19 2010-02-17 サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド 超接合デバイスの製造での平坦化方法
JP4904673B2 (ja) 2004-02-09 2012-03-28 富士電機株式会社 半導体装置および半導体装置の製造方法
JP4865194B2 (ja) * 2004-03-29 2012-02-01 ルネサスエレクトロニクス株式会社 超接合半導体素子
JP2006005275A (ja) * 2004-06-21 2006-01-05 Toshiba Corp 電力用半導体素子
JP2006073740A (ja) * 2004-09-01 2006-03-16 Toshiba Corp 半導体装置及びその製造方法
US7439583B2 (en) * 2004-12-27 2008-10-21 Third Dimension (3D) Semiconductor, Inc. Tungsten plug drain extension
TWI401749B (zh) 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
EP1696490A1 (de) * 2005-02-25 2006-08-30 STMicroelectronics S.r.l. Ladungskompensationshalbleiterbauelement und dazugehoriges Herstellungsverfahren
EP1710843B1 (de) * 2005-04-04 2012-09-19 STMicroelectronics Srl Integriertes Leistungsbauelement
JP2008538659A (ja) * 2005-04-22 2008-10-30 アイスモス テクノロジー コーポレイション 酸化物で内面が覆われた溝を有する超接合素子と酸化物で内面を覆われた溝を有する超接合素子を製造するための方法
JP2007012858A (ja) * 2005-06-30 2007-01-18 Toshiba Corp 半導体素子及びその製造方法
EP1742259A1 (de) * 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Halbleiter-Leistungsbauelement mit Mehrfach-Drain-Struktur und entsprechendes Herstellungsverfahren
US7446018B2 (en) * 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US7659588B2 (en) * 2006-01-26 2010-02-09 Siliconix Technology C. V. Termination for a superjunction device
JP2007221024A (ja) * 2006-02-20 2007-08-30 Toshiba Corp 半導体装置
US8304311B2 (en) * 2006-04-11 2012-11-06 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device
WO2007122646A1 (en) * 2006-04-21 2007-11-01 Stmicroelectronics S.R.L. Process for manufacturing a power semiconductor device and corresponding power semiconductor device
US7737469B2 (en) * 2006-05-16 2010-06-15 Kabushiki Kaisha Toshiba Semiconductor device having superjunction structure formed of p-type and n-type pillar regions
JP5342752B2 (ja) * 2006-05-16 2013-11-13 株式会社東芝 半導体装置
JP5188037B2 (ja) * 2006-06-20 2013-04-24 株式会社東芝 半導体装置
JP2007311669A (ja) * 2006-05-22 2007-11-29 Toshiba Corp 半導体装置及びその製造方法
EP1873837B1 (de) * 2006-06-28 2013-03-27 STMicroelectronics Srl Leistungs-Halbleiterbauelement mit einer Randabschlussstruktur und Verfahren zu seiner Herstellung
US7944018B2 (en) * 2006-08-14 2011-05-17 Icemos Technology Ltd. Semiconductor devices with sealed, unlined trenches and methods of forming same
US7723172B2 (en) 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US8012806B2 (en) 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
JP2009088345A (ja) 2007-10-01 2009-04-23 Toshiba Corp 半導体装置
US20090166729A1 (en) * 2007-12-27 2009-07-02 Infineon Technologies Austria Ag Power semiconductor having a lightly doped drift and buffer layer
CN101510557B (zh) 2008-01-11 2013-08-14 艾斯莫斯技术有限公司 具有电介质终止的超结半导体器件及制造该器件的方法
US7846821B2 (en) 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US7795045B2 (en) * 2008-02-13 2010-09-14 Icemos Technology Ltd. Trench depth monitor for semiconductor manufacturing
US8030133B2 (en) * 2008-03-28 2011-10-04 Icemos Technology Ltd. Method of fabricating a bonded wafer substrate for use in MEMS structures
US8101997B2 (en) * 2008-04-29 2012-01-24 Infineon Technologies Austria Ag Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production
IT1397574B1 (it) * 2008-12-29 2013-01-16 St Microelectronics Rousset Dispositivo a semiconduttore di potenza di tipo multi-drain e relativa struttura di terminazione di bordo
JP5484741B2 (ja) * 2009-01-23 2014-05-07 株式会社東芝 半導体装置
JP4998524B2 (ja) * 2009-07-24 2012-08-15 サンケン電気株式会社 半導体装置
US8901652B2 (en) * 2009-09-01 2014-12-02 Stmicroelectronics S.R.L. Power MOSFET comprising a plurality of columnar structures defining the charge balancing region
US20110049638A1 (en) 2009-09-01 2011-03-03 Stmicroelectronics S.R.L. Structure for high voltage device and corresponding integration process
US9230810B2 (en) * 2009-09-03 2016-01-05 Vishay-Siliconix System and method for substrate wafer back side and edge cross section seals
US8466510B2 (en) * 2009-10-30 2013-06-18 Alpha And Omega Semiconductor Incorporated Staggered column superjunction
US8436428B2 (en) * 2009-12-28 2013-05-07 Stmicroelectronics S.R.L. Integrated common source power MOSFET device, and manufacturing process thereof
US8154078B2 (en) * 2010-02-17 2012-04-10 Vanguard International Semiconductor Corporation Semiconductor structure and fabrication method thereof
JP5537996B2 (ja) * 2010-03-03 2014-07-02 株式会社東芝 半導体装置
CN101826554A (zh) * 2010-05-04 2010-09-08 无锡新洁能功率半导体有限公司 具有超结结构的半导体器件及其制造方法
CN103026461B (zh) 2010-07-26 2016-10-26 意法半导体股份有限公司 用于填充半导体材料本体中深沟槽的工艺以及根据相同工艺所得的半导体器件
CN102386224A (zh) * 2010-08-30 2012-03-21 苏州博创集成电路设计有限公司 一种纵向超结金属氧化物场效应晶体管器件及其制备方法
US9490372B2 (en) 2011-01-21 2016-11-08 Semiconductor Components Industries, Llc Method of forming a semiconductor device termination and structure therefor
KR101876573B1 (ko) * 2011-12-23 2018-07-10 매그나칩 반도체 유한회사 반도체 소자 및 그 제조 방법
US8946814B2 (en) 2012-04-05 2015-02-03 Icemos Technology Ltd. Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates
US9112026B2 (en) 2012-10-17 2015-08-18 Semiconductor Components Industries, Llc Semiconductor devices and method of making the same
JP5983415B2 (ja) * 2013-01-15 2016-08-31 住友電気工業株式会社 炭化珪素半導体装置
JP6168513B2 (ja) * 2013-05-13 2017-07-26 ローム株式会社 半導体装置およびその製造方法
ITTO20130410A1 (it) 2013-05-22 2014-11-23 St Microelectronics Srl Dispositivo di potenza a supergiunzione e relativo procedimento di fabbricazione
KR101795828B1 (ko) 2013-09-17 2017-11-10 매그나칩 반도체 유한회사 초접합 반도체 소자 및 제조 방법
US9484404B2 (en) 2014-01-29 2016-11-01 Stmicroelectronics S.R.L. Electronic device of vertical MOS type with termination trenches having variable depth
US9324784B2 (en) 2014-04-10 2016-04-26 Semiconductor Components Industries, Llc Electronic device having a termination region including an insulating region
US9343528B2 (en) 2014-04-10 2016-05-17 Semiconductor Components Industries, Llc Process of forming an electronic device having a termination region including an insulating region
DE102014005879B4 (de) * 2014-04-16 2021-12-16 Infineon Technologies Ag Vertikale Halbleitervorrichtung
CN104183627B (zh) * 2014-08-29 2017-05-03 电子科技大学 一种超结功率器件终端结构
JP2015164218A (ja) * 2015-05-12 2015-09-10 株式会社東芝 半導体装置
JP6441190B2 (ja) * 2015-09-11 2018-12-19 株式会社東芝 半導体装置の製造方法
JP6693131B2 (ja) * 2016-01-12 2020-05-13 富士電機株式会社 半導体装置
CN105720089B (zh) * 2016-02-16 2018-10-26 上海华虹宏力半导体制造有限公司 超级结及其制造方法
JP6855700B2 (ja) * 2016-08-05 2021-04-07 富士電機株式会社 半導体装置およびその製造方法
US9899508B1 (en) 2016-10-10 2018-02-20 Stmicroelectronics S.R.L. Super junction semiconductor device for RF applications, linear region operation and related manufacturing process
US10263070B2 (en) 2017-06-12 2019-04-16 Alpha And Omega Semiconductor (Cayman) Ltd. Method of manufacturing LV/MV super junction trench power MOSFETs
US11152251B2 (en) * 2017-07-31 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device having via formed by ion beam
IT201700113926A1 (it) 2017-10-10 2019-04-10 St Microelectronics Srl Dispositivo mosfet di potenza e relativo procedimento di fabbricazione
CN108054196B (zh) * 2017-12-08 2020-09-04 南京溧水高新创业投资管理有限公司 半导体功率器件的终端结构及其制作方法
IT201800006323A1 (it) 2018-06-14 2019-12-14 Dispositivo a semiconduttore del tipo a bilanciamento di carica, in particolare per applicazioni rf ad elevata efficienza, e relativo procedimento di fabbricazione
JP7056707B2 (ja) * 2020-09-18 2022-04-19 富士電機株式会社 半導体装置
CN112103188A (zh) * 2020-09-27 2020-12-18 江苏东海半导体科技有限公司 一种渐变超结终端及其制造方法
US20230411447A1 (en) * 2022-06-21 2023-12-21 K. Eklund Innovation Semiconductor device comprising a lateral super junction field effect transistor

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159060A (en) * 1981-03-26 1982-10-01 Nec Corp Semiconductor device
JPS592344A (ja) * 1982-06-28 1984-01-07 Nec Corp 半導体集積回路の製造方法
IT1214805B (it) 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
JPH01270346A (ja) * 1988-04-22 1989-10-27 Fuji Electric Co Ltd 半導体装置
JPH0310556U (de) * 1989-06-19 1991-01-31
US5070382A (en) * 1989-08-18 1991-12-03 Motorola, Inc. Semiconductor structure for high power integrated circuits
US5075739A (en) * 1990-01-02 1991-12-24 Motorola, Inc. High voltage planar edge termination using a punch-through retarding implant and floating field plates
EP0632503B1 (de) * 1993-07-01 2001-10-31 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess
US5594261A (en) * 1994-04-05 1997-01-14 Harris Corporation Device for isolating parallel sub-elements with reverse conducting diode regions
US5444272A (en) * 1994-07-28 1995-08-22 International Rectifier Corporation Three-terminal thyristor with single MOS-gate controlled characteristics
US5841197A (en) * 1994-11-18 1998-11-24 Adamic, Jr.; Fred W. Inverted dielectric isolation process
JPH08167714A (ja) * 1994-12-14 1996-06-25 Sanyo Electric Co Ltd 縦型ｍｏｓ半導体装置
US5969400A (en) * 1995-03-15 1999-10-19 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device
US5633180A (en) * 1995-06-01 1997-05-27 Harris Corporation Method of forming P-type islands over P-type buried layer
DE69534488D1 (de) * 1995-07-31 2006-02-09 St Microelectronics Srl Monolitische Hochspannungshalbleiteranordnung mit integrierter Randstruktur und Verfahren zur Herstellung
JPH0955496A (ja) * 1995-08-17 1997-02-25 Oki Electric Ind Co Ltd 高耐圧ｍｏｓトランジスタ及びその製造方法
JP3392665B2 (ja) * 1995-11-06 2003-03-31 株式会社東芝 半導体装置
DE69515876T2 (de) * 1995-11-06 2000-08-17 St Microelectronics Srl Leistungsbauelement in MOS-Technologie mit niedrigem Ausgangswiderstand und geringer Kapazität und dessen Herstellungsverfahren
KR100203306B1 (ko) * 1996-06-29 1999-06-15 김영환 반도체 소자의 제조방법
US5798187A (en) * 1996-09-27 1998-08-25 The Regents Of The University Of California Fuel cell with metal screen flow-field
KR100228331B1 (ko) * 1996-12-30 1999-11-01 김영환 반도체 소자의 삼중웰 제조 방법
US6225165B1 (en) * 1998-05-13 2001-05-01 Micron Technology, Inc. High density SRAM cell with latched vertical transistors
DE69833743T2 (de) * 1998-12-09 2006-11-09 Stmicroelectronics S.R.L., Agrate Brianza Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen

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