US20110049638A1 - Structure for high voltage device and corresponding integration process - Google Patents

Structure for high voltage device and corresponding integration process Download PDF

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US20110049638A1
US20110049638A1 US12868023 US86802310A US2011049638A1 US 20110049638 A1 US20110049638 A1 US 20110049638A1 US 12868023 US12868023 US 12868023 US 86802310 A US86802310 A US 86802310A US 2011049638 A1 US2011049638 A1 US 2011049638A1
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structure
conductivity
semiconductor
surface
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Mario Giuseppe Saggio
Domenico Murabito
Angelo Magri'
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STMicroelectronics SRL
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    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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Abstract

An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

Description

    PRIORITY CLAIM
  • The instant application claims priority to Italian Patent Application No. MI2009A001522, filed Sep. 1, 2009, which application is incorporated herein by reference in its entirety.
  • TECHNICAL FIELD
  • An embodiment relates to a structure for a high voltage device.
  • More specifically, an embodiment relates to a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, the epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized.
  • An embodiment also relates to an integration process of a structure for a high voltage device of the type which comprises the steps of:
  • realizing a semiconductor substrate having a first conductivity type;
    epitaxially growing on said semiconductor substrate an epitaxial layer having the first conductivity type; and
    realizing in said epitaxial layer at least one deep trench having a high aspect ratio in order to realize at least one column structure in said epitaxial layer.
  • An embodiment particularly, but not exclusively, relates to a vertical conduction MISFET device which is driven through a gate dielectric and the following description is made with reference to this field of application for convenience of explanation only.
  • SUMMARY
  • As it is well known, in the field of high-voltage power semiconductor devices, several efforts have been addressed to provide solutions that improve the efficiency of these devices, and in particular obtain an increase of the breakdown voltage (BV) and a reduction of the output or on resistance (Ron) thereof.
  • In the development trend following the evolution of the high-voltage power devices, the approach that many think has the best compromise between breakdown voltage and on resistance is the so called SuperJunction approach, which provides for realizing a plurality of three-dimensional structures (3D) as drain structures. Different manufacturing methods of these three-dimensional drain structures are aimed at realizing a structure integrating columns or column structures, in particular having a first conductivity type, for instance of the p type, able to counterbalance the opposite charge, in particular of the opposite conductivity type, for instance the n type, of the drain layer wherein said column structures are realized, in particular in the portion of said layer extending between subsequent pairs of column structures.
  • These devices, so called multi drain (MD), thus work on the basis of the charge balance concept within the drain structure, being considered as the column structures and the drain layer as a whole.
  • Known solutions are described, for instance, in commonly assigned U.S. Pat. Nos. 6,228,719, 6,300,171, 6,404,010, 6,586,798 and 7,498,619 which are incorporated by reference, and which, in particular, relate to vertical-conduction power semiconductor devices of the multi drain type.
  • The devices disclosed in these documents substantially comprise, within a drain epitaxial layer, of a first conductivity type, charge balanced column structures, having a second conductivity type, opposed than the first type.
  • In particular, the column structures are realized with a dopant concentration which is substantially equal and opposite to the dopant concentration of the drain layer, so as to obtain a substantial charge balance which allows obtaining high breakdown voltages. Advantageously, by using a drain layer which has a high dopant concentration, devices may be realized which have a low on resistance and thus reduced conduction losses.
  • Generally, making column structures comprises a sequence of steps of growing epitaxial layers of the first conductivity type, for instance of the N type, each step being followed by a dopant implantation of the second conductivity type, for instance of the P type.
  • Regions of the P type being so implanted are in particular realized so as to be stacked up in the depth development sense of the drain epitaxial layer wherein they are made and are subjected to a following diffusion process of the dopant atoms, in such a way to originate uniform column structures.
  • Above the drain epitaxial layer, in contact with the column structures, active regions of the high-voltage device are realized, in particular body wells, the column structures thus providing extensions of said body wells inside the drain layer.
  • In essence, multi drain devices so realized may combine a high cut-off voltage with reduced losses thanks to the charge balance between a conduction region, namely the drain region between the columns and the column structures extending into the drain layer, which allow increasing the concentration of such a conduction region, thus obtaining a strong reduction of conduction losses.
  • Other methods for realizing multi drain devices having a charge compensation are known, for example, from the articles: “A Novel Trench Concept for the Fabrication of Compensation Devices” to Rüb et al., ISPSD, Apr. 14-17, 2003, Cambridge, UK, “Oxide-Bypassed VDMOS (OBVDMOS): An Alternative to Superjunction High Voltage MOS Power Devices” to Liang et al., IEEE Electron Devices Letters, Vol. 22, No. 8, Aug. 2001, and “Experimental Results and Simulation Analysis of 250V Super Trench Power MOSFET (STM)” to Nitta et al., Mitsubishi Electric Co., ULSI Development Center, 12th International symposium on power semiconductor devices & Ics, Toulouse, May 22-25, 2000 as well as from U.S. Patent Application No. 2001/0055861 published on Dec. 27, 2001 in the name of Patti et al. and from U.S. Pat. No. 6,410,958 issued on Jun. 25, 2002 to Usui et al., all of the above references being incorporated by reference.
  • Although advantageous in several aspects, the known solutions to realize multi-drain devices may comprise a high number of process steps, thus possibly being difficult to implement. Moreover, it often occurs that the dopant profile in the conduction region is not constant.
  • Finally, these known solutions may not easily allow extending the voltage class of the multi-drain devices so obtained.
  • Therefore, an embodiment of the present disclosure is a structure for a high-voltage device having structural and functional characteristics which overcome at least one of the limits and drawbacks which still affect the devices realized according to the prior art.
  • An embodiment is a structure for a high-voltage device through a superjunction structure obtained by partially filling a deep trench having a high aspect ratio, in particular having a ratio between width and height less than 3/20, with an epitaxial layer doped in opposition with the preexisting semiconductor layer thus forming the column structures. The quantity of dopant being in the epitaxial layer would be the one counterbalancing the dopant being in the neighbouring conduction areas, i.e., the epitaxial layer outside the column structures. The structure also comprises a dielectric layer able to fill said deep trench, being partially filled by said epitaxial layer.
  • In an embodiment, the column structures are structures of the drain area and turn out to have a same periodicity of the active surface areas, being wells realizing body areas, each drain column structure being “fastened” to a corresponding body well.
  • In an embodiment, a structure for a high-voltage device comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprise high-aspect-ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed to said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
  • According to an embodiment, said epitaxial layer of said external portion is U-shaped and extends both on the wall and on the bottom of a corresponding column structure.
  • According to a further embodiment, said external portion could have a dopant concentration with a constant concentration dopant profile and with a transition zone towards said epitaxial layer outside said column structures having a smaller size than a thickness of a silicon epitaxial layer of said external portion.
  • Furthermore, according to an embodiment, said external portion may have a dopant concentration with a growing dopant profile towards an interface with said epitaxial layer outside said column structures.
  • According to an embodiment, said external portion may have a dopant concentration with a substantially constant concentration dopant profile.
  • Alternatively, said external portion may have a dopant concentration with a variable concentration profile having a maximum near said interface with said epitaxial layer.
  • According to another embodiment, the thickness of said external portion may be constant along its whole U-shaped profile.
  • According to another embodiment, said column structures may have a ratio between width and height less than 3/20.
  • According to yet another embodiment, said column structures may realize a first active area of said high voltage device and said high voltage device comprises at least a second active area which is realized in said active surface area and has at least one fastening zone with said first active area.
  • According to an embodiment, the said first active area may be fastened in correspondence with said fastening zone to a conduction portion of said first active area.
  • According to an embodiment, said conduction portion of said first active area may be an external portion of said column structures.
  • According to an embodiment, said high voltage device is a MOS transistor and said first active area is a drain area comprising said epitaxial layer and said column structures and said second active area is a body area.
  • According to an embodiment, said high-voltage device could comprise, in said active surface area, a plurality of body wells of said second type of conductivity, inside which corresponding plurality of source wells of said first type of conductivity are realized, as well as a plurality of gate structures, being realized between consecutive pairs of column structures, above a channel region being define in said epitaxial layer between said body wells and in contact with said source wells.
  • Yet according to an embodiment, said structure for a high-voltage device may further comprise a capping layer, being realized on said high-voltage device and in particular covering said gate structures.
  • According to an embodiment, said gate structures are chosen between planar type and trench gate type structures.
  • Moreover, according to an embodiment, said structure for a high-voltage device may further comprise contact surface structures being chosen between microtrench type or conventional structures.
  • According to an embodiment, said column structures may have a same periodicity with respect to said second active areas.
  • According to an embodiment, each of said column structures may have a width between approximately 1.5 and 4 um, for example approximately 2 um and a height between approximately 10 and 70 um, for example approximately 30 um.
  • According to an embodiment, said external portion may have a dopant concentration between approximately 1e15 and 1e17, for example approximately 1e16 at/cm3, and said epitaxial layer may have a dopant concentration between approximately 5e14 and 5e16, for example approximately 5e15.
  • Furthermore, according to an embodiment, said column structures may have a distance between approximately 2 um and 8 um, for example approximately 4 um.
  • According to an embodiment, said column structures may extend down to said semiconductor substrate.
  • According to an embodiment, said column structures may extend down to a prefixed distance from said semiconductor substrate.
  • According to an embodiment, said high-voltage device is chosen between a MOS transistor, a diode, and an IGBT device.
  • An embodiment of an integration process for a structure for a high voltage device comprises the steps of:
  • realizing a semiconductor substrate having a first conductivity type;
    epitaxially growing on said semiconductor substrate an epitaxial layer having said first conductivity type;
    realizing in said epitaxial layer at least one deep trench having a high aspect ratio in order to realize at least one column structure in said epitaxial layer;
    an epitaxial growing step within said trench of a silicon layer being doped and having a second conductivity type, opposed to said first conductivity type and having a dopant charge which counterbalances a dopant charge being in said epitaxial layer outside said column structures; and
    a filling step of said trench by means of a filling dielectric layer in order to realize a filling portion of said at least one column structure.
  • According to an embodiment, said epitaxial growing step within said trench may grow a silicon layer at least on the walls and on the bottom of said trench, thus realizing an U-shaped external portion of said at least one column structure
  • According to an embodiment, said epitaxial growing steps of said epitaxial layer on said semiconductor substrate and of said epitaxial layer within said trench may be realized with a limited thermal budget and with a process maximum temperature less than approximately 1100° C.
  • According to an embodiment, said epitaxial growing steps may realize said epitaxial layer within said trench with a dopant concentration comprised between approximately 1e15 and 1e17, for example 1e16 at/cm3, and said epitaxial layer on said semiconductor substrate with a dopant concentration comprised between approximately 5e14 and 5e16, for example approximately 5e15.
  • According to an embodiment, said column structures may realize a first active area of said high-voltage device and may comprise a step of realizing, in an active surface area of said structure, at least one second active area which has at least one fastening zone with said first active area.
  • According to an embodiment, said integration process may integrate a MOS transistor of the multi-drain type, by realizing, as the first active area, a drain area which comprises said epitaxial layer and said column structures and, as the second active area, a body area.
  • According to an embodiment, the integration process may integrate a diode by realizing, as the first active area, a cathode area and, as the second active area, an anode area.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Characteristics and advantages of at least one embodiment of a structure for a high-voltage device and corresponding integration process will be apparent from the following description, which is given by way of indicative and non-limiting example with reference to the annexed drawings.
  • FIG. 1 schematically shows a section view of an embodiment of a structure for a high-voltage device;
  • FIGS. 2A and 2B schematically show the dopant concentration profiles of different embodiments of the structure of FIG. 1;
  • FIGS. 3A-3D schematically show section views of the structure of FIG. 1 during different steps of an embodiment of an integration process.
  • DETAILED DESCRIPTION
  • With reference to such figures, and in particular to FIG. 1, 1 globally and schematically indicates an embodiment of a structure for a high-voltage device.
  • It is suitable to note that figures showing schematic portions of the integrate structure may not be drawn to scale, but are drawn in such a way to show features of at least one embodiment.
  • Moreover, process steps as herein below described may not form a complete process flow for manufacturing high-voltage devices. An embodiment may be reduced into practice using techniques for manufacturing high-voltage devices as currently used into the field, and, so a discussion of these conventional process steps may be omitted for brevity.
  • In an embodiment a structure 1 for a high-voltage device comprises a semiconductor substrate 2 covered by an epitaxial layer 3, having a first conductivity type, for example N type. A plurality of column structures 4 having a relatively high-aspect ratio, for example less than about 3/20, is realized in the epitaxial layer 3.
  • The structure 1 for a high-voltage device further includes an active surface area 5, wherein the active areas of the high-voltage device are realized, as will be discussed in the following description.
  • Each of the column structures 4 includes an external portion 6, for example an epitaxial silicon layer being suitably doped, as well as a filling portion 7, for example a dielectric layer, such as an oxide, being deposited inside the respective column structure 4 for, e.g., completely filling it. The epitaxial silicon layer of the external portion 6 is doped and has a second conductivity type, for example the P type.
  • The charge that is epitaxially inserted in order to realize the external portion 6 is such as to counterbalance the charge being in the epitaxial layer 3 outside the column structures 4. Moreover, the epitaxial layer that realizes the external portion 6 is on the walls and on the bottom of the corresponding column structure 4, which is realized, per the following description, starting from a trench being dug in the epitaxial layer 3, for example a deep trench having a high aspect ratio, i.e., a low ratio between width and height, for example less than about 3/20.
  • In the active surface area 5, a high-voltage device is realized, in a conventional manner, of the type comprising at least an active area 8.
  • The column structures 4 have respective fastening zones 12 with the active areas 8, having a same periodicity thereof.
  • In particular, an embodiment of the structure 1 for a high-voltage device comprises column structures 4 in turn realized by a U-shaped zone of semiconductor material, i.e., the external portion 6 of the epitaxial silicon, being suitably doped with a dopant of an opposite type with respect to the one of the neighboring semiconductor material, i.e., the epitaxial layer 3 outside the column structures 4, this U-shaped external portion 6 being in turn filled by a dielectric layer to form the filling portion 7.
  • It is suitable to note that, the U-shaped external portion 6 may have an approximately constant thickness and an approximately constant concentration dopant profile having a transition zone shifted towards the semiconductor material of the neighboring epitaxial layer 3, this zone having a smaller size than the thickness of the silicon epitaxial layer of the external portion 6 (in particular, extending for a distance that is less than around 1/5 of the thickness of the external portion 6), as is discussed below.
  • Moreover, the charge quantity being in the epitaxial silicon layer of the U-shaped external portion 6 of the column structures 4 is such that a balance of the charge is obtained with respect to the epitaxial layer 3 outside the column structures 4 themselves.
  • In the example of FIG. 1, a MOS transistor of the multi-drain type is realized.
  • Therefore, in the example as shown, the MOS transistor comprises a drain epitaxial layer 3 being provided with a plurality of column structures 4 and an active surface area 5 wherein a plurality of body wells 8 are realized, having the second conductivity type, for example the P type, inside which a corresponding plurality of source wells 9, of the first conductivity type, for example the N type, are realized.
  • An embodiment of the high-voltage MOS device of the example of FIG. 1 is completed by realizing a plurality of gate structures 10, being realized between consecutive pairs of column structures 4, above a channel region, being defined in the drain epitaxial layer 3 between the body wells 8 and the source wells 9.
  • An embodiment of the structure 1 for a high-voltage device may further include a covering or capping layer 11, being realized above the whole high-voltage device and, for example, covering the gate structures 10.
  • Finally, in an embodiment, the structure 1 for a high-voltage device may be provided, in a known manner, with surface contact structures of a microtrench or a conventional type.
  • Moreover, the gate structures 10 may be of the planar type or of the trench gate type.
  • In an embodiment the drain column structures 4, having a same periodicity as the body wells 8, have respective fastening zones 12 with the body wells 8 themselves. In particular, each of the column structures 4 comprises a pair of fastening zones 12 with the body wells 8, which bounds the column structure at the upper side.
  • In an embodiment of the structure 1 for a high-voltage device, each of the column structures 4 has a width Lc between approximately 1.5 and 4 um, for example, about 2 um, and a height Hc between approximately 10 and 70 um, for example, about 30 um, thus defining a maximum value of an aspect ratio of the deep trench which constitutes the column structures 4 equal to about 3/20.
  • Moreover, according to an embodiment, the epitaxial layer that realizes the external portion 6 has a dopant concentration between approximately 1e15 and 1e17, for example about 1e16 at/cm3, while the drain epitaxial layer 3 has a dopant concentration between approximately 5e14 and 5e16, for example about 5e15.
  • In an embodiment, the column structures 4 are separated by a distance Dc between approximately 2 um and 8 um, for example about 4 um, and by a distance Dcc between the symmetry axes of the column structures 4 between approximately 2.5 um and 12 um, for example about 6 um.
  • In an embodiment, the structure 1 for a high-voltage device realizes about a 600 V device.
  • By varying the height Hc of the column structures 4, it is however possible to obtain high voltage devices from, for example, about 300 V up to about 2000 V.
  • The dopant concentration along the axis X of the column structures 4 of an embodiment of the structure 1 for a high-voltage device is shown in FIG. 2A, X being the longitudinal development axis of the structure 1 itself, as also indicated in FIG. 1. In particular, the charge epitaxially introduced into the epitaxial layer which realizes the U-shaped external portion 6 of the column structures 4 is such that it counterbalances the charge being in the epitaxial layer 3 outside the column structures 4 themselves, the filling portion 7 of such column structures 4 being instead realized by an oxide.
  • In an embodiment, the dopant profile is thus almost devoid of a transient in the N conduction zone, i.e., in the epitaxial layer 3. In particular, the U-shaped external portion 6 has an approximately constant thickness and an approximately constant concentration dopant profile and with a narrow transition zone of, for example, N dopant shifted towards the semiconductor material of the neighboring epitaxial layer 3, which extends for a smaller distance than the thickness of the silicon epitaxial layer of the external portion 6 (for example, extending for a distance that is less than around 1/5 of the thickness of the external portion 6).
  • Analogously, in FIG. 2B a dopant concentration profile along the column structures 4 of an embodiment of the structure 1 for a high-voltage device is shown, X being the longitudinal development axis of the structure 1 itself.
  • According to this embodiment, the dopant in the epitaxial layer forming the U-shaped external portion 6 of the column structures 4 is not constant, but it has a peak in correspondence with the interface with the epitaxial layer 3 outside the column structures 4 themselves.
  • According to an embodiment, the manufacturing process of the structure 1 for a high-voltage device turns out to be well controlled since it is able provide a charge balance between the U-shaped external portion 6 of the column structures 4 and the epitaxial layer 3 outside them (e.g., between the N zone and the P zone) without needing an extremely fine control of the thickness of the silicon epitaxial layer as grown in order to realize the U-shaped external portion 6. In particular, an embodiment, changes of the thickness of the external portion 6 may cause little change to the total charge amount being contained in the silicon epitaxial layer of such external portion 6, thus making implementation of the process easier.
  • While in an embodiment as shown in FIG. 1 the column structures 4 do not reach the semiconductor substrate 2, it is possible to have an embodiment in which they reach it.
  • Moreover, it may be possible to realize in the active surface area 5 a high voltage device different from a MOS transistor, such as for example a diode or an IGBT device.
  • It may be possible to consider an embodiment of the structure 1 for a high-voltage device as including a first active area being realized by the column structures 4 and a second active area 8, and having at least one fastening zone 12 within the first active area 4.
  • In an embodiment, the second active area is “fastened” in correspondence with the fastening zone 12 to a conductive portion of the first active area, in particular of the column structures.
  • In an embodiment shown in FIG. 1, making a MOS transistor of the multi-drain type, the first active area is the drain area while the second one is the body area. In the case, for instance, of a diode, such first and second active areas would be the cathode and anode areas (or vice versa depending on the conductivities of these areas.
  • Also in the exemplary case of FIG. 1, the second active area is “fastened” in correspondence with the fastening zone 12 to the external portion 6 of the column structure 4, being a conductive portion of the first active area.
  • An embodiment also relates to an integration process of an embodiment of a structure 1 for a high-voltage device of the above indicated type.
  • An embodiment of integration process includes the steps of:
  • realizing a semiconductor substrate 2 having a first conductivity type;
  • epitaxially growing on such semiconductor substrate 2 an epitaxial layer 3 having the first conductivity type; and
    realizing in said epitaxial layer 3 at least a deep trench 4 having a high aspect ratio in order to realize at least one column structure, as schematically shown in FIG. 3A.
  • Next, within the trench 4 is grown a silicon layer 6, being placed at least on the walls and on the bottom of the trench 4 so as to realize an external portion of a column structure 4 being thus formed in the epitaxial layer 3.
  • The epitaxial layer 6 having been grown to form such an external portion is doped with a dopant of a second type and in such a way that the dopant charge being epitaxially introduced approximately counterbalances the charge of the dopant of the first type of the epitaxial layer 3 surrounding the trench 4, as schematically shown in FIG. 3B.
  • The steps of epitaxially growing the drain epitaxial layer 3 and the epitaxial layer 6 of the external portion of the column structures are realized with a limited thermal budget and a maximum process temperature less than about 1100° C. In this way, the process turns out to be compatible also with large-sized wafers (for instance of 8″ or 12″) and it is possible to minimize the transition zone between the column structures 4 and the conduction zones, i.e., the portions of the drain epitaxial layer 3 outside said column structures 4.
  • In other words, a process having a low thermal budget is used in order to keep almost unaltered the dopant distribution inside the epitaxial layer 6 having been grown inside the trench 4 which makes the column structures.
  • For example, the epitaxial growing steps realize the epitaxial layer 6 with a dopant concentration between about 1e15 and 1e17, for example about 1e16 at/cm3, and a drain epitaxial layer 3 with a dopant concentration between about 5e14 and 5e16, for example about 5e15.
  • Furthermore, the process may include a filling step of the trench 4 by means of a filling dielectric layer 7, for example an oxide, in order to realize a filling portion of the column structure 4, as schematically shown in FIG. 3C.
  • This filling step by means of the filling dielectric layer 7 e.g., completely fills the trench 4 to prevent voids from forming in the column structure 4.
  • The process then includes a step of realizing, in an active surface area 5 of the structure 1, a high voltage device comprising at least an active area. For example, as in the example shown in FIG. 1, the high-voltage device is a MOS transistor of the multi-drain type comprising a drain area being realized by the epitaxial layer 3 and the column structures 4 and comprising source wells 9 being realized in body wells 8, these latter having been realized in contact with the column structures 4 in correspondence with fastening zones 12, as well as gate structures 10 being realized over channel regions being defined in the body wells 8 and in contact with the source wells 9, as schematically shown in FIG. 3D.
  • An embodiment of the above described integration process has a lower number of steps than a conventional technology of integration of multi-drain transistors, and thus may be easier to implement.
  • Moreover, in an embodiment, the charge balance being realized by the epitaxial layer 6 of the external portion of the column structures 4 with respect to the epitaxial layer 3 which surrounds them, allows obtaining a constant dopant profile in the conduction zone, the extension of the voltage class of the high voltage device so obtained being thus easier.
  • In an embodiment the use of an epitaxial growing step of the layer 6 allows eliminating at least one problem of an implant angle tied to the high aspect ratio of the trench 4, with a better doping control of the external portion 6 of the column structures 4.
  • For example, it may be possible, by using a drain layer of the P type and column structures of the N type, to obtain a structure for a high-voltage device of a dual type.
  • A system, such as an automobile, may include device having an embodiment of the structure 1 of FIG. 1.
  • From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.

Claims (70)

  1. 1. Structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprise high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, wherein each of the column structures comprises at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
  2. 2. Structure for a high voltage device according to claim 1, wherein said epitaxial layer of said external portion is U-shaped and extends both on the wall and on the bottom of a corresponding column structure.
  3. 3. Structure for a high voltage device according to claim 2, wherein said external portion has a dopant concentration with a constant concentration dopant profile and with a transition zone towards said epitaxial layer outside said column structures having a smaller size than a thickness of a silicon epitaxial layer of said external portion.
  4. 4. Structure for a high voltage device according to claim 2, wherein said external portion has a dopant concentration with a growing dopant profile towards an interface with said epitaxial layer outside said column structures.
  5. 5. Structure for a high voltage device according to claim 4, wherein said external portion has a dopant concentration with a substantially constant concentration dopant profile.
  6. 6. Structure for a high voltage device according to claim 4, wherein said external portion has a dopant concentration with a variable concentration profile having a maximum near said interface with said epitaxial layer.
  7. 7. Structure for a high voltage device according to claim 2, wherein the thickness of said external portion is constant along its whole U-shaped profile.
  8. 8. Structure for a high voltage device according to claim 1, wherein said column structures have a ratio between width and height less than 3/20.
  9. 9. Structure for a high voltage device according to claim 1, wherein said column structures realize a first active area of said high voltage device and in that said high voltage device comprises at least a second active area which is realized in said active surface area and has at least one fastening zone with said first active area.
  10. 10. Structure for a high voltage device according to claim 9, wherein said first active area is fastened in correspondence with said fastening zone to a conduction portion of said first active area.
  11. 11. Structure for a high voltage device according to claim 9, wherein said conduction portion of said first active area is an external portion of said column structures.
  12. 12. Structure for a high voltage device according to claim 8, wherein said high voltage device is a MOS transistor of the Multi Drain type and in that said first active area is a drain area comprising said epitaxial layer and said column structures and in that said second active area is a body area.
  13. 13. Structure for a high voltage device according to claim 12, wherein said high voltage device comprises, in said active surface area, a plurality of body wells of said second type of conductivity, inside which corresponding plurality of source wells of said first type of conductivity are realized, as well as a plurality of gate structures, being realized between consecutive pairs of column structures, above a channel region being define in said epitaxial layer between said body wells and in contact with said source wells.
  14. 14. Structure for a high voltage device according to claim 13, it further comprising a capping layer, being realized on said high voltage device and in particular covering said gate structures.
  15. 15. Structure for a high voltage device according to claim 13, wherein said gate structures are chosen between planar type and trench gate type structures.
  16. 16. Structure for a high voltage device according to claim 13, it further comprising contact surface structures being chosen between microtrench type or conventional structures.
  17. 17. Structure for a high voltage device according to claim 8, wherein said column structures have a same periodicity with respect to said second active areas.
  18. 18. Structure for a high voltage device according to claim 1, wherein each of said column structures has a width between about 1.5 and 4 um, for example about 2 um and a height between about 10 and 70 um, for example about 30 um.
  19. 19. Structure for a high voltage device according to claim 1, wherein said external portion has a dopant concentration between about 1e15 and 1e17, for example about 1e16 at/cm3 and said epitaxial layer has a dopant concentration between about 5e14 and 5e16, for example about 5e15.
  20. 20. Structure for a high voltage device according to claim 1, wherein said column structures have a distance between about 2 um and 8 um, for example about 4 um.
  21. 21. Structure for a high voltage device according to claim 1, wherein said column structures extend down to said semiconductor substrate.
  22. 22. Structure for a high voltage device according to claim 1, wherein said column structures extend down to a prefixed distance from said semiconductor substrate.
  23. 23. Structure for a high voltage device according to claim 1, wherein said high voltage device is chosen between a MOS transistor, a diode and an IGBT device.
  24. 24. Integration process of a structure for a high voltage device of the type which comprises the steps of:
    realizing a semiconductor substrate having a first conductivity type;
    epitaxially growing on said semiconductor substrate an epitaxial layer having said first conductivity type; and
    realizing in said epitaxial layer at least one deep trench having a high aspect ratio in order to realize at least one column structure in said epitaxial layer;
    an epitaxial growing step within said trench of a silicon layer being doped and having a second conductivity type, opposed than said first conductivity type and having a dopant charge which counterbalances a dopant charge being in said epitaxial layer outside said column structures and
    a filling step of said trench by means of a filling dielectric layer in order to realize a filling portion of said at least one column structure.
  25. 25. Integration process according to claim 24, wherein said epitaxial growing step within said trench grows said silicon layer at least on the walls and on the bottom of said trench thus realizing an U-shaped external portion of said at least one column structure.
  26. 26. Integration process according to claim 24, wherein said epitaxial growing steps of said epitaxial layer on said semiconductor substrate and of said epitaxial layer within said trench are realized with a limited thermal budget and with a process maximum temperature less than 1100° C.
  27. 27. Integration process according to claim 26, wherein said epitaxial growing steps realize said epitaxial layer within said trench with a dopant concentration comprised between about 1e15 and 1e17, for example about 1e16 at/cm3, and said epitaxial layer on said semiconductor substrate with a dopant concentration comprised between about 5e 14 and 5e16, for example about 5e15.
  28. 28. Integration process according to claim 24, wherein said column structures realize a first active area of said high voltage device and in that if further comprises a step of realizing, in an active surface area of said structure, at least one second active area which has at least one fastening zone with said first active area.
  29. 29. Integration process according to claim 28, further comprising integrating a MOS transistor of the multi-drain type, by realizing, as the first active area, a drain area which comprises said epitaxial layer and said column structures and, as the second active area, a body area.
  30. 30. Integration process according to claim 28, further comprising integrating a diode by realizing, as the first active area, a cathode area and, as the second active area, an anode area.
  31. 31. A structure, comprising:
    a semiconductor layer having a first conductivity;
    a first semiconductor region extending into the semiconductor layer and having a second conductivity; and
    a first insulator region extending into the semiconductor region.
  32. 32. The structure of claim 31 wherein the semiconductor layer comprises an epitaxial layer.
  33. 33. The structure of claim 31 wherein the first conductivity comprises an N-type conductivity.
  34. 34. The structure of claim 31 wherein the semiconductor region comprises an epitaxial region.
  35. 35. The structure of claim 31 wherein the second conductivity comprises a P-type conductivity.
  36. 36. The structure of claim 31 wherein the insulator region comprises an oxide.
  37. 37. The structure of claim 31 wherein:
    the semiconductor layer has a layer surface;
    the semiconductor region extends into the semiconductor layer from an opening in the layer surface, and has a region surface; and
    the insulator region extends into the semiconductor region from an opening in the region surface.
  38. 38. The structure of claim 31, further comprising:
    wherein the semiconductor layer has a surface and forms a drain;
    a body region of the second conductivity disposed in the semiconductor layer adjacent to the semiconductor region and the surface;
    a source region of the first conductivity disposed in the body region adjacent to the surface;
    a gate insulator disposed over the body region; and
    a gate disposed over the gate insulator.
  39. 39. The structure of claim 31, further comprising:
    wherein the semiconductor layer has a surface and forms a drain;
    a body region of the second conductivity disposed in the semiconductor layer and adjacent to the semiconductor region and the surface;
    a body extension region of the second conductivity disposed in the semiconductor region adjacent to the body region;
    a source region of the first conductivity disposed in the body region adjacent to the surface;
    a gate insulator disposed over the body region; and
    a gate disposed over the gate insulator.
  40. 40. The structure of claim 31, further comprising:
    wherein the semiconductor layer has a surface and forms a drain;
    a body region of the second conductivity disposed in the semiconductor layer and adjacent to the semiconductor region and the surface;
    a body-extension region of the second conductivity disposed in the semiconductor region adjacent to the body region;
    a source region of the first conductivity disposed in the body region adjacent to the surface;
    a gate insulator disposed over the body region;
    a gate disposed over the gate insulator; and
    a source contact region disposed over the surface and adjacent to the body-extension and source regions.
  41. 41. The structure of claim 31 wherein:
    the semiconductor layer has a doping concentration of approximately between 5×1014 and 5×1016 atoms/cm3; and
    the semiconductor region has a doping concentration of approximately between 1×1015 and 1×1017 atoms/cm3.
  42. 42. The structure of claim 31 wherein:
    the semiconductor layer has a doping concentration of approximately 5×1015 atoms/cm3; and
    the semiconductor region has a doping concentration of approximately 1×1016 atoms/cm3.
  43. 43. The structure of claim 31 wherein:
    the semiconductor layer comprises a surface; and
    the semiconductor region has a height from the surface of between approximately 10 and 70 μm.
  44. 44. The structure of claim 31 wherein:
    the semiconductor layer comprises a surface; and
    the semiconductor region has a height from the surface of approximately 30 μm.
  45. 45. The structure of claim 31 wherein the semiconductor region has a width of between approximately 1.5 and 4 μm.
  46. 46. The structure of claim 31 wherein the semiconductor region has a width of approximately 2 μm.
  47. 47. The structure of claim 31, further comprising:
    a second semiconductor region extending into the semiconductor layer and having a second conductivity; and
    a second insulator region extending into the second semiconductor region.
  48. 48. The structure of claim 47, further comprising:
    wherein the semiconductor layer has a surface and forms a drain;
    a first body region of the second conductivity disposed in the semiconductor layer adjacent to the first semiconductor region and the surface;
    a first source region of the first conductivity disposed in the first body region adjacent to the surface;
    a first gate insulator disposed over the first body region;
    a first gate disposed over the gate insulator;
    a second body region of the second conductivity disposed in the semiconductor layer adjacent to the second semiconductor region and the surface;
    a second source region of the first conductivity disposed in the second body region adjacent to the surface;
    a second gate insulator disposed over the second body region; and
    a second gate disposed over the second gate insulator.
  49. 49. The structure of claim 47 wherein the first and second semiconductor regions are spaced apart by approximately 2 to 8 μm.
  50. 50. The structure of claim 47 wherein the first and second semiconductor regions are spaced apart by approximately 4 μm.
  51. 51. The structure of claim 47 wherein the first and second insulator regions are spaced apart by approximately 2.5 to 12 μm.
  52. 52. The structure of claim 47 wherein the first and second insulator regions are spaced apart by approximately 6 μm.
  53. 53. The structure of claim 31, further comprising:
    wherein the semiconductor layer has a surface and forms a drain;
    a first body region of the second conductivity disposed in the semiconductor layer adjacent to the semiconductor region and the surface;
    a first source region of the first conductivity disposed in the first body region adjacent to the surface;
    a first gate insulator disposed over the first body region;
    a first gate disposed over the first gate insulator;
    a second body region of the second conductivity disposed in the semiconductor layer adjacent to the first semiconductor region and the surface;
    a second source region of the first conductivity disposed in the second body region adjacent to the surface;
    a second gate insulator disposed over the second body region; and
    a second gate disposed over the second gate insulator.
  54. 54. The structure of claim 31, further comprising:
    wherein the semiconductor layer has a surface and forms a drain;
    a first body region of the second conductivity disposed in the semiconductor layer adjacent to the semiconductor region and the surface;
    a first body-extension region of the second conductivity disposed in the semiconductor region adjacent to the first body region;
    a first source region of the first conductivity disposed in the first body region adjacent to the surface;
    a first gate insulator disposed over the first body region;
    a first gate disposed over the first gate insulator;
    a second body region of the second conductivity disposed in the semiconductor layer adjacent to the first semiconductor region and the surface;
    a second body-extension region of the second conductivity disposed in the semiconductor region adjacent to the second body region;
    a second source region of the first conductivity disposed in the second body region adjacent to the surface;
    a second gate insulator disposed over the second body region; and
    a second gate disposed over the second gate insulator.
  55. 55. The semiconductor structure of claim 31, further comprising a doping transition region disposed between the semiconductor layer and the first semiconductor region.
  56. 56. The semiconductor structure of claim 31 wherein the first semiconductor region has an approximately constant doping profile between the semiconductor layer and the first insulator region.
  57. 57. The semiconductor structure of claim 31 wherein the first semiconductor region has a varying doping profile between the semiconductor layer and the first insulator region.
  58. 58. An integrated circuit, comprising:
    a semiconductor layer having a first conductivity; and
    an electronic device, comprising:
    a first semiconductor region extending into the semiconductor layer and having a second conductivity; and
    a first insulator region extending into the semiconductor region.
  59. 59. A system, comprising:
    a first integrated circuit, comprising:
    a semiconductor layer having a first conductivity; and
    an electronic device, comprising:
    a first semiconductor region extending into the semiconductor layer and having a second conductivity; and
    a first insulator region extending into the semiconductor region; and
    a second integrated circuit coupled to the first integrated circuit.
  60. 60. The system of claim 59 wherein the first and second integrated circuits are disposed on a same die.
  61. 61. The system of claim 59 wherein the first and second integrated circuits are disposed on respective dies.
  62. 62. The system of claim 59 wherein the second integrated circuit comprises a controller.
  63. 63. A method, comprising:
    forming a first trench in a first semiconductor layer having a first conductivity;
    lining a wall of the first trench with a second semiconductor layer having a second conductivity; and
    forming a first insulator region in the lined first trench.
  64. 64. The method of claim 63, further comprising epitaxially growing the first semiconductor layer over a substrate.
  65. 65. The method of claim 63, further comprising epitaxially growing the second semiconductor layer over the first semiconductor layer.
  66. 66. The method of claim 63, further comprising:
    forming a body region of the second conductivity in the first semiconductor layer adjacent to the trench;
    forming a source region of the first conductivity in the body region;
    forming a gate insulator over the body region; and
    forming a gate over the gate insulator.
  67. 67. The method of claim 63, further comprising:
    forming a body region of the second conductivity in the first semiconductor layer adjacent to the trench; and
    forming a body-region extension of the second conductivity in the second semiconductor layer adjacent to the body region.
  68. 68. The method of claim 63, further comprising forming a body region of the second conductivity in the first and second semiconductor layers adjacent to a surface of the first semiconductor layer.
  69. 69. The method of claim 63, further comprising:
    forming a second trench in the first semiconductor layer;
    lining a wall of the second trench with a third semiconductor layer having the second conductivity; and
    forming a second insulator region in the lined second trench.
  70. 70. The method of claim 63, further comprising:
    wherein lining the wall of the first trench comprises lining the wall of the first trench with a first portion of the second semiconductor layer;
    forming a second trench in the first semiconductor layer;
    lining a wall of the second trench with a second portion of the second semiconductor layer; and
    forming a second insulator region in the lined second trench.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150076660A1 (en) * 2013-09-18 2015-03-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US20160163787A1 (en) * 2013-03-13 2016-06-09 Michael W. Shore Gate pad and gate feed breakdown voltage enhancement

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102214684B (en) * 2011-06-03 2012-10-10 清华大学 Semiconductor structure with suspended sources and drains as well as formation method thereof
WO2017168736A1 (en) * 2016-03-31 2017-10-05 新電元工業株式会社 Semiconductor device and production method for semiconductor device
CN105789270A (en) * 2016-04-21 2016-07-20 西安电子科技大学 VDMOS device with variable dielectric side

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174773B1 (en) * 1995-02-17 2001-01-16 Fuji Electric Co., Ltd. Method of manufacturing vertical trench misfet
US6228719B1 (en) * 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
US6300171B1 (en) * 1998-12-09 2001-10-09 Stmicroelectronics S.R.L. Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
US20010055861A1 (en) * 2000-04-04 2001-12-27 Davide Patti Process for manufacturing deep well junction structures
US6404010B2 (en) * 2000-05-19 2002-06-11 Stmicroelectronics S.R.L. MOS technology power device
US6410958B1 (en) * 2000-11-27 2002-06-25 Kabushiki Kaisha Toshiba Power MOSFET having laterally three-layered structure formed among element isolation regions
US20020100933A1 (en) * 2001-01-30 2002-08-01 Marchant Bruce D. Field effect transistor having a lateral depletion structure
EP1267415A2 (en) * 2001-06-11 2002-12-18 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
US6586798B1 (en) * 1998-12-09 2003-07-01 Stmicroelectronics S.R.L. High voltage MOS-gated power device
US6803626B2 (en) * 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US20080038850A1 (en) * 2006-08-11 2008-02-14 Denso Corporation Method for manufacturing semiconductor device
US20080138953A1 (en) * 2003-05-20 2008-06-12 Ashok Challa Methods of Making Power Semiconductor Devices with Thick Bottom Oxide Layer
US7393749B2 (en) * 2005-06-10 2008-07-01 Fairchild Semiconductor Corporation Charge balance field effect transistor
US7498619B2 (en) * 2005-02-25 2009-03-03 Stmicroelectronics S.R.L. Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process
US7851897B1 (en) * 2008-06-16 2010-12-14 Maxim Integrated Products, Inc. IC package structures for high power dissipation and low RDSon

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1742259A1 (en) 2005-07-08 2007-01-10 SGS-THOMSON MICROELECTRONICS S.r.l. Semiconductor power device with multiple drain structure and corresponding manufacturing process
EP1742258A1 (en) 2005-07-08 2007-01-10 SGS-THOMSON MICROELECTRONICS S.r.l. Semiconductor power device with multiple drain and corresponding manufacturing process
US8304311B2 (en) 2006-04-11 2012-11-06 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174773B1 (en) * 1995-02-17 2001-01-16 Fuji Electric Co., Ltd. Method of manufacturing vertical trench misfet
US6228719B1 (en) * 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
US6586798B1 (en) * 1998-12-09 2003-07-01 Stmicroelectronics S.R.L. High voltage MOS-gated power device
US6300171B1 (en) * 1998-12-09 2001-10-09 Stmicroelectronics S.R.L. Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
US20010055861A1 (en) * 2000-04-04 2001-12-27 Davide Patti Process for manufacturing deep well junction structures
US6404010B2 (en) * 2000-05-19 2002-06-11 Stmicroelectronics S.R.L. MOS technology power device
US6410958B1 (en) * 2000-11-27 2002-06-25 Kabushiki Kaisha Toshiba Power MOSFET having laterally three-layered structure formed among element isolation regions
US20020100933A1 (en) * 2001-01-30 2002-08-01 Marchant Bruce D. Field effect transistor having a lateral depletion structure
EP1267415A2 (en) * 2001-06-11 2002-12-18 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
US6803626B2 (en) * 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US20080138953A1 (en) * 2003-05-20 2008-06-12 Ashok Challa Methods of Making Power Semiconductor Devices with Thick Bottom Oxide Layer
US7498619B2 (en) * 2005-02-25 2009-03-03 Stmicroelectronics S.R.L. Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process
US7393749B2 (en) * 2005-06-10 2008-07-01 Fairchild Semiconductor Corporation Charge balance field effect transistor
US20080038850A1 (en) * 2006-08-11 2008-02-14 Denso Corporation Method for manufacturing semiconductor device
US7851897B1 (en) * 2008-06-16 2010-12-14 Maxim Integrated Products, Inc. IC package structures for high power dissipation and low RDSon

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Wolf et al.; Silicon Processing for the VLSI Era, volume 1: Process Technology; Year 1986; Lattice Press, Sunset Beach, California; p.124 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160163787A1 (en) * 2013-03-13 2016-06-09 Michael W. Shore Gate pad and gate feed breakdown voltage enhancement
US9536941B2 (en) * 2013-03-13 2017-01-03 Michael Wayne Shore Gate pad and gate feed breakdown voltage enhancement
US20150076660A1 (en) * 2013-09-18 2015-03-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9558986B2 (en) * 2013-09-18 2017-01-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof

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