JPS57159060A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS57159060A JPS57159060A JP4458381A JP4458381A JPS57159060A JP S57159060 A JPS57159060 A JP S57159060A JP 4458381 A JP4458381 A JP 4458381A JP 4458381 A JP4458381 A JP 4458381A JP S57159060 A JPS57159060 A JP S57159060A
- Authority
- JP
- Japan
- Prior art keywords
- region
- guard
- annular
- surrounding
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To accelerate the spreading of a depletion layer in the vicinity of the surface and to contrive improvement of the withstand voltage for the subject semiconductor device by a method wherein, in the semiconductor device of a planar construction, two annular guard regions are formed surrounding an element region, and the depth of the outer circumferential guard region is formed shallower than that of the inner circumferential guard region. CONSTITUTION:In the case of a planar transistor consisting of a P type collector region 1, an N type base region 2 and P type emitter region, an annular first guard region 4 surrounding the base region 2 and an annular second guard region 5, surrounding the region 4, and having the shallower depth than the region 4, are provided. Insulating layers 6 and 7, which protect each junction, are coated on the surface, and metal electrodes 8, 9 and 10 are provided on each element region. As a result, when an inverted bias is applied in between the collector and the base of the transistor, a depletion layer 11 spreads out satisfactorily even in the vicinity of the surface, thereby enabling to prevent the breakdown of element due to an electric field concentration in the neighborhood of the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4458381A JPS57159060A (en) | 1981-03-26 | 1981-03-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4458381A JPS57159060A (en) | 1981-03-26 | 1981-03-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57159060A true JPS57159060A (en) | 1982-10-01 |
Family
ID=12695502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4458381A Pending JPS57159060A (en) | 1981-03-26 | 1981-03-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57159060A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1011146A1 (en) * | 1998-12-09 | 2000-06-21 | STMicroelectronics S.r.l. | Integrated edge structure for high voltage semiconductor devices and related manufacturing process |
-
1981
- 1981-03-26 JP JP4458381A patent/JPS57159060A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1011146A1 (en) * | 1998-12-09 | 2000-06-21 | STMicroelectronics S.r.l. | Integrated edge structure for high voltage semiconductor devices and related manufacturing process |
| JP2000183350A (en) * | 1998-12-09 | 2000-06-30 | Stmicroelectronics Srl | Manufacture of integrated edge structure for high voltage semiconductor device and integrated edge structure |
| US6300171B1 (en) | 1998-12-09 | 2001-10-09 | Stmicroelectronics S.R.L. | Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure |
| US6809383B2 (en) | 1998-12-09 | 2004-10-26 | Stmicroelectronics S.R.L. | Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure |
| JP4597293B2 (en) * | 1998-12-09 | 2010-12-15 | エスティーマイクロエレクトロニクス エス．アール．エル． | Method for manufacturing integrated edge structure for high voltage semiconductor device and integrated edge structure |
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