JP4998524B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4998524B2 JP4998524B2 JP2009173268A JP2009173268A JP4998524B2 JP 4998524 B2 JP4998524 B2 JP 4998524B2 JP 2009173268 A JP2009173268 A JP 2009173268A JP 2009173268 A JP2009173268 A JP 2009173268A JP 4998524 B2 JP4998524 B2 JP 4998524B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- columnar
- electric field
- field relaxation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 67
- 230000005684 electric field Effects 0.000 claims description 75
- 230000002093 peripheral effect Effects 0.000 claims description 47
- 238000013459 approach Methods 0.000 claims description 13
- 230000007423 decrease Effects 0.000 claims description 9
- 239000012535 impurity Substances 0.000 description 31
- 230000000052 comparative effect Effects 0.000 description 22
- 239000000758 substrate Substances 0.000 description 19
- 230000015556 catabolic process Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000009826 distribution Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
以下、図面を参照して、FET(電界効果トランジスタ)を複数有する半導体装置に本発明を適用した第1実施形態について説明する。図1は、第1実施形態による半導体装置の断面図である。図2は、半導体装置の平面概略図である。尚、図1は、図2のI−I線に沿った断面図である。以下の説明において、図1の矢印で示す外内を、外側及び内側とする。図2は、p型ベース領域及び電界緩和領域の平面形状を説明するためのものであり、不要な構成を省略している。
W1>W2>W3
となる。尚、ここでいう幅Wnとは、外内方向上の幅のことである。一例として、「D1×0.9=D2」、「D2×0.9=D3」と、0.1ずつ幅Wnが小さくなるように設定してもよい。これにより、p型電界緩和領域24nと隣接するp型電界緩和領域24n+1との間隔Snは、外側に近づくに連れて徐々に大きくなる。即ち、
S1<S2
となる。
次に、上述した第1実施形態による半導体装置1の動作について説明する。
次に、上述した第1実施形態による半導体装置1の製造方法について説明する。図3〜図8は、第1実施形態による半導体装置の各製造工程を説明する図である。
次に上述した第1実施形態による半導体装置1の効果について説明する。
次に、上述した効果を実証するために実施した電位分布シミュレーションについて説明する。
2 セル領域
3 外周領域
4 等電位リング領域
6 半導体素子
7 半導体基体
7a 主面
11 基板
11a 主面
11b 主面
12 n−型ドリフト領域
13 p−型柱状領域
14 p型ベース領域
15 n型ソース領域
16 ゲート電極
17 ゲート絶縁膜
18 ソース電極
19 ドレイン電極
23n p−型柱状耐圧向上領域
24n p型電界緩和領域
27 絶縁膜
31 リング電極
35a〜35g n型ドリフト領域層
36、38、39 レジスト膜
36a、38a、39a 開口部
37a〜37f p型不純物領域
D 距離
Sn 間隔
Wn 幅
Claims (4)
- 半導体素子が形成されるセル領域と、前記セル領域の外周に形成された外周領域とを有する半導体装置において、
前記セル領域及び前記外周領域に形成された第1導電型の第1導電型領域と、
前記セル領域の第1導電型領域に形成された第2導電型の複数の第1柱状領域と、
前記外周領域の第1導電型領域に形成された第2導電型の複数の第2柱状領域と、
前記第2柱状領域の上部に形成された第2導電型の複数の電界緩和領域とを備え、
前記外周領域における内側の前記電界緩和領域と隣接する電界緩和領域との間隔は、前記外周領域における外側の前記電界緩和領域と隣接する電界緩和領域との間隔よりも小さく、前記第1柱状領域と隣接する第1柱状領域との距離、前記第2柱状領域と隣接する第2柱状領域との距離、及び互いに隣接する前記第1柱状領域と前記第2柱状領域間の距離がすべて等しく、且つ、隣接する前記第1柱状領域の中心間距離、隣接する前記第2柱状領域の中心間距離、互いに隣接する前記第1柱状領域と前記第2柱状領域の中心間距離、及び隣接する前記電界緩和領域の中心間距離がすべて等しいことを特徴とするスーパージャンクション構造を有する半導体装置。 - 前記電界緩和領域と隣接する電界緩和領域との間隔は、前記外周領域における外側に近づくに連れて徐々に大きくなることを特徴とする請求項1に記載のスーパージャンクション構造を有する半導体装置。
- 前記電界緩和領域の幅は、前記外周領域における外側に近づくに連れて徐々に小さくなることを特徴とする請求項1または請求項2に記載のスーパージャンクション構造を有する半導体装置。
- 前記電界緩和領域の深さは、前記外周領域における外側に近づくに連れて徐々に浅くなることを特徴とする請求項1乃至請求項3のいずれか1項に記載のスーパージャンクション構造を有する半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009173268A JP4998524B2 (ja) | 2009-07-24 | 2009-07-24 | 半導体装置 |
US12/836,911 US8330233B2 (en) | 2009-07-24 | 2010-07-15 | Semiconductor device |
CN201010236329XA CN101964343B (zh) | 2009-07-24 | 2010-07-21 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009173268A JP4998524B2 (ja) | 2009-07-24 | 2009-07-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011029393A JP2011029393A (ja) | 2011-02-10 |
JP4998524B2 true JP4998524B2 (ja) | 2012-08-15 |
Family
ID=43496537
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009173268A Active JP4998524B2 (ja) | 2009-07-24 | 2009-07-24 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8330233B2 (ja) |
JP (1) | JP4998524B2 (ja) |
CN (1) | CN101964343B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5504235B2 (ja) * | 2011-09-29 | 2014-05-28 | 株式会社東芝 | 半導体装置 |
US8975136B2 (en) * | 2013-02-18 | 2015-03-10 | Infineon Technologies Austria Ag | Manufacturing a super junction semiconductor device |
CN104638004B (zh) * | 2013-11-15 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | 超级结mosfet器件的结构 |
US10411116B2 (en) * | 2015-04-30 | 2019-09-10 | Suzhou Oriental Semiconductor Co., Ltd. | Semiconductor super-junction power device and manufacturing method therefor |
WO2017094144A1 (ja) * | 2015-12-02 | 2017-06-08 | サンケン電気株式会社 | 半導体装置 |
TWI699887B (zh) * | 2017-04-20 | 2020-07-21 | 聚積科技股份有限公司 | 具有分段式濃度的功率半導體裝置 |
CN115362560A (zh) | 2020-03-30 | 2022-11-18 | 罗姆股份有限公司 | 半导体装置 |
CN111430466A (zh) * | 2020-05-06 | 2020-07-17 | 厦门芯达茂微电子有限公司 | TE-cooler MOSFET结构及其制备、调节方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0310556U (ja) * | 1989-06-19 | 1991-01-31 | ||
DE69833743T2 (de) * | 1998-12-09 | 2006-11-09 | Stmicroelectronics S.R.L., Agrate Brianza | Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen |
JP4765012B2 (ja) * | 2000-02-09 | 2011-09-07 | 富士電機株式会社 | 半導体装置及びその製造方法 |
US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP3908572B2 (ja) * | 2002-03-18 | 2007-04-25 | 株式会社東芝 | 半導体素子 |
WO2005065385A2 (en) * | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP2006005275A (ja) | 2004-06-21 | 2006-01-05 | Toshiba Corp | 電力用半導体素子 |
JP2006073740A (ja) * | 2004-09-01 | 2006-03-16 | Toshiba Corp | 半導体装置及びその製造方法 |
-
2009
- 2009-07-24 JP JP2009173268A patent/JP4998524B2/ja active Active
-
2010
- 2010-07-15 US US12/836,911 patent/US8330233B2/en active Active
- 2010-07-21 CN CN201010236329XA patent/CN101964343B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US8330233B2 (en) | 2012-12-11 |
US20110018101A1 (en) | 2011-01-27 |
CN101964343B (zh) | 2012-05-09 |
CN101964343A (zh) | 2011-02-02 |
JP2011029393A (ja) | 2011-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4998524B2 (ja) | 半導体装置 | |
US8748982B2 (en) | High breakdown voltage semiconductor device | |
US7553731B2 (en) | Method of manufacturing semiconductor device | |
JP4980663B2 (ja) | 半導体装置および製造方法 | |
US10529849B2 (en) | High-voltage semiconductor device including a super-junction doped structure | |
CN102412260B (zh) | 超级结半导体器件的终端保护结构及制作方法 | |
US20150179764A1 (en) | Semiconductor device and method for manufacturing same | |
JP5537996B2 (ja) | 半導体装置 | |
JP5136578B2 (ja) | 半導体装置 | |
CN102867842B (zh) | 超级结器件及制造方法 | |
JP2007266505A (ja) | 電力用半導体素子 | |
JP2006196518A (ja) | 半導体装置およびその製造方法 | |
CN106165101B (zh) | 半导体装置 | |
WO2015118721A1 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2009088005A (ja) | 半導体装置およびその製造方法 | |
JP2011204796A (ja) | 半導体装置およびその製造方法 | |
WO2014087499A1 (ja) | 半導体装置 | |
JP5559232B2 (ja) | 電力用半導体素子 | |
JP5641995B2 (ja) | 半導体素子 | |
KR101360070B1 (ko) | 반도체 소자 및 그 제조 방법 | |
KR20140044075A (ko) | 반도체 소자 및 그 제조 방법 | |
JP5691550B2 (ja) | 半導体装置 | |
EP3896744A1 (en) | Termination for trench field plate power mosfet | |
JP2006261562A (ja) | 半導体装置 | |
EP3174104B1 (en) | Power semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110614 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110616 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110803 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120131 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120326 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120417 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120430 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4998524 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150525 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |