WO2014087499A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2014087499A1
WO2014087499A1 PCT/JP2012/081483 JP2012081483W WO2014087499A1 WO 2014087499 A1 WO2014087499 A1 WO 2014087499A1 JP 2012081483 W JP2012081483 W JP 2012081483W WO 2014087499 A1 WO2014087499 A1 WO 2014087499A1
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Prior art keywords
region
semiconductor substrate
impurity concentration
depth
semiconductor device
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PCT/JP2012/081483
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English (en)
French (fr)
Inventor
亀山　悟
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トヨタ自動車株式会社
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Application filed by トヨタ自動車株式会社 filed Critical トヨタ自動車株式会社
Priority to KR1020157013114A priority Critical patent/KR20150066596A/ko
Priority to JP2014550844A priority patent/JPWO2014087499A1/ja
Priority to CN201280077544.7A priority patent/CN104838503A/zh
Priority to DE112012007200.6T priority patent/DE112012007200T5/de
Priority to PCT/JP2012/081483 priority patent/WO2014087499A1/ja
Priority to BR112015012736A priority patent/BR112015012736A2/pt
Priority to US14/443,509 priority patent/US20150318385A1/en
Publication of WO2014087499A1 publication Critical patent/WO2014087499A1/ja

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    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Definitions

  • the technology described in this specification relates to a semiconductor device.
  • Patent Document 1 discloses a technique for reducing the amount of holes injected into the cathode region in order to improve high speed and low loss.
  • Patent Document 1 discloses a shallow high-concentration p exposed on the surface of a semiconductor substrate in order to reduce the dose of p-type impurities in the anode region and reduce the amount of holes injected into the cathode region.
  • the layers and the deep low-concentration p layers exposed on the surface of the semiconductor substrate are alternately arranged in the planar direction of the semiconductor substrate.
  • the first semiconductor device disclosed in this specification includes a semiconductor substrate having an anode region and a cathode region.
  • the anode region has a first conductivity type first region having a maximum value of the first conductivity type impurity concentration at a position that is a first depth from the surface of the semiconductor substrate, and the surface side of the semiconductor substrate from the first depth.
  • the first conductivity type second region having the maximum value of the first conductivity type impurity concentration at a position of the second depth, and between the first region and the second region, the first conductivity type
  • a third region having an impurity concentration of 1/10 or less of the surface of the semiconductor substrate.
  • the first region affects the hole injection amount. This can be suppressed.
  • the first conductivity type impurity concentration in the first region can be increased in order to ensure the breakdown voltage, and the first conductivity type impurity in the second region can be decreased in order to suppress the hole injection amount. And a reduction in the amount of hole injection can both be achieved.
  • the third region may be a region containing a second conductivity type impurity. Furthermore, at least a part of the third region is exposed on the surface of the semiconductor substrate, and may be Schottky bonded to the surface electrode of the semiconductor substrate.
  • the impurity concentration at the first depth in the first region is preferably 1 ⁇ 10 16 atoms / cm 3 or less.
  • the second semiconductor device disclosed in this specification includes a diode region and an IGBT region on the same semiconductor substrate.
  • the diode region includes an anode region and a cathode region.
  • the anode region has a first conductivity type first region having a maximum value of the first conductivity type impurity concentration at a position that is a first depth from the surface of the semiconductor substrate, and the surface side of the semiconductor substrate from the first depth.
  • the second region of the first conductivity type having the maximum value of the impurity concentration of the first conductivity type.
  • the IGBT region includes a first conductivity type body region, a second conductivity type drift region, a second conductivity type emitter region, and a first conductivity type collector region, and the body region is a surface of the semiconductor substrate.
  • the first conductivity type impurity concentration has a first maximum value at a position at a first depth from the first depth, and the first conductivity type impurity concentration has a position closer to the surface side of the semiconductor substrate than the first depth. It has a second maximum value.
  • the second semiconductor device in order to increase the first conductivity type impurity concentration in the first region in order to ensure a breakdown voltage, and to suppress the hole injection amount. Impurities of the first conductivity type in the second region can be reduced.
  • the third region having a sufficiently low impurity concentration of the first conductivity type is included between the first region and the second region, it is possible to suppress the first region from affecting the hole injection amount.
  • the breakdown voltage is ensured in the region having the first maximum value, and holes can be efficiently extracted in the region having the second maximum value during the IGBT operation.
  • FIG. 1 is a plan view of a semiconductor device according to Example 1.
  • FIG. FIG. 2 is a sectional view taken along line II-II in FIG.
  • FIG. 2 is a diagram conceptually showing an impurity concentration distribution in an anode region of the semiconductor device of FIG. 1.
  • 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 1.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 1.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 1.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 1.
  • FIG. It is a longitudinal cross-sectional view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification.
  • FIG. 7 is a longitudinal sectional view of a semiconductor device according to Example 2.
  • FIG. FIG. 12 is a diagram conceptually showing an impurity concentration distribution in an anode region of the semiconductor device of FIG. 11.
  • 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device of Example 2.
  • FIG. 12 is a diagram conceptually showing an impurity concentration distribution in an anode region of the semiconductor device of FIG. 11.
  • 6 is a diagram illustrating a method for manufacturing the semiconductor device
  • FIG. 6 is a longitudinal sectional view of a semiconductor device of Example 3.
  • FIG. FIG. 20 conceptually shows an impurity concentration distribution in an anode region of the semiconductor device of FIG. 19.
  • FIG. 20 conceptually shows an impurity concentration distribution in the body region of the semiconductor device of FIG. 19 and in the vicinity thereof. It is a longitudinal cross-sectional view of the semiconductor device which concerns on a modification.
  • the semiconductor device 10 includes a semiconductor substrate 100 including a cell region 11 and a peripheral region 12.
  • the surface electrode 132 is not shown.
  • the semiconductor substrate 100 includes an n-type cathode layer 101 exposed on the back surface (surface in the negative direction of the z-axis), and an n-type drift layer provided on the surface of the cathode layer 101 (surface in the positive direction of the z-axis). 102.
  • the cathode layer 101 and the drift layer 102 constitute a cathode region.
  • the cathode layer 101 is in contact with the back electrode 131.
  • an anode region 120 is provided on the surface of the drift layer 102, and the anode region 120 includes a first region 103 in contact with the surface of the drift layer 102 and a second region 105 exposed on the surface of the semiconductor substrate 100.
  • a third region 104 provided between the first region 103 and the second region 105.
  • the second region 105 is in contact with the surface electrode 132.
  • p-type FLR layers 111 and 112 are provided on the surface of the drift layer 102.
  • the surface of the FLR layer 111 is in contact with the surface electrode 132 on the central side of the semiconductor substrate 100 and in contact with the insulating film 133 on the peripheral side.
  • the FLR layers 111 and 112 are peripheral breakdown voltage structures of the semiconductor device 10.
  • the form of the peripheral breakdown voltage structure is not limited to the FLR layer, and a conventionally known structure such as a RESURF layer can be used.
  • FIG. 3 is a diagram showing a p-type impurity concentration distribution in the depth direction of the anode region 120.
  • the vertical axis indicates the position of the semiconductor substrate 100 in the depth direction.
  • A1 is the position of the upper end of the second area 105
  • B1 is the position of the boundary between the second area 105 and the third area 104
  • C1 is the position of the boundary between the third area 104 and the first area 103.
  • D1 is the position of the boundary between the first region 103 and the drift layer 102.
  • Reference numerals 173 and 175 indicate p-type impurity concentration distributions of the first region 103 and the second region 105, respectively.
  • a p-type impurity concentration distribution in an anode region of a conventional semiconductor device is also illustrated as a reference number 179.
  • the maximum value of the p-type impurity concentration in the distribution 173 is located at the first depth from the surface of the semiconductor substrate 100, and the maximum value of the p-type impurity concentration in the distribution 175 is the second value from the surface of the semiconductor substrate 100. Located at depth.
  • the maximum value of the p-type impurity concentration in the first region 103 (the peak concentration value of the distribution 173) is 2 ⁇ 10 16 atoms / cm 3 .
  • the p-type impurity concentration in the second region is the highest on the surface of the semiconductor substrate 100 (that is, the depth A1) and is 1 ⁇ 10 17 atoms / cm 3 .
  • the p-type impurity concentration of the third region 104 is lower than 1 ⁇ 10 16 atoms / cm 3 .
  • the p-type impurity concentration in the third region 104 is not more than 1/10 of the p-type impurity concentration at the depth A 1 that is the surface position of the semiconductor substrate 100.
  • the p-type impurity concentration in the anode region becomes the maximum with the surface (depth A1) of the semiconductor substrate being increased, and becomes lower as the depth increases. Therefore, in order to increase the p-type impurity concentration in the region near the cathode region of the anode region in order to ensure the breakdown voltage of the semiconductor device, it is necessary to increase the p-type impurity concentration on the surface of the semiconductor substrate. If the p-type impurity concentration on the surface of the semiconductor substrate is high, the amount of holes injected increases, and the high speed and low loss characteristics of the semiconductor device decrease.
  • the p-type impurity concentration distribution 173 in the first region 103 and the p-type impurity concentration distribution 175 in the second region 105 can be individually designed independently.
  • the semiconductor device 10 includes a third region 104 having a low p-type impurity concentration between the first region 103 and the second region 105.
  • the p-type impurity concentration of the third region 104 is 1/10 or less of the p-type impurity concentration at the depth A1 that is the surface position of the semiconductor substrate 100 as in this embodiment, the first region 103 It is possible to sufficiently suppress the influence of the p-type impurity concentration on the hole injection amount.
  • FIGS. 4 to 6 show only the cell region 11 of FIG. 2, and only the step of forming the anode region 120 in the cell region 11 will be described using these drawings.
  • Other configurations of the semiconductor device 10 can be formed by a method similar to a conventional method for manufacturing a semiconductor device.
  • a semiconductor substrate 500 is prepared.
  • an n + layer 501 that becomes the cathode layer 101 and an n layer 502 that becomes the drift layer 102 are stacked in this order from the back surface side.
  • p-type impurity ions are implanted into the n layer 502 at a position that becomes the second depth from the surface of the semiconductor substrate 500.
  • the second depth is a position that is substantially the surface of the semiconductor substrate 500.
  • a p-type ion implantation layer 505 is formed as shown in FIG.
  • the n + layer 501 may be formed on the semiconductor substrate 500 after performing the step of forming the surface structure of the semiconductor device 10 described below.
  • p-type impurity ions are implanted into the first layer from the surface of the semiconductor substrate 500 in the n layer 502, and as shown in FIG. 503 is formed.
  • the first depth is a position deeper than the second depth (position in the negative direction of the z axis).
  • an intermediate layer 504 having a low p-type impurity concentration is formed between the ion implantation layer 503 and the ion implantation layer 505.
  • the second region 105 covers the entire surface of the third region 104.
  • the present invention is not limited to this.
  • the second region 205 may be formed in a part of the surface of the third region 204 in the cell region.
  • the second region 205 is formed in a stripe shape extending in the y direction when the surface of the semiconductor substrate 200 is viewed in plan.
  • the second region 205 and the third region 204 are exposed on the surface of the semiconductor substrate 200 and are in contact with the surface electrode 132.
  • the second region 205 and the surface electrode 132 are in ohmic contact, and the third region 204 and the surface electrode 132 are in Schottky contact.
  • circular second regions 215 may be distributed on the surface of the third region 214.
  • FIG. 11 is a longitudinal sectional view of the cell region of the semiconductor device 30 according to the second embodiment.
  • the semiconductor device 30 includes a semiconductor substrate 300.
  • the semiconductor substrate 300 includes an n-type cathode layer 301, an n-type drift layer 302, a p-type first region 303, an n-type third region 304, and a p-type, which are stacked in order from the back side.
  • the second region 305 is provided.
  • the cathode layer 301 and the drift layer 302 constitute a cathode region.
  • the first region 303, the third region 304 and the second region 305 constitute an anode region 320.
  • the cathode layer 301 is in contact with the back electrode 131, and the second region 305 is in contact with the front electrode 132.
  • the other configuration of the semiconductor device 30 is the same as that of the semiconductor device 10 shown in FIG.
  • FIG. 12 is a diagram showing an impurity concentration distribution in the depth direction of the anode region 320.
  • the vertical axis indicates the position of the semiconductor substrate 300 in the depth direction.
  • A2 is the position of the upper end of the second area 305
  • B2 is the position of the boundary between the second area 305 and the third area 304
  • C2 is the position of the boundary between the third area 304 and the first area 303.
  • D2 is the position of the boundary between the first region 303 and the drift layer 302.
  • Reference numbers 373 and 375 indicate p-type impurity concentration distributions in the first region 303 and the second region 305, respectively
  • reference number 374 indicates an n-type impurity concentration distribution in the third region 304, respectively.
  • the maximum value of the p-type impurity concentration in the distribution 373 is located at the first depth (position between the depths C2 and D2) from the surface of the semiconductor substrate 300, and the curve indicating the concentration distribution is approximately the first. It extends in the area 303.
  • the maximum value of the p-type impurity concentration in the distribution 375 is located at the second depth (depth A1 in this embodiment) from the surface of the semiconductor substrate 300, and the curve indicating the concentration distribution extends to the first region 303. ing.
  • the maximum value of the n-type impurity concentration in the distribution 374 is located at the third depth (position between the depths B2 and C2) from the surface of the semiconductor substrate 300, and the curve indicating the concentration distribution is approximately the third value. It extends in the area 304.
  • the maximum value of the p-type impurity concentration in the first region 303 (the peak concentration value of the distribution 373) is 2 ⁇ 10 16 atoms / cm 3 .
  • the p-type impurity concentration in the second region is highest at the surface of the semiconductor substrate 300 (that is, the depth A2) and is 1 ⁇ 10 17 atoms / cm 3 .
  • the p-type impurity concentration in the third region 304 is lower than 1 ⁇ 10 16 atoms / cm 3 .
  • the p-type impurity concentration of the third region 304 is not more than 1/10 of the p-type impurity concentration at the depth A 2 that is the surface position of the semiconductor substrate 300.
  • a semiconductor substrate 550 is prepared.
  • an n + layer 551 serving as the cathode layer 301 and an n layer 552 serving as the drift layer 302 are stacked in this order from the back surface side.
  • p-type impurity ions are implanted into the n layer 552 at a position that becomes the second depth from the surface of the semiconductor substrate 550.
  • the second depth is a position that is substantially the surface of the semiconductor substrate 550.
  • a p-type ion implantation layer 555 is formed as shown in FIG.
  • p-type impurity ions are implanted into the first depth from the surface of the semiconductor substrate 550 in the ion implantation layer 555, and as shown in FIG. 16, p-type ion implantation is performed.
  • Layer 553 is formed.
  • the first depth is a position deeper than the second depth (position in the negative direction of the z axis).
  • n-type impurity ions are implanted into a position between the first depth and the second depth in the ion implantation layer 555, and as shown in FIG. An injection layer 554 is formed.
  • the semiconductor substrate 550 in the state shown in FIG. 18 is annealed, the semiconductor device 30 having the annealing layer 320 including the first region 303, the second region 305, and the third region 304 can be manufactured as shown in FIG.
  • the third region 304 may be formed by performing n-type ion implantation.
  • the distribution of the p-type impurity concentration having the maximum value in the second region 305 may be spread over the entire anode region 320 as indicated by the distribution 375.
  • FIG. 19 is a longitudinal sectional view of the cell region of the semiconductor device 70 according to the third embodiment.
  • the semiconductor device 70 includes a semiconductor substrate 700 on which an IGBT region 71 and a diode region 72 are formed.
  • a p-type collector layer 711, an n-type buffer layer 712, an n-type drift layer 702, a p-type first body layer 713, A p-type second body layer 714 is laminated.
  • a p-type body contact layer 715 and an n-type emitter layer 716 are formed on the surface of the second body layer 714 and exposed on the surface of the semiconductor substrate 700.
  • the buffer layer 712 and the drift layer 702 extend to the diode region 72.
  • the semiconductor substrate 700 is provided with a trench gate 741 that penetrates the first body layer 713 and the second body layer 714 from the surface to reach the drift region 702.
  • the trench gate 741 is in contact with the emitter layer 716 on its side surface.
  • the first body layer 713, the second body layer 714, and the body contact layer 715 function as a body region in the IGBT region 71.
  • an n-type cathode layer 701, a buffer layer 712, a drift layer 702, a p-type first region 703, and an n-type third region 704 are stacked in that order from the back surface side.
  • a p-type second region 705 is formed on a part of the surface of the third region 704 and is exposed on the surface of the semiconductor substrate 700.
  • the cathode region of the diode region 72 includes a cathode layer 701, a buffer layer 712, and a drift layer 702, and the anode region 720 includes a first region 703, a second region 705, and a third region 704.
  • the semiconductor substrate 700 is provided with a dummy gate 742 that reaches the drift region 702 through the second region 704 and the first region 703 from the surface thereof.
  • the second region 705, the third region 704, the body contact layer 715, and the emitter layer 716 are in contact with the surface electrode 732.
  • the cathode layer 701 and the collector layer 711 are exposed on the back surface of the semiconductor substrate 700 adjacent to each other and are in contact with the back electrode 731.
  • FIG. 20 is a diagram showing a p-type impurity concentration distribution in the depth direction of the anode region 720.
  • the vertical axis indicates the position of the semiconductor substrate 700 in the depth direction.
  • A3 is the position of the upper end of the second region 705
  • B3 is the position of the lower end of the second region 705
  • C3 is the position of the boundary between the third region 704 and the first region 703,
  • D3 is the first region. This is the position of the boundary between 703 and the drift layer 702.
  • Reference numerals 773 and 775 indicate p-type impurity concentration distributions of the first region 703 and the second region 705, respectively.
  • FIG. 21 is a diagram showing a p-type impurity concentration distribution in the depth direction from the body contact layer 715 to the first body layer 713.
  • the vertical axis indicates the position of the semiconductor substrate 700 in the depth direction.
  • A4 is the position of the upper end of the body contact layer 715
  • B4 is the position of the lower end of the body contact layer 715
  • C4 is the position of the boundary between the second body layer 714 and the first body layer 713
  • D4 is the first position.
  • 1 is a boundary position between the body layer 713 and the drift layer 702.
  • Reference numerals 783, 784, and 785 indicate p-type impurity concentration distributions of the first body layer 713 and the second region 705, respectively.
  • the distribution 775 and the distribution 785 may be formed by the same process. Further, the distribution 773 and the distribution 783 may be formed by the same process. As shown in FIG. 21, the body region of IGBT region 71 has a first maximum value (maximum value of distribution 783) of the p-type impurity concentration at a position at the first depth from the surface of semiconductor substrate 700. In addition, the second maximum value (maximum value of the distribution 775) of the p-type impurity concentration is provided at a position closer to the surface side of the semiconductor substrate 700 than the first depth. A region having a relatively low p-type impurity concentration exists between the region having the first maximum value and the region having the second maximum value.
  • the semiconductor device may include a semiconductor element structure other than a diode as a part thereof.
  • the semiconductor device 70 is an RC-IGBT that includes an IGBT region 71 and a diode region 72 in the same semiconductor substrate 700.
  • a lifetime control region for example, a high concentration formed by ion irradiation or the like is used to reduce the carrier lifetime and improve the switching characteristics. In some cases, a region including a crystal defect) is formed. According to the semiconductor device 70, since the amount of holes injected from the anode region to the cathode region can be reduced in the diode region 72, the lifetime control function of the lifetime control region can be reduced.
  • the IGBT region 71 By reducing the lifetime control function, it is possible to suppress the deterioration of the characteristics of the IGBT region 71 due to the lifetime control region and reduce the leakage current.
  • a breakdown voltage is secured in the region having the first maximum value (first body layer 713), and in the region having the second maximum value (body contact layer 715), holes are generated during the IGBT operation. Can be pulled out efficiently.
  • the impurity concentration of the region (second body layer 714) between the region having the first maximum value and the region having the second maximum value n formed along the trench gate 741 during the IGBT operation Type channel control.
  • the configuration of the IGBT region is not limited to the form described in the third embodiment.
  • the IGBT region 71 of the semiconductor substrate 700a may include a region 71a including the emitter layer 716 and a region 71b not including the emitter layer 716.
  • the region 71b a channel is not formed when the gate is turned on, and the channel density of the IGBT region 71 is reduced, so that carriers can be accumulated. For this reason, in the semiconductor device 70a, the on-resistance can be lowered.

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Abstract

　本明細書が開示する第１の半導体装置は、アノード領域と、カソード領域とを有する半導体基板を備えている。アノード領域は、半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の最大値を有する、第１導電型の第１領域と、第１の深さより半導体基板の表面側の第２の深さとなる位置に第１導電型の不純物濃度の最大値を有する第１導電型の第２領域と、第１領域と第２領域との間に設けられ、第１導電型の不純物濃度が半導体基板の表面の１／１０以下である第３領域と、を含む。

Description

半導体装置
　本明細書に記載の技術は、半導体装置に関する。
　ダイオードの素子構造を有する半導体装置では、アノード領域の設計は、耐圧、高速性、低損失性等の特性に影響する。例えば、日本国特許公開公報２００４－８８０１２号（特許文献１）では、高速性および低損失性を向上させるために、カソード領域へのホール注入量を低減する技術を開示している。具体的には、特許文献１には、アノード領域のｐ型の不純物のドーズ量を低減してカソード領域へのホール注入量を低減するために、半導体基板の表面に露出する浅い高濃度のｐ層と、半導体基板の表面に露出する深い低濃度のｐ層とを半導体基板の平面方向に交互に配置している。
特開２００４－８８０１２号公報
　日本国特許公開公報２００４－８８０１２号に記載されているように、カソード領域へのホール注入量を低減するためにアノード領域のｐ型の不純物のドーズ量を低減すると、耐圧が低下する。アノード領域の深さや不純物濃度、不純物のドーズ量は、半導体装置の耐圧の確保のために制限される。従来の半導体装置では、耐圧の確保とホール注入量の低減とを両立することが困難である。
　本明細書が開示する第１の半導体装置は、アノード領域と、カソード領域とを有する半導体基板を備えている。アノード領域は、半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の最大値を有する、第１導電型の第１領域と、第１の深さより半導体基板の表面側の第２の深さとなる位置に第１導電型の不純物濃度の最大値を有する第１導電型の第２領域と、第１領域と第２領域との間に設けられ、第１導電型の不純物濃度が半導体基板の表面の１／１０以下である第３領域と、を含む。
　上記の第１の半導体装置によれば、第１領域と第２領域の間に、第１導電型の不純物濃度が十分に低い第３領域を含むため、第１領域がホール注入量に影響することを抑制できる。耐圧を確保するために第１領域の第１導電型の不純物濃度を高くするともに、ホール注入量を抑制するために第２領域の第１導電型の不純物を低くすることができ、耐圧の確保とホール注入量の低減とを両立することができる。
　上記の第１の半導体装置では、第３領域は、第２導電型の不純物を含む領域であってもよい。さらには、第３領域の少なくとも一部は、半導体基板の表面に露出しており、半導体基板の表面電極とショットキー接合していてもよい。
　上記の半導体装置では、第１領域の第１の深さとなる位置の不純物濃度は、１×１０１６ａｔｏｍｓ／ｃｍ３以下であることが好ましい。
　本明細書が開示する第２の半導体装置は、ダイオード領域と、ＩＧＢＴ領域とを同一の半導体基板に備えている。ダイオード領域は、アノード領域と、カソード領域とを含む。アノード領域は、半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の最大値を有する、第１導電型の第１領域と、第１の深さより半導体基板の表面側の第２の深さとなる位置に第１導電型の不純物濃度の最大値を有する第１導電型の第２領域とを含む。ＩＧＢＴ領域は、第１導電型のボディ領域と、第２導電型のドリフト領域と、第２導電型のエミッタ領域と、第１導電型のコレクタ領域とを含み、ボディ領域は、半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の第１の極大値を有し、かつ、第１の深さより半導体基板の表面側となる位置に第１導電型の不純物濃度の第２の極大値を有する。
　上記の第２の半導体装置によれば、第１の半導体装置と同様に、耐圧を確保するために第１領域の第１導電型の不純物濃度を高くするともに、ホール注入量を抑制するために第２領域の第１導電型の不純物を低くすることができる。また、第１領域と第２領域の間に、第１導電型の不純物濃度が十分に低い第３領域を含むため、第１領域がホール注入量に影響することを抑制できる。また、ＩＧＢＴ領域では、第１の極大値を有する領域において耐圧が確保されるとともに、第２の極大値を有する領域において、ＩＧＢＴ動作時にホールを効率よく引き抜くことができる。
実施例１に係る半導体装置の平面図である。 図１のＩＩ－ＩＩ線断面図である。 図１の半導体装置のアノード領域における不純物濃度分布を概念的に示す図である。 実施例１の半導体装置の製造方法を説明する図である。 実施例１の半導体装置の製造方法を説明する図である。 実施例１の半導体装置の製造方法を説明する図である。 実施例１の半導体装置の製造方法を説明する図である。 変形例に係る半導体装置の縦断面図である。 変形例に係る半導体装置の平面図である。 変形例に係る半導体装置の平面図である。 実施例２に係る半導体装置の縦断面図である。 図１１の半導体装置のアノード領域における不純物濃度分布を概念的に示す図である。 実施例２の半導体装置の製造方法を説明する図である。 実施例２の半導体装置の製造方法を説明する図である。 実施例２の半導体装置の製造方法を説明する図である。 実施例２の半導体装置の製造方法を説明する図である。 実施例２の半導体装置の製造方法を説明する図である。 実施例２の半導体装置の製造方法を説明する図である。 実施例３の半導体装置の縦断面図である。 図１９の半導体装置のアノード領域における不純物濃度分布を概念的に示す図である。 図１９の半導体装置のボディ領域およびその近傍における不純物濃度分布を概念的に示す図である。 変形例に係る半導体装置の縦断面図である。
　図１，２に示すように、半導体装置１０は、セル領域１１と周辺領域１２とを含む半導体基板１００を備えている。なお、図１においては、表面電極１３２の図示を省略している。
　半導体基板１００は、その裏面（ｚ軸の負方向の面）に露出するｎ型のカソード層１０１と、カソード層１０１の表面（ｚ軸の正方向の面）に設けられたｎ型のドリフト層１０２とを備えている。カソード層１０１およびドリフト層１０２は、カソード領域を構成している。カソード層１０１は、裏面電極１３１と接している。セル領域１１では、ドリフト層１０２の表面にアノード領域１２０が備えられており、アノード領域１２０は、ドリフト層１０２の表面に接する第１領域１０３と、半導体基板１００の表面に露出する第２領域１０５と、第１領域１０３と第２領域１０５との間に設けられた第３領域１０４とを含んでいる。第２領域１０５は、表面電極１３２に接している。周辺領域１２では、ドリフト層１０２の表面に、ｐ型のＦＬＲ層１１１，１１２が備えられている。ＦＬＲ層１１１の表面は、半導体基板１００の中央側において表面電極１３２に接し、周辺側において絶縁膜１３３に接している。ＦＬＲ層１１１，１１２は、半導体装置１０の周辺耐圧構造である。周辺耐圧構造の形態は、ＦＬＲ層に限定されず、リサーフ層等の従来公知の構造を用いることができる。
　図３は、アノード領域１２０の深さ方向のｐ型の不純物濃度分布を示す図である。縦軸は半導体基板１００の深さ方向の位置を示している。Ａ１は第２領域１０５の上端の位置であり、Ｂ１は第２領域１０５と第３領域１０４との境界の位置であり、Ｃ１は第３領域１０４と第１領域１０３との境界の位置であり、Ｄ１は第１領域１０３とドリフト層１０２との境界の位置である。参照番号の１７３，１７５は、それぞれ、第１領域１０３、第２領域１０５のｐ型の不純物濃度分布を示している。比較のため、参照番号１７９として、従来の半導体装置のアノード領域のｐ型の不純物濃度分布を併せて図示している。
　分布１７３のｐ型の不純物濃度の最大値は、半導体基板１００の表面から第１の深さに位置し、分布１７５のｐ型の不純物濃度の最大値は、半導体基板１００の表面から第２の深さに位置している。第１領域１０３のｐ型の不純物濃度の最大値（分布１７３のピーク濃度値）は、２×１０１６ａｔｏｍｓ／ｃｍ３である。第２領域のｐ型の不純物濃度は、半導体基板１００の表面（すなわち、深さＡ１）において最も高く、１×１０１７ａｔｏｍｓ／ｃｍ３である。第３領域１０４のｐ型の不純物濃度は、１×１０１６ａｔｏｍｓ／ｃｍ３よりも低い。第３領域１０４のｐ型の不純物濃度は、半導体基板１００の表面位置である深さＡ１におけるｐ型の不純物濃度の１／１０以下である。
　従来の半導体装置では、分布１７９のように、アノード領域のｐ型の不純物濃度は、半導体基板の表面（深さＡ１）を最大として、深くなるに従って低くなる。このため、半導体装置の耐圧を確保するために、アノード領域のカソード領域に近い領域でｐ型の不純物濃度を高くするには、半導体基板表面のｐ型の不純物濃度を高くする必要がある。半導体基板表面のｐ型の不純物濃度が高いと、ホールの注入量が多くなって、半導体装置の高速性および低損失性が低下する。
　これに対して、半導体装置１０では、第１領域１０３のｐ型の不純物濃度の分布１７３と、第２領域１０５のｐ型の不純物濃度の分布１７５とを別個でそれぞれ独自に設計できる。耐圧を高くするためには第１領域１０３のｐ型の不純物濃度のみを適宜高くすればよく、併せて第２領域１０５のｐ型の不純物濃度を高くする必要がない。これによって、第２領域１０５のｐ型の不純物濃度を十分に低くすることができるため、ホール注入量を抑制することができる。また、半導体装置１０は、第１領域１０３と第２領域１０５との間に、ｐ型不純物濃度が低い第３領域１０４を有している。このため、第１領域１０３のｐ型の不純物がホール注入量に影響することを抑制することができる。本実施例のように、第３領域１０４のｐ型の不純物濃度が、半導体基板１００の表面位置である深さＡ１におけるｐ型の不純物濃度の１／１０以下であれば、第１領域１０３のｐ型の不純物濃度がホール注入量に影響することを十分に抑制できる。
　半導体装置１０の製造方法について、図４～６を参照しながら説明する。なお、図４～６では、図２のセル領域１１のみを図示しており、これらの図を用いて、セル領域１１にアノード領域１２０を形成する工程のみを説明する。半導体装置１０のその他の構成は、従来の半導体装置の製造方法と同様の方法によって形成することができる。
　まず、図４に示すように、半導体基板５００を準備する。半導体基板５００は、裏面側から順に、カソード層１０１となるｎ＋層５０１と、ドリフト層１０２となるｎ層５０２が積層されている。この状態で、図４に示すように、ｎ層５０２内の半導体基板５００の表面から第２深さとなる位置にｐ型の不純物イオンを注入する。第２深さは、半導体基板５００のほぼ表面となる位置である。これによって、図５に示すように、ｐ型のイオン注入層５０５を形成する。なお、ｎ＋層５０１は、下記に示す半導体装置１０の表面構造を形成する工程を行った後で、半導体基板５００に形成されてもよい。
　次に、図６に示すように、ｎ層５０２内の半導体基板５００の表面から第１深さとなる位置にｐ型の不純物イオンを注入し、図７に示すように、ｐ型のイオン注入層５０３を形成する。第１深さは、第２深さよりも深い位置（ｚ軸の負方向の位置）である。また、これによって、イオン注入層５０３とイオン注入層５０５との間に、ｐ型の不純物濃度が低い中間層５０４が形成される。図７に示す状態の半導体基板５００をアニール処理すると、図２に示すように、第１領域１０３、第２領域１０５、第３領域１０４を含むアノード領域１２０を有する半導体装置１０を製造できる。
（変形例）
　実施例１では、第２領域１０５が第３領域１０４の表面全体を覆っていたが、これに限定されない。例えば、図８，９に示す半導体装置２０のように、セル領域において、第３領域２０４の表面の一部に第２領域２０５が形成されていてもよい。第２領域２０５は、半導体基板２００の表面を平面視したときに、ｙ方向伸びる縞状に形成されている。半導体基板２００の表面には、第２領域２０５と第３領域２０４が露出し、表面電極１３２と接している。第２領域２０５と表面電極１３２とはオーミック接合しており、第３領域２０４と表面電極１３２とはショットキー接合している。また、図１０に示すように、半導体基板２１０の表面を平面視したとき、第３領域２１４の表面に円形状の第２領域２１５が分布していてもよい。
　図１１は、実施例２に係る半導体装置３０のセル領域の縦断面図を示している。半導体装置３０は、半導体基板３００を備えている。半導体基板３００は、その裏面側から順に積層された、ｎ型のカソード層３０１と、ｎ型のドリフト層３０２と、ｐ型の第１領域３０３と、ｎ型の第３領域３０４と、ｐ型の第２領域３０５とを備えている。カソード層３０１およびドリフト層３０２は、カソード領域を構成している。第１領域３０３、第３領域３０４および第２領域３０５は、アノード領域３２０を構成している。カソード層３０１は、裏面電極１３１と接しており、第２領域３０５は、表面電極１３２と接している。半導体装置３０のその他の構成は、図１に示す半導体装置１０と同様であるため、説明を省略する。
　図１２は、アノード領域３２０の深さ方向の不純物濃度分布を示す図である。縦軸は半導体基板３００の深さ方向の位置を示している。Ａ２は第２領域３０５の上端の位置であり、Ｂ２は第２領域３０５と第３領域３０４との境界の位置であり、Ｃ２は第３領域３０４と第１領域３０３との境界の位置であり、Ｄ２は第１領域３０３とドリフト層３０２との境界の位置である。参照番号の３７３，３７５は、それぞれ、第１領域３０３、第２領域３０５のｐ型の不純物濃度分布を示し、参照番号３７４は、第３領域３０４のｎ型の不純物濃度分布を示している。
　分布３７３のｐ型の不純物濃度の最大値は、半導体基板３００の表面から第１の深さ（深さＣ２とＤ２の間の位置）に位置し、その濃度分布を示す曲線は、概ね第１領域３０３内に広がっている。分布３７５のｐ型の不純物濃度の最大値は、半導体基板３００の表面から第２の深さ（本実施例では深さＡ１）に位置し、濃度分布を示す曲線は、第１領域３０３まで広がっている。分布３７４のｎ型の不純物濃度の最大値は、半導体基板３００の表面から第３の深さに位置（深さＢ２とＣ２の間の位置）し、その濃度分布を示す曲線は、概ね第３領域３０４内に広がっている。
　第１領域３０３のｐ型の不純物濃度の最大値（分布３７３のピーク濃度値）は、２×１０１６ａｔｏｍｓ／ｃｍ３である。第２領域のｐ型の不純物濃度は、半導体基板３００の表面（すなわち、深さＡ２）において最も高く、１×１０１７ａｔｏｍｓ／ｃｍ３である。第３領域３０４のｐ型の不純物濃度は、１×１０１６ａｔｏｍｓ／ｃｍ３よりも低い。第３領域３０４のｐ型の不純物濃度は、半導体基板３００の表面位置である深さＡ２におけるｐ型の不純物濃度の１／１０以下である。
　半導体装置３０の製造方法について、図１３～１８を参照しながら説明する。まず、図１３に示すように、半導体基板５５０を準備する。半導体基板５５０は、裏面側から順に、カソード層３０１となるｎ＋層５５１と、ドリフト層３０２となるｎ層５５２が積層されている。この状態で、図１３に示すように、ｎ層５５２内の半導体基板５５０の表面から第２深さとなる位置にｐ型の不純物イオンを注入する。第２深さは、半導体基板５５０のほぼ表面となる位置である。これによって、図１４に示すように、ｐ型のイオン注入層５５５を形成する。
　次に、図１５に示すように、イオン注入層５５５内の半導体基板５５０の表面から第１深さとなる位置にｐ型の不純物イオンを注入し、図１６に示すように、ｐ型のイオン注入層５５３を形成する。第１深さは、第２深さよりも深い位置（ｚ軸の負方向の位置）である。
　次に、図１７に示すように、イオン注入層５５５内の第１深さと第２深さとの間となる位置にｎ型の不純物イオンを注入し、図１８に示すように、ｎ型のイオン注入層５５４を形成する。図１８に示す状態の半導体基板５５０をアニール処理すると、図１１に示すように、第１領域３０３、第２領域３０５、第３領域３０４を含むアニール層３２０を有する半導体装置３０を製造できる。
　本実施例のように、ｎ型のイオン注入を行うことによって、第３領域３０４を形成してもよい。この場合、第２領域３０５に最大値を有するｐ型の不純物濃度の分布は、分布３７５に示すようにアノード領域３２０全体に広がっていてもよい。
　図１９は、実施例３に係る半導体装置７０のセル領域の縦断面図を示している。半導体装置７０は、ＩＧＢＴ領域７１とダイオード領域７２とが形成された半導体基板７００を備えている。半導体基板７００のＩＧＢＴ領域７１には、その裏面側から順に、ｐ型のコレクタ層７１１と、ｎ型のバッファ層７１２と、ｎ型のドリフト層７０２と、ｐ型の第１ボディ層７１３と、ｐ型の第２ボディ層７１４が積層されている。第２ボディ層７１４の表面に、ｐ型のボディコンタクト層７１５およびｎ型のエミッタ層７１６が形成され、半導体基板７００の表面に露出している。バッファ層７１２およびドリフト層７０２は、ダイオード領域７２まで伸びている。半導体基板７００には、その表面から第１ボディ層７１３および第２ボディ層７１４を貫通してドリフト領域７０２に達するトレンチゲート７４１が設けられている。トレンチゲート７４１は、その側面においてエミッタ層７１６と接している。第１ボディ層７１３と、第２ボディ層７１４と、ボディコンタクト層７１５とは、ＩＧＢＴ領域７１におけるボディ領域として機能する。
　ダイオード領域７２には、その裏面側から順に、ｎ型のカソード層７０１と、バッファ層７１２と、ドリフト層７０２と、ｐ型の第１領域７０３と、ｎ型の第３領域７０４が積層されている。第３領域７０４の表面の一部に、ｐ型の第２領域７０５が形成され、半導体基板７００の表面に露出している。ダイオード領域７２のカソード領域は、カソード層７０１と、バッファ層７１２と、ドリフト層７０２によって構成され、アノード領域７２０は、第１領域７０３と、第２領域７０５と、第３領域７０４によって構成されている。半導体基板７００には、その表面から第２領域７０４および第１領域７０３を貫通してドリフト領域７０２に達するダミーゲート７４２が設けられている。
　第２領域７０５、第３領域７０４、ボディコンタクト層７１５およびエミッタ層７１６は、表面電極７３２と接している。カソード層７０１とコレクタ層７１１とは、互いに隣接して半導体基板７００の裏面に露出しており、裏面電極７３１に接している。
　図２０は、アノード領域７２０の深さ方向のｐ型の不純物濃度分布を示す図である。縦軸は半導体基板７００の深さ方向の位置を示している。Ａ３は第２領域７０５の上端の位置であり、Ｂ３は第２領域７０５の下端の位置であり、Ｃ３は第３領域７０４と第１領域７０３との境界の位置であり、Ｄ３は第１領域７０３とドリフト層７０２との境界の位置である。参照番号の７７３，７７５は、それぞれ、第１領域７０３、第２領域７０５のｐ型の不純物濃度分布を示している。
　図２１は、ボディコンタクト層７１５から第１ボディ層７１３までの深さ方向のｐ型の不純物濃度分布を示す図である。縦軸は半導体基板７００の深さ方向の位置を示している。Ａ４はボディコンタクト層７１５の上端の位置であり、Ｂ４はボディコンタクト層７１５の下端の位置であり、Ｃ４は第２ボディ層７１４と第１ボディ層７１３との境界の位置であり、Ｄ４は第１ボディ層７１３とドリフト層７０２との境界の位置である。参照番号の７８３，７８４，７８５は、それぞれ、第１ボディ層７１３、第２領域７０５のｐ型の不純物濃度分布を示している。分布７７５と分布７８５とは、同一工程によって形成されてもよい。また、分布７７３と分布７８３とは、同一工程によって形成されてもよい。図２１に示すように、ＩＧＢＴ領域７１のボディ領域は、半導体基板７００の表面から第１の深さとなる位置にｐ型の不純物濃度の第１の極大値（分布７８３の最大値）を有し、かつ、第１の深さより半導体基板７００の表面側となる位置にｐ型の不純物濃度の第２の極大値（分布７７５の最大値）を有する。第１の極大値を有する領域と第２の極大値を有する領域の間には、ｐ型の不純物濃度が比較的低い領域が存在している。
　本実施例のように、半導体装置は、ダイオード以外の半導体素子構造をその一部に含んでいてもよい。半導体装置７０は、ＩＧＢＴ領域７１と、ダイオード領域７２とを同一の半導体基板７００に含むＲＣ－ＩＧＢＴである。ＲＣ－ＩＧＢＴにおいては、ダイオード領域７２内のドリフト層７０２内に、キャリアのライフタイムを低減してスイッチング特性を向上させるために、ライフタイム制御領域（例えば、イオン照射等によって形成される高濃度に結晶欠陥を含む領域）を形成する場合がある。半導体装置７０によれば、ダイオード領域７２において、アノード領域からカソード領域へのホール注入量を低減することができるため、ライフタイム制御領域のライフタイム制御機能を低減することができる。ライフタイム制御機能を低減させることで、ライフタイム制御領域に起因するＩＧＢＴ領域７１の特性悪化を抑制し、リーク電流を低減することができる。また、ＩＧＢＴ領域７１では、第１の極大値を有する領域（第１ボディ層７１３）において耐圧が確保されるとともに、第２の極大値を有する領域（ボディコンタクト層７１５）において、ＩＧＢＴ動作時にホールを効率よく引き抜くことができる。第１の極大値を有する領域と第２の極大値を有する領域の間の領域（第２ボディ層７１４）の不純物濃度を調整することによって、ＩＧＢＴ動作時にトレンチゲート７４１に沿って形成されるｎ型のチャネル制御を行うことができる。
（変形例）
　ＩＧＢＴ領域の構成は、実施例３で説明した形態に限定されない。例えば、図２２に示す半導体装置７０ａのように、半導体基板７００ａのＩＧＢＴ領域７１は、エミッタ層７１６を含む領域７１ａと、エミッタ層７１６を含まない領域７１ｂとを含んでいてもよい。領域７１ｂでは、ゲートオン時にチャネルが形成されず、ＩＧＢＴ領域７１のチャネル密度が低くなるため、キャリアを蓄積することができる。このため、半導体装置７０ａでは、オン抵抗を低くすることができる。
　以上、本発明の実施例について詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
　本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。

 

Claims (5)

  1. 　アノード領域と、カソード領域とを有する半導体基板を備えた半導体装置であって、
    　アノード領域は、
    　　半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の最大値を有する、第１導電型の第１領域と、
    　　第１の深さより半導体基板の表面側の第２の深さとなる位置に第１導電型の不純物濃度の最大値を有する第１導電型の第２領域と、
    　　第１領域と第２領域との間に設けられ、第１導電型の不純物濃度が半導体基板の表面の１／１０以下である第３領域と、を含む、半導体装置。
  2. 　第３領域は、第２導電型の不純物を含む領域である、請求項１に記載の半導体装置。
  3. 　第３領域の少なくとも一部は、半導体基板の表面に露出しており、半導体基板の表面電極とショットキー接合する、請求項２に記載の半導体装置。
  4. 　第１領域の第１の深さとなる位置の不純物濃度は、１×１０１６ａｔｏｍｓ／ｃｍ３以下である、請求項１～３のいずれか一項に記載の半導体装置。
  5. 　ダイオード領域と、ＩＧＢＴ領域とを同一の半導体基板に備えており、
    　ダイオード領域は、アノード領域と、カソード領域とを含み、
    　アノード領域は、
    　　半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の最大値を有する、第１導電型の第１領域と、
    　　第１の深さより半導体基板の表面側の第２の深さとなる位置に第１導電型の不純物濃度の最大値を有する第１導電型の第２領域とを含み、
    　ＩＧＢＴ領域は、第１導電型のボディ領域と、第２導電型のドリフト領域と、第２導電型のエミッタ領域と、第１導電型のコレクタ領域とを含み、
    　　ボディ領域は、半導体基板の表面から第１の深さとなる位置に第１導電型の不純物濃度の第１の極大値を有し、かつ、第１の深さより半導体基板の表面側となる位置に第１導電型の不純物濃度の第２の極大値を有する、半導体装置。
     
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