CN104838503A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104838503A
CN104838503A CN201280077544.7A CN201280077544A CN104838503A CN 104838503 A CN104838503 A CN 104838503A CN 201280077544 A CN201280077544 A CN 201280077544A CN 104838503 A CN104838503 A CN 104838503A
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亀山悟
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Toyota Motor Corp
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Abstract

本说明书公开的第一半导体装置具备了具有阳极区与阴极区的半导体基板。阳极区包括：第一导电型的第一区域，其在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的最大值；第一导电型的第二区域，其在与第一深度相比靠半导体基板的表面侧的第二深度的位置处具有第一导电型的杂质浓度的最大值；第三区域，其被设置于第一区域与第二区域之间，并且所述第三区域的第一导电型的杂质浓度为半导体基板的表面的1/10以下。

Description

半导体装置
技术领域
本说明书中记载的技术涉及一种半导体装置。
背景技术
在具有二级管的元件结构的半导体装置中，阳极区的设计会对耐压、高速性、低损失性等特性产生影响。例如，在日本专利公开公报2004-88012号(专利文献1)中公开了如下的技术，即，为了提高高速性以及低损失性而降低向阴极区的空穴注入量的技术。具体而言，在专利文献1中，为了降低阳极区的p型的杂质的注入量并且降低向阴极区的空穴注入量，从而在半导体基板的平面方向上交替地配置有在半导体基板的表面上露出的高浓度的较浅的p层、和在半导体基板的表面上露出的低浓度的较深的p层。
在先技术文献
专利文献
专利文献1：日本特开2004－88012号公报
发明内容
发明所要解决的课题
如日本专利公开公报2004-88012号中所记载那样，当为了降低向阴极区的空穴注入量而降低阳极区的p型的杂质的注入量时，耐压将下降。为了確保半导体装置的耐压，阳极区的深度或杂质浓度、杂质的注入量是被限制的。在现有的半导体装置中，难以使耐压的確保和空穴注入量的降低这两者兼顾。
用于解决课题的方法
本说明书所公开的第一半导体装置具备了具有阳极区与阴极区的半导体基板。阳极区包括：第一导电型的第一区域，其在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的最大值；第一导电型的第二区域，其在与第一深度相比靠半导体基板的表面侧的第二深度的位置处具有第一导电型的杂质浓度的最大值；第三区域，其被设置于第一区域与第二区域之间，并且所述第三区域的第一导电型的杂质浓度为半导体基板的表面的1/10以下。
根据上述的第一半导体装置，由于在第一区域与第二区域之间包括第一导电型的杂质浓度足够低的第三区域，因此能够抑制第一区域对空穴注入量造成影响的情况。能够在为了确保耐压而提高第一区域的第一导电型的杂质浓度的同时，为了抑制空穴注入量而减少第二区域的第一导电型的杂质，从而能够同时实现耐压的確保与空穴注入量的降低。
在上述的第一半导体装置中，第三区域也可以是包含第二导电型的杂质的区域。另外，也可以使第三区域的至少一部分露出于半导体基板的表面，并且与半导体基板的表面电极进行肖特基接合。
在上述的半导体装置中，优选为，第一区域的第一深度的位置的杂质浓度为1×1016atoms/cm3以下。
本说明书所公开的第二半导体装置在同一半导体基板上具备二极管区与IGBT区。二极管区包含阳极区与阴极区。阳极区包含：第一导电型的第一区域，其在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的最大值；第一导电型的第二区域，其在与第一深度相比靠半导体基板的表面侧的第二深度的位置处具有第一导电型的杂质浓度的最大值。IGBT区包含第一导电型的体区、第二导电型的漂移区、第二导电型的发射区、第一导电型的集电区，体区在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的第一极大值，并且在与第一深度相比靠半导体基板的表面侧的位置处具有第一导电型的杂质浓度的第二极大值。
根据上述的第二半导体装置，与第一半导体装置相同地，能够在为了确保耐压而提高第一区域的第一导电型的杂质浓度的同时，为了抑制空穴注入量而减少第二区域的第一导电型的杂质。另外，由于在第一区域与第二区域之间包含第一导电型的杂质浓度足够低的第三区域，因此能够抑制第一区域对空穴注入量造成影响。另外，在IGBT区域中，能够在具有第一极大值的区域中确保耐压的同时，在具有第二极大值的区域中，在IGBT工作时有效地除去空穴。
附图说明
图1为实施例1所涉及的半导体装置的俯视图。
图2为图1的II-II线剖视图。
图3为概念性地表示图1的半导体装置的阳极区中的杂质浓度分布的图。
图4为对实施例1的半导体装置的制作方法进行说明的图。
图5为对实施例1的半导体装置的制作方法进行说明的图。
图6为对实施例1的半导体装置的制作方法进行说明的图。
图7为对实施例1的半导体装置的制作方法进行说明的图。
图8为改变例所涉及的半导体装置的纵剖视图。
图9为改变例所涉及的半导体装置的俯视图。
图10为改变例所涉及的半导体装置的俯视图。
图11为实施例2所涉及的半导体装置的纵剖视图。
图12为概念性地表示图11的半导体装置的阳极区中的杂质浓度分布的图。
图13为对实施例2的半导体装置的制作方法进行说明的图。
图14为对实施例2的半导体装置的制作方法进行说明的图。
图15为对实施例2的半导体装置的制作方法进行说明的图。
图16为对实施例2的半导体装置的制作方法进行说明的图。
图17为对实施例2的半导体装置的制作方法进行说明的图。
图18为对实施例2的半导体装置的制作方法进行说明的图。
图19为实施例3的半导体装置的纵剖视图。
图20为概念性地表示图19的半导体装置的阳极区中的杂质浓度分布的图。
图21为概念性地表示图19的半导体装置的体区以及其附近的杂质浓度分布的图。
图22为改变例所涉及的半导体装置的纵剖视图。
具体实施方式
实施例1
如图1、2所示，半导体装置10具备包含元件区域11与周边区域12的半导体基板100。另外，在图1中，省略了表面电极132的图示。
半导体基板100具备：露出于半导体基板100的背面(z轴的负方向的面)的n型阴极层101、和被设置在阴极层101的表面(z轴的正方向的面)上的n型的漂移层102。阴极层101以及漂移层102构成阴极区域。阴极层101与背面电极131相接。在元件区域11中，在漂移层102的表面上具备阳极区120，阳极区120包括：与漂移层102的表面相接的第一区域103、露出于半导体基板100的表面的第二区域105、被设置在第一区域103与第二区域105之间的第三区域104。第二区域105与表面电极132相接。在周边区域12中，在漂移层102的表面上具备p型的FLR层111、112。FLR层111的表面在半导体基板100的中央侧与表面电极132相接，在周边侧与绝缘膜133相接。FLR层111、112为半导体装置10的周边耐压结构。周边耐压结构的方式并不限定于FLR层，还能够使用降低表面电场(REduced SURfaceField：RESURF)层等的现有公知的结构。
图3为表示阳极区120的深度方向上的p型的杂质浓度分布的图。纵轴示出了半导体基板100的深度方向上的位置。A1为第二区域105的上端的位置，B1为第二区域105与第三区域104的边界的位置，C1为第三区域104与第一区域103的边界的位置，D1为第一区域103与漂移层102的边界的位置。参照符号173、175分别示出了第一区域103、第二区域105的p型的杂质浓度分布。为了进行比较，一并图示了参照符号为179的现有的半导体装置的阳极区的p型的杂质浓度分布。
分布173的p型的杂质浓度的最大值位于离半导体基板100的表面第一深度的位置处，分布175的p型的杂质浓度的最大值位于离半导体基板100的表面第二深度的位置处。第一区域103的p型的杂质浓度的最大值(分布173的峰值浓度值)为2×1016atoms/cm3。第二区域的p型的杂质浓度在半导体基板100的表面(即、深度A1)处最高，为1×1017atoms/cm3。第三区域104的p型的杂质浓度低于1×1016atoms/cm3。第三区域104的p型的杂质浓度为，作为半导体基板100的表面位置的深度A1处的p型的杂质浓度的1/10以下。
在现有的半导体装置中，如分布179所示，阳极区的p型的杂质浓度在半导体基板的表面(深度A1)处为最大，且随着变深而降低。因此，为了确保半导体装置的耐压，在阳极区的靠近阴极区的区域中提高p型的杂质浓度时，需要提高半导体基板表面的p型的杂质浓度。当半导体基板表面的p型的杂质浓度较高时，空穴的注入量将增多，从而将降低半导体装置的高速性以及低损失性。
相对于此，在半导体装置10中，能够对第一区域103的p型的杂质浓度的分布173、与第二区域105的p型的杂质浓度的分布175独立地分别单独地进行设计。为了提高耐压，只要适当地提高第一区域103的p型的杂质浓度即可，无需一并提高第二区域105的p型的杂质浓度。由此，由于能够将第二区域105的p型的杂质浓度设为足够低，因此能够抑制空穴注入量。另外，半导体装置10中，在第一区域103与第二区域105之间具有p型杂质浓度较低的第三区域104。因此，能够抑制第一区域103的p型的杂质对空穴注入量造成影响。如本实施例，如果第三区域104的p型的杂质浓度为，作为半导体基板100的表面位置的深度A1处的p型的杂质浓度的1/10以下，则能够充分抑制第一区域103的p型的杂质浓度对空穴注入量造成影响的情况。
参照图4～6对半导体装置10的制造方法进行说明。另外，在图4～6中，仅图示了图2的元件区域11，使用这些图，仅对在元件区域11上形成阳极区120的工序进行说明。半导体装置10的其他结构能够通过与现有的半导体装置的制作方法相同的方法而形成。
首先，如图4所示，准备半导体基板500。半导体基板500从背面侧起依次层叠有成为阴极层101的n+层501、成为漂移层102的n层502。在该状态下，如图4所示，在n层502内的离半导体基板500的表面第二深度的位置处注入p型的杂质离子。第二深度为，半导体基板500的大致表面的位置。由此，如图5所示，形成p型的离子注入层505。另外，也可以在实施了下文叙述的形成半导体装置10的表面结构的工序之后，在半导体基板500上形成n+层501。
接下来，如图6所示，在n层502内的离半导体基板500的表面第一深度的位置处注入p型的杂质离子，如图7所示，形成p型的离子注入层503。第一深度为深于第二深度的位置(z轴的负方向的位置)。另外，由此，在离子注入层503与离子注入层505之间，形成p型的杂质浓度较低的中間层504。当对图7中所示的状态的半导体基板500进行退火处理时，如图2所示，能够制作具有包括第一区域103、第二区域105、第三区域104在内的阳极区120的半导体装置10。
(改变例)
虽然在实施例1中，第二区域105覆盖了第三区域104的整个表面，但并不限定于此。例如，如图8、9所示的半导体装置20，在元件区域中，也可以在第三区域204的表面的一部分上形成有第二区域205。第二区域205在俯视观察半导体基板200的表面时，形成为向y方向延伸的条纹状。在半导体基板200的表面上，第二区域205与第三区域204露出，并与表面电极132相接。第二区域205与表面电极132进行欧姆接合，第三区域204与表面电极132进行肖特基接合。另外，如图10所示，在俯视观察半导体基板210的表面时，也可以在第三区域214的表面上分布有圆形形状的第二区域215。
实施例2
图11为示出了实施例2所涉及的半导体装置30的元件区域的纵剖视图。半导体装置30具备半导体基板300。半导体基板300具备从半导体基板300的背面侧起依次被层叠的n型的阴极层301、n型的漂移层302、p型的第一区域303、n型的第三区域304、p型的第二区域305。阴极层301以及漂移层302构成阴极区。第一区域303、第三区域304以及第二区域305构成了阳极区320。阴极层301与背面电极131相接，第二区域305与表面电极132相接。半导体装置30的其他的结构与如图1所示的半导体装置10相同，所以省略说明。
图12为表示阳极区320的深度方向上的杂质浓度分布的图。纵轴示出了半导体基板300的深度方向上的位置。A2为第二区域305的上端的位置，B2为第二区域305与第三区域304的边界的位置，C2为第三区域304与第一区域303的边界的位置，D2为第一区域303与漂移层302的边界的位置。符号373、375分别表示第一区域303、第二区域305的p型的杂质浓度分布，参照符号374示出了第三区域304的n型的杂质浓度分布。
分布373的p型的杂质浓度的最大值位于离半导体基板300的表面第一深度(深度C2与D2之间的位置)的位置处，表示其浓度分布的曲线为，大致在第一区域303内延伸。分布375的p型的杂质浓度的最大值位于离半导体基板300的表面第二深度(在本实施例中深度A1)的位置处，表示浓度分布的曲线延伸至第一区域303。分布374的n型的杂质浓度的最大值位于离半导体基板300的表面第三深度(深度B2与C2之间的位置)的位置处，表示其浓度分布的曲线大致在第三区域304内延伸。
第一区域303的p型的杂质浓度的最大值(分布373的峰值浓度值)为2×1016atoms/cm3。第二区域的p型的杂质浓度为在半导体基板300的表面(即深度A2)处最高，且为1×1017atoms/cm3。第三区域304的p型的杂质浓度低于1×1016atoms/cm3。第三区域304的p型的杂质浓度为，作为半导体基板300的表面位置的深度A2处的p型的杂质浓度的1/10以下。
参照图13～18对半导体装置30的制作方法进行说明。首先，如图13所示，准备半导体基板550。半导体基板550从背面侧起依次层叠有成为阴极层301的n+层551、成为漂移层302的n层552。在该状态下，如图13所示，n层552内的离半导体基板550的表面第二深度的位置处注入p型的杂质离子。第二深度为，半导体基板550的大致表面的位置。由此，如图14所示，形成p型的离子注入层555。
接下来，如图15所示，离子注入层555内的离半导体基板550的表面第一深度的位置处注入p型的杂质离子，如图16所示，形成p型的离子注入层553。第一深度为深于第二深度的位置(z轴的负方向的位置)。
接下来，如图17所示，在离子注入层555内的第一深度与第二深度之间的位置处注入n型的杂质离子，从而如图18所示，形成n型的离子注入层554。当对图18中所示的状态的半导体基板550进行退火处理时，如图11所示，能够制作出具有包括第一区域303、第二区域305、第三区域304在内的退火层320的半导体装置30。
如本实施例，也可以通过实施n型的离子注入，从而形成第三区域304。在该种情况下，在第二区域305上具有最大值的p型的杂质浓度的分布如分布375所示那样能够在整个阳极区320中延伸。
实施例3
图19示出了实施例3所涉及的半导体装置70的元件区域的纵剖视图。半导体装置70具备了形成有IGBT区71与二级管区72的半导体基板700。在半导体基板700的IGBT区71中，从其背面侧起依次层叠有p型的集电层711、n型的缓冲层712、n型的漂移层702、p型的第一体层713、p型的第二体层714。在第二体层714的表面上形成有p型的体接触层715以及n型的发射层716，并且露出于半导体基板700的表面。缓冲层712以及漂移层702延伸至二级管区域72。在半导体基板700中设置有沟槽栅741，该沟槽栅741从该半导体基板700的表面起贯穿第一体层713以及第二体层714而到达漂移区域702。沟槽栅741在其侧面与发射层716相接。第一体层713、第二体层714、体接触层715作为IGBT区71中的体区而发挥作用。
二级管区72中，从其背面侧起依次层叠有n型的阴极层701、缓冲层712、漂移层702、p型的第一区域703、n型的第三区域704。在第三区域704的表面的一部分上形成有p型的第二区域705，并且露出于半导体基板700的表面。二级管区72的阴极区由阴极层701、缓冲层712、漂移层702构成，阳极区720由第一区域703、第二区域705、第三区域704构成。在半导体基板700中设置有，从该半导体基板700表面起贯穿第二区域704以及第一区域703而达到漂移区域702的假设栅极742。
第二区域705、第三区域704、体接触层715以及发射层716与表面电极732相接。阴极层701与集电层711相互邻接并露出于半导体基板700的背面，并与背面电极731相接。
图20为表示阳极区720的深度方向的p型的杂质浓度分布的图。纵轴示出了半导体基板700的深度方向上的位置。A3为第二区域705的上端的位置，B3为第二区域705的下端的位置，C3为第三区域704与第一区域703的边界的位置，D3为第一区域703与漂移层702的边界的位置。参照符号773、775分别表示第一区域703、第二区域705的p型的杂质浓度分布。
图21为表示从体接触层715起至第一体层713为止的深度方向的p型的杂质浓度分布的图。纵轴表示半导体基板700的深度方向上的位置。A4为体接触层715的上端的位置，B4为体接触层715的下端的位置，C4为第二体层714与第一体层713的边界的位置，D4为第一体层713与漂移层702的边界的位置。参照符号783、784、785分别表示第一体层713、第二区域705的p型的杂质浓度分布。分布775与分布785还可以通过同一工序而被形成。另外，分布773与分布783还可以通过同一工序而被形成。如图21所示，IGBT区71的体区在离半导体基板700的表面第一深度的位置处具有p型的杂质浓度的第一极大值(分布783的最大值)，而且，在与第一深度相比靠半导体基板700的表面侧的位置处具有p型的杂质浓度的第二极大值(分布775的最大值)。具有第一极大值的区域与具有第二极大值的区域之间，存在p型的杂质浓度比较低的区域。
如本实施例这样，半导体装置也可以在其一部分上包含除二级管以外的半导体元件结构。半导体装置70为在同一半导体基板700上包含IGBT区71与二级管区72的RC-IGBT。在RC-IGBT中，在二级管区域72内的漂移层702内，为了减少载流子的寿命并提高开关元件特性而有时会形成寿命控制区域(例如，通过离子照射等而形成的在高浓度中包含结晶缺陷的区域)。根据半导体装置70，由于在二级管区域72中，能够降低从阳极区向阴极区的空穴注入量，因此能够降低寿命控制区域的寿命控制功能。通过使寿命控制功能降低，从而抑制了因寿命控制区域而引起的IGBT区71的特性恶化，从而能够减少漏电。另外，在IGBT区71中，能够在具有第一极大值的区域(第一体层713)中確保耐压的同时，在具有第二极大值的区域(体接触层715)中，IGBT工作时高效地去除空穴。通过对具有第一极大值的区域与具有第二最大值的区域之间的区域(第二体层714)的杂质浓度进行调节，从而能够实施在IGBT工作时沿着沟槽栅741而被形成的n型的沟道控制。
(改变例)
IGBT区的结构并不限定于实施例3中所进行说明的方式。例如，如图22所示的半导体装置70a，半导体基板700a的IGBT区71还可以包含：包括发射层716的区域71a、和未包括发射层716的区域71b。由于在区域71b中，栅极导通(on)时不形成沟道，IGBT区71的沟道密度变低，因此能够蓄积载流子。因此，在半导体装置70a中，能够降低通态电阻。
虽然以上对本发明的实施例进行了详细的说明，但这些仅为示例，而并非为权利要求书进行限定的内容。在权利要求书中记载的技术中，包括对以上例示的具体例进行各种变形、変更的内容。
本说明书或附图中所说明的技术要素可以单独或通过各种组合来发挥技术上的有用性，而并不限定于申请时权利要求所记载的组合。此外，本说明书或附图所例示的技术能够同时实现多个目的，并且实现其中一个目的本身也具有技术上的有用性。

Claims (5)

1.一种半导体装置，其具备了具有阳极区与阴极区的半导体基板，其中，
阳极区包括：
第一导电型的第一区域，其在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的最大值；
第一导电型的第二区域，其在与第一深度相比靠半导体基板的表面侧的第二深度的位置处具有第一导电型的杂质浓度的最大值；
第三区域，其被设置于第一区域与第二区域之间，并且所述第三区域的第一导电型的杂质浓度为半导体基板的表面的1/10以下。
2.如权利要求1所述的半导体装置，其中，
第三区域为包含第二导电型的杂质的区域。
3.如权利要求2所述的半导体装置，其中，
第三区域的至少一部分露出于半导体基板的表面，并且与半导体基板的表面电极进行肖特基接合。
4.如权利要求1至3中任一项所述的半导体装置，其中，
第一区域的第一深度的位置的杂质浓度为1×1016atoms/cm3以下。
5.一种半导体装置，其中，
在同一半导体基板上具备二极管区与绝缘栅双极性晶体管区，
二极管区包含阳极区与阴极区，
阳极区包含：
第一导电型的第一区域，其在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的最大值；
第一导电型的第二区域，其在与第一深度相比靠半导体基板的表面侧的第二深度的位置处具有第一导电型的杂质浓度的最大值，
绝缘栅双极性晶体管区包含第一导电型的体区、第二导电型的漂移区、第二导电型的发射区、第一导电型的集电区，
体区在离半导体基板的表面第一深度的位置处具有第一导电型的杂质浓度的第一极大值，并且在与第一深度相比靠半导体基板的表面侧的位置处具有第一导电型的杂质浓度的第二极大值。
CN201280077544.7A 2012-12-05 2012-12-05 半导体装置 Pending CN104838503A (zh)

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