CN108735737B - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN108735737B
CN108735737B CN201810373333.7A CN201810373333A CN108735737B CN 108735737 B CN108735737 B CN 108735737B CN 201810373333 A CN201810373333 A CN 201810373333A CN 108735737 B CN108735737 B CN 108735737B
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CN108735737A (zh
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中村浩之
曾根田真也
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Abstract

目的在于提供能够降低恢复电流的技术。半导体装置具有半导体衬底，半导体衬底具有第1主面以及第2主面，该半导体衬底被规定出配置有续流二极管的第1区域、配置有IGBT的第2区域、和在俯视观察时将第1区域以及第2区域包围的耐压保持区域。半导体衬底具有：阳极层，其配置于第1区域的第1主面，呈第1导电型；扩散层，其与阳极层相邻地配置于耐压保持区域的第1主面，呈第1导电型。与阳极层和扩散层之间的边界相比在阳极层侧的第1主面配置有第1沟槽。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及电力用半导体装置等半导体装置及其制造方法。
背景技术
作为电力用半导体装置的功率器件在家电产品、电动汽车以及铁路这样的领域乃至作为可再生能源的发电而备受瞩目的太阳能发电以及风力发电的领域被广泛地使用。在这些领域中，大多通过由功率器件构建的逆变器电路，对感应电动机等电感性负载进行驱动。就对电感性负载进行驱动的结构而言，具有续流二极管(以下记作“FWD”)，该续流二极管用于使通过电感性负载的反电动势产生的电流回流。此外，通常的逆变器电路由多个绝缘栅极型双极晶体管(以下记作“IGBT”)和多个FWD构成。
然而，就逆变器电路而言，强烈期望小型轻量化以及低成本化，不希望将多个IGBT和多个FWD独立搭载于逆变器电路。作为其解决方法之一，正在推进IGBT和FWD一体化的反向导通型IGBT(以下记作“RC-IGBT”)的开发，就应用了上述技术的结构而言，能够实现半导体装置的搭载面积缩小、低成本化。
就RC-IGBT而言，是在不具有反向导通性能的通常的IGBT的仅配置有p型集电极层的面，配置有作为IGBT的p型集电极层和作为FWD的n型阴极层。并且，在RC-IGBT的与该面相反侧的面配置有：作为IGBT的p型基极层；作为FWD的p型阳极层；以及在俯视观察时将所述p型基极层和所述p型阳极层包围的耐压保持区域的p型扩散层。此外，在例如非专利文献1、专利文献1～3等公开了RC-IGBT。
专利文献1：日本特开2008-53648号公报
专利文献2：日本特开2008-103590号公报
专利文献3：日本特开2008-109028号公报
非专利文献1:Takahashi H，et al，“1200V Reverse Conducting IGBT”，Proceeding of ISPSD，2004年，p.133-136
然而，就RC-IGBT而言，存在下述问题，即，在FWD从接通状态变成断开状态时，流过与作为二极管通常应流过的电流(正向电流)反向的电流即恢复电流，该恢复电流成为能量损失的原因。
发明内容
因此，本发明就是为了解决上述的问题而提出的，其目的在于提供能够降低恢复电流的技术。
本发明涉及的半导体装置具有：半导体衬底，其具有第1主面以及第2主面，该半导体衬底被规定出配置有续流二极管的第1区域、配置有IGBT(Insulated Gate BipolarTransistor)的第2区域、和在俯视观察时将所述第1区域以及所述第2区域包围的耐压保持区域；表面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第1主面之上；以及背面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第2主面之上，所述半导体衬底具有：阳极层，其配置于所述第1区域的所述第1主面，呈第1导电型；扩散层，其与所述阳极层相邻地配置于所述耐压保持区域的所述第1主面，呈所述第1导电型；以及阴极层，其配置于所述第1区域的所述第2主面，呈第2导电型，与所述阳极层和所述扩散层之间的边界相比在所述阳极层侧的所述第1主面配置有第1沟槽。
发明的效果
根据本发明，与阳极层和扩散层之间的边界相比在阳极层侧的第1主面配置有第1沟槽。由此，能够降低恢复电流。
附图说明
图1是表示实施方式1涉及的半导体装置的结构的剖视图。
图2是表示实施方式2涉及的半导体装置的结构的俯视图。
图3是表示实施方式3涉及的半导体装置的结构的剖视图。
图4是表示实施方式4涉及的半导体装置的结构的剖视图。
图5是表示实施方式5涉及的半导体装置的结构的剖视图。
图6是表示实施方式6涉及的半导体装置的结构的剖视图。
图7是表示实施方式7涉及的半导体装置的结构的俯视图。
图8是表示实施方式7涉及的半导体装置的结构的剖视图。
图9是表示相关半导体装置的结构的俯视图。
图10是表示相关半导体装置的结构的剖视图。
标号的说明
1FWD区域，2IGBT区域，3耐压保持区域，11半导体衬底，13p型阳极层，14第1p型扩散层，16n型阴极层，24表面电极，25背面电极，31第1沟槽，32第2沟槽，35分离区域。
具体实施方式
<相关半导体装置>
首先，在对本发明的实施方式涉及的半导体装置进行说明之前，对与其相关的电力用半导体装置(以下，记作“相关半导体装置”)进行说明。
图9是表示相关半导体装置的结构的俯视图，图10是沿图9的A1-A2线的示出该结构的剖视图。
如图9所示，相关半导体装置具有被规定出FWD区域1、IGBT区域2和耐压保持区域3的半导体衬底11，该FWD区域1是配置有FWD的第1区域，该IGBT区域2是配置有IGBT的第2区域。2个IGBT区域2在俯视观察时将FWD区域1夹着，耐压保持区域3在俯视观察时将FWD区域1以及该2个IGBT区域2包围。另外，相关半导体装置具有栅极焊盘51，该栅极焊盘51配置于IGBT区域2。
下面，将第1导电型设为n型，将第2导电型设为p型进行说明。另外，下面，将半导体衬底11的第1主面设为图10中的半导体衬底11的上表面，进一步来说，设为FWD区域1、IGBT区域2以及耐压保持区域3各自的上表面，将半导体衬底11的第2主面设为图10中的半导体衬底11的下表面，进一步来说，设为FWD区域1、IGBT区域2以及耐压保持区域3各自的下表面而进行说明。
如图10所示，相关半导体装置的半导体衬底11具有：n型漂移层12、p型阳极层13、n型缓冲层15、n型阴极层16、第2p型扩散层17以及作为扩散层的第1p型扩散层14。另外，虽然未图示，但半导体衬底11例如具有n型发射极层、p型基极层以及p型集电极层等IGBT的结构要素。
就n型漂移层12而言，n型的杂质浓度相对低，是横跨FWD区域1、IGBT区域2以及耐压保持区域3而配置的。
FWD的p型阳极层13配置于FWD区域1的上表面，配置于n型漂移层12的上表面之上。
未图示的IGBT的n型发射极层以及p型基极层配置于IGBT区域2的上表面，配置于n型漂移层12的上表面之上。上述n型发射极层以及p型基极层构成作为IGBT的一部分的MOSFET(Metal Oxide Semiconductor Field Effect Transistor)。另外，IGBT的p型基极层与FWD的p型阳极层13相邻。
第1p型扩散层14配置于耐压保持区域3的上表面，配置于n型漂移层12的上表面之上。另外，第1p型扩散层14与FWD的p型阳极层13相邻。并且，第1p型扩散层14的p型的杂质浓度比p型阳极层13的该杂质浓度高，第1p型扩散层14比p型阳极层13的杂质深。此外，第1p型扩散层14与p型阳极层13之间的边界对应于耐压保持区域3与FWD区域1之间的边界，图10所示的沿上下延伸的虚线表示形成第1p型扩散层14时的注入区域的边界，换言之，表示掩模与开口区域的边界。
n型缓冲层15配置于FWD区域1、IGBT区域2以及耐压保持区域3的下表面，配置于n型漂移层12的下表面上。n型缓冲层15的n型杂质浓度比n型漂移层12的该杂质浓度高。
FWD的n型阴极层16配置于FWD区域1的下表面，配置于n型缓冲层15的下表面上。n型阴极层16的n型杂质浓度比n型缓冲层15的该杂质浓度高。
IGBT的p型集电极层配置于IGBT区域2的下表面，配置于n型缓冲层15的下表面上。另外，IGBT的p型集电极层与FWD的n型阴极层16相邻。
第2p型扩散层17配置于耐压保持区域3的下表面，配置于n型缓冲层15的下表面上。另外，第2p型扩散层17与FWD的n型阴极层16相邻。就相关半导体装置而言，第2p型扩散层17中的FWD区域1侧的端部凸出至FWD区域1。第2p型扩散层17的FWD区域1侧的端部与图10所示的沿上下延伸的虚线之间的长度PW设得比n型漂移层12中的位于第1p型扩散层14下侧的部分的厚度大。由此，能够抑制载流子从第1p型扩散层14经过n型漂移层12而到达至n型阴极层16。此外，该第2p型扩散层17构成FLR(Field Limiting Ring)构造、或者RESURF(REduced SURface Field)构造等，在这里，省略详细的结构的说明。
相关半导体装置不仅具有上述的半导体衬底11，还具有层间绝缘膜21、23、表面电极24、背面电极25以及由多晶硅构成的栅极电极层22。
层间绝缘膜21配置于半导体衬底11的端部。栅极电极层22配置于层间绝缘膜21之上，层间绝缘膜23将栅极电极层22覆盖。
表面电极24配置于FWD区域1、IGBT区域2以及耐压保持区域3的上表面之上，与图9的栅极焊盘51电连接。背面电极25配置于FWD区域1、IGBT区域2以及耐压保持区域3的下表面上。
如上构成的相关半导体装置作为RC-IGBT起作用。具体而言，在IGBT为接通状态的情况下，流动从p型集电极层朝向n型发射极层的电流(图10的从下朝上的电流)。在IGBT从接通状态变成断开状态的情况下，由于与RC-IGBT连接的未图示的电感性负载，向RC-IGBT施加反向电压。其结果，表面电极24侧成为高电位，FWD成为接通状态，流动从p型阳极层13朝向n型阴极层16的电流(图10的从上朝下的电流)、即方向与IGBT为接通状态的情况相反的电流。通过以上述方式释放反向电压，从而抑制由该反向电压引起的故障，并且在电感性负载中有效利用反向电压。
接下来，在IGBT从断开状态切换至接通状态，从而FWD从接通状态切换至断开状态时，由于至此为止所注入的p型阳极层13的空穴等载流子的原因，恢复电流以与FWD处于接通状态时流过的电流相反的方向持续流动一段时间。该恢复电流的朝向与在IGBT为接通状态的情况下应在RC-IGBT流过的电流相同，因此成为能量损失的原因。
特别是，就上述的相关半导体装置而言，浓度较高的第1p型扩散层14与p型阳极层13相邻。就上述结构而言，在IGBT从断开状态切换至接通状态，FWD从接通状态切换至断开状态时，从第1p型扩散层14向p型阳极层13注入空穴。其结果，应排出的空穴增加，因此与空穴的移动方向相反方向的电流、即图10的箭头Irr所示的恢复电流增大。与此相对，在耐压保持区域3的下表面设置有第2p型扩散层17、或使该第2p型扩散层17凸出至FWD区域1，从而能够降低恢复电流，但期望进一步降低恢复电流。在这里，如下面说明的那样，根据实施方式1～7涉及的半导体装置，能够降低恢复电流。
<实施方式1>
图1是表示本发明的实施方式1涉及的半导体装置的结构的剖视图。以下，对本实施方式1所说明的结构要素中与在相关半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图1所示，就本实施方式1涉及的半导体装置而言，与p型阳极层13和第1p型扩散层14之间的边界相比在p型阳极层13侧的半导体衬底11的上表面配置有第1沟槽31。即，第1沟槽31不与第1p型扩散层14接触，配置于p型阳极层13中的第1p型扩散层14侧的部分。此外，在本实施方式1中，第1沟槽31是与至少在FWD区域1以及IGBT区域2形成的未图示的栅极电极构造相同地形成的。因此，在第1沟槽31内隔着与栅极绝缘膜相同的绝缘膜，配置有与栅极电极层相同的电极层。
根据上述本实施方式1涉及的半导体装置，在FWD从接通状态切换至断开状态时，能够抑制从第1p型扩散层14向p型阳极层13注入空穴。其结果，能够降低从第1p型扩散层14经由p型阳极层13而向n型阴极层16流动的恢复电流。
此外，在本实施方式1中，半导体衬底11既可以由硅(Si)等半导体构成，也可以由碳化硅(SiC)、氮化镓(GaN)、金刚石等宽带隙半导体构成。这在实施方式2及其之后也是同样的。
<实施方式2>
图2是表示本发明的实施方式2涉及的半导体装置的结构的俯视图。以下，对本实施方式2所说明的结构要素中与在相关半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图2所示，就本实施方式2涉及的半导体装置而言，在p型阳极层13配置有与第1沟槽31交叉的第2沟槽32。此外，在第2沟槽32内，与第1沟槽31同样地，隔着与栅极绝缘膜相同的绝缘膜，配置有与栅极电极层相同的电极层。
根据上述本实施方式2涉及的半导体装置，原本在第1沟槽31的下侧集中的电场被分散至第2沟槽32的下侧。由此，能够抑制电场集中于沟槽，因此能够提高耐压性，且能够抑制沟槽的缺点。
<实施方式3>
图3是表示本发明的实施方式3涉及的半导体装置的结构的剖视图。以下，对本实施方式3所说明的结构要素中与在相关半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
就本实施方式3涉及的半导体装置而言，p型阳极层13的p型的杂质浓度随着接近第1p型扩散层14而变低。此外，对于作为p型阳极层13形成浓度具有梯度的杂质层的方法，既可以使用例如通常已知的VLD(Variation of Lateral Doping)，也可以使用除此以外的方法。
根据上述本实施方式3涉及的半导体装置，通过对p型阳极层13的浓度设置梯度，从而能够提高p型阳极层13与第1p型扩散层14之间的、图3的由假想线示出的电阻33。由此，能够降低从第1p型扩散层14经由p型阳极层13而向n型阴极层流动的恢复电流。
<实施方式4>
图4是表示本发明的实施方式4涉及的半导体装置的结构的剖视图。以下，对本实施方式4所说明的结构要素中与在相关半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图4所示，就本实施方式4涉及的半导体装置而言，表面电极24配置于耐压保持区域3的上方，不与第1p型扩散层14接触。在这里，层间绝缘膜23中的FWD区域1侧的端部凸出至FWD区域1，通过该凸出部分使表面电极24和第1p型扩散层14分离。此外，表面电极24配置于FWD区域1以及IGBT区域2之上，与p型阳极层13、p型基极层以及n型发射极层接触。
根据上述本实施方式4涉及的半导体装置，能够在FWD为接通状态时抑制在第1p型扩散层14处的载流子即空穴的产生。因此，能够在FWD从接通状态切换至断开状态时，抑制从第1p型扩散层14向p型阳极层13注入空穴，因此能够降低恢复电流。
<实施方式5>
图5是表示本发明的实施方式5涉及的半导体装置的结构的剖视图。以下，对本实施方式5所说明的结构要素中与在实施方式4涉及的半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图5所示，就本实施方式5涉及的半导体装置而言，p型阳极层13和第1p型扩散层14由n型漂移层12的一部分分离开，n型漂移层12的该一部分由于层间绝缘膜23的凸出部分而与表面电极24分离。
根据上述本实施方式5涉及的半导体装置，能够提高p型阳极层13与第1p型扩散层14之间的、图5的由假想线示出的电阻34。由此，能够降低从第1p型扩散层14经由p型阳极层13而向n型阴极层流动的恢复电流。
<实施方式6>
图6是表示本发明的实施方式6涉及的半导体装置的结构的剖视图。以下，对本实施方式6所说明的结构要素中与在实施方式4涉及的半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图6所示，本实施方式6涉及的半导体衬底11还具有呈n型的分离区域35，分离区域35夹在p型阳极层13与第1p型扩散层14之间而配置于半导体衬底11的上表面之上，分离区域35的上部通过层间绝缘膜23的凸出部分而与表面电极24分离。此外，在本实施方式6中，分离区域35的n型的杂质浓度高于n型漂移层12的该杂质浓度。
根据上述本实施方式6涉及的半导体装置，与形成分离区域35相对应地，与实施方式5相比制造工序增加，但能够将p型阳极层13与第1p型扩散层14之间的、图6的由假想线局部示出的电阻36的电阻值设为预想的值。由此，能够适当地降低恢复电流。
<实施方式7>
图7是表示本发明的实施方式7涉及的半导体装置的结构的俯视图，图8是表示该结构的剖视图。以下，对本实施方式7所说明的结构要素中与在相关半导体装置时说明的结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图7以及图8所示，就本实施方式7涉及的半导体装置而言，第1p型扩散层14包含多个选择注入层14a和配置有多个选择注入层14a的半导体层14b。如图7所示，多个四边形状的选择注入层14a沿耐压保持区域3的周向而以交错状的图案配置，如图8所示，选择注入层14a配置于半导体层14b的上部。但是，多个选择注入层14a的形状、位置以及范围并不限定于图7以及图8所示的内容。
在本实施方式7中，第1p型扩散层14是通过在应形成第1p型扩散层14的区域内选择性地注入杂质而形成的。由此，向多个选择注入层14a注入杂质，但并未向半导体层14b注入杂质。然而，通过热扩散等，多个选择注入层14a的杂质扩散至半导体层14b。因此，基本上，半导体层14b的杂质浓度低于选择注入层14a的杂质浓度。此外，在选择注入层14a以及半导体层14b沿从一侧朝向另一侧的方向的杂质浓度变化既可以是急剧的，也可以是缓慢的。就以上述方式构成的本实施方式7而言，第1p型扩散层14的杂质浓度变得不均匀。
根据上述本实施方式7涉及的半导体装置，能够使整个第1p型扩散层14的平均杂质浓度低于选择注入层14a的杂质浓度。由此，能够在FWD为接通状态时抑制在第1p型扩散层14处的空穴的产生，因此能够降低恢复电流。
此外，本发明能够在该发明的范围内对各实施方式及各变形例自由地进行组合，或者对各实施方式以及各变形例适当地进行变形、省略。

Claims (3)

1.一种半导体装置，其具有：
半导体衬底，其具有第1主面以及第2主面，该半导体衬底被规定出配置有续流二极管的第1区域、配置有IGBT即绝缘栅型双极晶体管的第2区域、和在俯视观察时将所述第1区域以及所述第2区域包围的耐压保持区域；
表面电极，其配置于所述第1区域以及所述第2区域的所述第1主面之上；以及
背面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第2主面之上，
所述半导体衬底具有：
阳极层，其配置于所述第1区域的所述第1主面，呈第1导电型；
扩散层，其与所述阳极层相邻地配置于所述耐压保持区域的所述第1主面，呈所述第1导电型；
阴极层，其配置于所述第1区域的所述第2主面，呈第2导电型；以及
绝缘层，
所述表面电极与所述阳极层接触而连接，所述表面电极延伸至所述扩散层的上方且通过所述绝缘层而与所述扩散层分离，所述扩散层的所述第1导电型的杂质浓度比所述阳极层的所述第1导电型的杂质浓度高。
2.一种半导体装置，其具有：
半导体衬底，其具有第1主面以及第2主面，该半导体衬底被规定出配置有续流二极管的第1区域、配置有IGBT即绝缘栅型双极晶体管的第2区域、和在俯视观察时将所述第1区域以及所述第2区域包围的耐压保持区域；
表面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第1主面之上；以及
背面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第2主面之上，
所述半导体衬底具有：
阳极层，其配置于所述第1区域的所述第1主面，呈第1导电型；
扩散层，其配置于所述耐压保持区域的所述第1主面，呈所述第1导电型；
分离区域，其夹在所述阳极层与所述扩散层之间而配置于所述第1主面，呈第2导电型，所述分离区域的所述第2导电型的杂质浓度比所述半导体衬底高；以及
阴极层，其配置于所述第1区域的所述第2主面，呈所述第2导电型，
所述扩散层的所述第1导电型的杂质浓度比所述阳极层的所述第1导电型的杂质浓度高。
3.一种半导体装置的制造方法，其中，
所述半导体装置具有：
半导体衬底，其具有第1主面以及第2主面，该半导体衬底被规定出配置有续流二极管的第1区域、配置有IGBT即绝缘栅型双极晶体管的第2区域、和在俯视观察时将所述第1区域以及所述第2区域包围的耐压保持区域；
表面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第1主面之上；以及
背面电极，其配置于所述第1区域、所述第2区域以及所述耐压保持区域的所述第2主面之上，
所述半导体衬底具有：
阳极层，其配置于所述第1区域的所述第1主面，呈第1导电型；
扩散层，其与所述阳极层相邻地配置于所述耐压保持区域的所述第1主面，呈所述第1导电型；以及
阴极层，其配置于所述第1区域的所述第2主面，呈第2导电型，
一个所述扩散层是通过在应形成该扩散层的区域内向交错状地配置的多个区域注入杂质进行热扩散而形成的。
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