US20180308838A1 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

Info

Publication number
US20180308838A1
US20180308838A1 US15/851,447 US201715851447A US2018308838A1 US 20180308838 A1 US20180308838 A1 US 20180308838A1 US 201715851447 A US201715851447 A US 201715851447A US 2018308838 A1 US2018308838 A1 US 2018308838A1
Authority
US
United States
Prior art keywords
region
layer
main surface
type
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/851,447
Inventor
Hiroyuki Nakamura
Shinya SONEDA
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKAMURA, HIROYUKI, Soneda, Shinya
Publication of US20180308838A1 publication Critical patent/US20180308838A1/en
Priority to US16/875,457 priority Critical patent/US11610882B2/en
Priority to US18/062,475 priority patent/US20230106654A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to a semiconductor device such as a power semiconductor device and a method of manufacturing the semiconductor device.
  • a power device as a power semiconductor device is used in a wide range of fields such as the fields of home electronic appliances, electric vehicles, and railroads and the fields of solar photovoltaic power generation and wind power generation that have been attracting more attention as power generation of renewable energy.
  • an inductive load of an induction motor or the like is driven by an inverter circuit constructed by a power device in many cases.
  • a freewheeling diode hereinafter referred to as an “FWD” for circulating a current generated due to a counter-electromotive force of an inductive toad is provided.
  • a typical inverter circuit is formed of a plurality of insulated gate bipolar transistors (hereinafter referred to as “IGBTs”) and a plurality of FWDs.
  • the inverter circuit is largely desired to be reduced in size, weight, and cost, and thus it is not desirable to mount a plurality of IGBTs and a plurality of FWDs on the inverter circuit individually.
  • an IGBT of a reverse conducting type hereinafter referred to as an “RC-IGBT” that integrates the IGBT and the FWD has been developed, and the configuration with the above applied thereto enables reduction of the mounting area of the semiconductor device and reduction in cost.
  • a p-type collector layer as an IGBT and an n-type cathode layer as an FWD are arranged in a surface only having arranged therein a p-type collector layer of a typical IGBT that does not have reverse conducting property. Further, in a surface opposite to such a surface of the RC-IGBT, a p-type base layer as the IGBT, a p-type anode layer as the FWD, and a p-type diffusion layer of a withstand-voltage retention region surrounding those layers in plan view are arranged.
  • the RC-IGBT is disclosed in, for example, Takahashi H, et al, “1200V Reverse Conducting IGBT”, Proceedings of ISPSD, 2004, p. 133-136, Japanese Patent Application Laid-Open No. 2008-53648, Japanese Patent Application Laid-Open No. 2008-103590, and Japanese Patent Application Laid-Open No. 2008-109028.
  • the present invention is made in view of the problems as described above, and has an object to provide a technology capable of reducing a recovery current.
  • the present invention provides a semiconductor device including a semiconductor substrate, a surface electrode, and a back-surface electrode.
  • the semiconductor substrate has a first main surface and a second main surface, and a first region having a freewheeling diode arranged therein, second regions having an insulated gate bipolar transistor (IGBT) arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined in the semiconductor substrate.
  • the surface electrode is arranged on the first main surface of the first region, of the second regions, and of the withstand-voltage retention region.
  • the back-surface electrode is arranged on the second main surface of the first region, of the second regions, and of the withstand-voltage retention region.
  • the semiconductor substrate includes an anode layer having a first conductivity type, a diffusion layer having the first conductivity type, and a cathode layer having a second conductivity type.
  • the anode layer is arranged in the first main surface of the first region.
  • the diffusion layer is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer.
  • the cathode layer is arranged in the second main surface of the first region.
  • a first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.
  • the first trench is arranged in the first main surface on the side of the anode layer with respect to the boundary between the anode layer and the diffusion layer. With this, it is possible to reduce the recovery current.
  • FIG. 1 is a sectional view for illustrating configuration of a semiconductor device according to a first preferred embodiment of the present invention.
  • FIG. 2 is a plan view for illustrating configuration of the semiconductor device according to a second preferred embodiment of the present invention.
  • FIG. 3 is a sectional view for illustrating configuration of the semiconductor device according to a third preferred embodiment of the present invention.
  • FIG. 4 is a sectional view for illustrating configuration of the semiconductor device according to a fourth preferred embodiment of the present invention.
  • FIG. 5 is a sectional view for illustrating configuration of the semiconductor device according to a fifth preferred embodiment of the present invention.
  • FIG. 6 is a sectional view for illustrating configuration of the semiconductor device according to a sixth preferred embodiment of the present invention.
  • FIG. 7 is a plan view for illustrating configuration of the semiconductor device according to a seventh preferred embodiment of the present invention.
  • FIG. 8 is a sectional view for illustrating the configuration of the semiconductor device according to the seventh preferred embodiment.
  • FIG. 9 is a plan view for illustrating configuration of a related semiconductor device.
  • FIG. 10 is a sectional view for illustrating the configuration of the related semiconductor device.
  • a power semiconductor device related thereto (hereinafter referred to as a “related semiconductor device”) is described.
  • FIG. 9 is a plan view for illustrating configuration of a related semiconductor device
  • FIG. 10 is a sectional view for illustrating the configuration taken along the line A 1 -A 2 of FIG. 9 .
  • the related semiconductor device includes a semiconductor substrate 11 in which an FWD region 1 being a first region having an FWD arranged therein, IGBT regions 2 each being a second region having an IGBT arranged therein, and a withstand-voltage retention region 3 are defined.
  • the two IGBT regions 2 interpose the FWD region 1 therebetween in plan view, and the withstand-voltage retention region 3 surrounds the FWD region 1 and the two IGBT regions 2 in plan view.
  • the related semiconductor device includes a gate pad 51 arranged in the IGBT region 2 .
  • a first conductivity type is an n-type and a second conductivity type is a p-type. Further, description is hereinafter given assuming that a first main surface of the semiconductor substrate 11 is an upper surface of the semiconductor substrate 11 of FIG. 10 , which encompasses each upper surface of the FWD region 1 , the IGBT regions 2 , and the withstand-voltage retention region 3 , and that a second main surface of the semiconductor substrate 11 is a lower surface of the semiconductor substrate 11 of FIG. 10 , which encompasses each lower surface of the FWD region 1 , the IGBT regions 2 , and the withstand-voltage retention region 3 .
  • the semiconductor substrate 11 of the related semiconductor device includes an n-type drift layer 12 , a p-type anode layer 13 , a first p-type diffusion layer 14 being a diffusion layer, an n-type buffer layer 15 , an n-type cathode layer 16 , and a second p-type diffusion layer 17 .
  • the semiconductor substrate 11 includes components of an IGBT such as an n-type emitter layer, a p-type base layer, and a p-type collector layer, for example.
  • the n-type drift layer 12 has relatively low n-type impurity concentration, and is arranged across the FWD region 1 , the IGBT regions 2 , and the withstand-voltage retention region 3 .
  • the p-type anode layer 13 of the FWD is arranged in the upper surface of the FWD region 1 , and is arranged on an upper surface of the n-type drift layer 12 .
  • the n-type emitter layer and the p-type base layer of the IGBT are arranged in the upper surface of the IGBT region 2 , and are arranged on the upper surface of the n-type drift layer 12 .
  • Those n-type emitter layer and p-type base layer form a metal oxide semiconductor field effect transistor (MOSFET) being a part of the IGBT.
  • MOSFET metal oxide semiconductor field effect transistor
  • the p-type base layer of the IGBT is arranged adjacently to the p-type anode layer 13 of the FWD.
  • the first p-type diffusion layer 14 is arranged in the upper surface of the withstand-voltage retention region 3 , and is arranged on the upper surface of the n-type drift layer 12 . Further, the first p-type diffusion layer 14 is arranged adjacently to the p-type anode layer 13 of the FWD. Further, p-type impurity concentration of the first p-type diffusion layer 14 is higher than the impurity concentration of the p-type anode layer 13 , and the first p-type diffusion layer 14 is deeper than the impurity of the p-type anode layer 13 .
  • a boundary between the first p-type diffusion layer 14 and the p-type anode layer 13 corresponds to a boundary between the withstand-voltage retention region 3 and the FWD region 1
  • the vertically extending dotted line illustrated in FIG. 10 indicates a boundary of an injection region at the time of forming the first p-type diffusion layer 14 , that is, a boundary between a mask and an opening region.
  • the n-type buffer layer 15 is arranged in the lower surfaces of the FWD region 1 , the IGBT regions 2 , and the withstand-voltage retention region 3 , and is arranged on a lower surface of the n-type drift layer 12 .
  • N-type impurity concentration of the n-type buffer layer 15 is higher than the impurity concentration of the n-type drift layer 12 .
  • the n-type cathode layer 16 of the FWD is arranged in the lower surface of the FWD region 1 , and is arranged on a lower surface of the n-type buffer layer 15 .
  • N-type impurity concentration of the n-type cathode layer 16 is higher than the impurity concentration of the n-type buffer layer 15 .
  • the p-type collector layer of the IGBT is arranged in the lower surface of the IGBT region 2 , and is arranged on the lower surface of the n-type buffer layer 15 . Further, the p-type collector layer of the IGBT is arranged adjacently to the n-type cathode layer 16 of the FWD.
  • the second p-type diffusion layer 17 is arranged in the lower surface of the withstand-voltage retention region 3 , and is arranged on the lower surface of the n-type buffer layer 15 . Further, the second p-type diffusion layer 17 is arranged adjacently to the n-type cathode layer 16 of the FWD. In the related semiconductor device, an end portion of the second p-type diffusion layer 17 on the FWD region 1 side protrudes to the FWD region 1 .
  • a length PW between the end portion of the second p-type diffusion layer 17 on the FWD region 1 side and the vertically extending dotted line illustrated in FIG. 10 is set to be larger than a thickness of a portion of the n-type drift layer 12 below the first p-type diffusion layer 14 .
  • the second p-type diffusion layer 17 forms a field limiting ring (FLR) structure, a reduced surface field (RESURF) structure, or the like. However, description of the detailed configuration thereof is herein omitted.
  • FLR field limiting ring
  • RESURF reduced surface field
  • the related semiconductor device includes, in addition to the above-mentioned semiconductor substrate 11 , interlayer insulation films 21 and 23 , a gate electrode layer 22 formed of polysilicon, a surface electrode 24 , and a back-surface electrode 25 .
  • the interlayer insulation film 21 is arranged in an end portion of the semiconductor substrate 11 .
  • the gate electrode layer 22 is arranged on the interlayer insulation film 21 , and the interlayer insulation film 23 covers the gate electrode layer 22 .
  • the surface electrode 24 is arranged on the upper surfaces of the FWD region 1 , of the IGBT regions 2 , and of the withstand-voltage retention region 3 , and is electrically coupled to the gate pad 51 of FIG. 9 .
  • the back-surface electrode 25 is arranged on the lower surfaces of the FWD region 1 , of the IGBT regions 2 , and of the withstand-voltage retention region 3 .
  • the related semiconductor device configured as described above functions as an RC-IGBT. Specifically, in a case where the IGBT is in an on state, a current flows from the p-type collector layer toward the n-type emitter layer (current from the lower side toward the upper side in FIG. 10 ). In a case where the IGBT is turned into an off state from the on state, a reverse voltage is applied to the RC-IGBT due to an inductive load (not shown) coupled to the RC-IGBT. As a result, the surface electrode 24 side has a high potential to turn the FWD into the on state, causing a current to flow from the p-type anode layer 13 toward the n-type cathode layer 16 (current from the upper side toward the lower side in FIG.
  • a recovery current adversely continues to flow awhile in a reverse direction to the current having flowed when the FWD is in the on state, due to carriers such as holes of the p-type anode layer 13 that have been injected.
  • the recovery current is in the same direction as the current that is supposed to flow in the RC-IGBT in a case where the IGBT is in the on state, thus being a cause of energy loss.
  • the first p-type diffusion layer 14 having comparatively high concentration is arranged adjacently to the p-type anode layer 13 .
  • the IGBT is switched to the on state from the off state and the FWD is switched to the off state from the on state
  • holes are injected into the p-type anode layer 13 from the first p-type diffusion layer 14 .
  • holes that are supposed to be discharged increase, and thus a current in a reverse direction to a moving direction of the holes, that is, a recovery current indicated by an arrow Irr of FIG. 10 adversely increases.
  • FIG. 1 is a sectional view for illustrating configuration of a semiconductor device according to a first preferred embodiment of the present invention.
  • components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • a first trench 31 is arranged in the upper surface of the semiconductor substrate 11 on a side of the p-type anode layer 13 with respect to the boundary between the p-type anode layer 13 and the first p-type diffusion layer 14 . That is, the first trench 31 is not brought into contact with the first p-type diffusion layer 14 , and is arranged in a portion of the p-type anode layer 13 on the first p-type diffusion layer 14 side.
  • the first trench 31 is formed similarly to a gate electrode structure (not shown) formed at least in the FWD region 1 and the IGBT regions 2 . For this reason, inside the first trench 31 , an electrode layer that is the same as the gate electrode layer is arranged with intermediation of an insulation film that is the same as the gate insulation film.
  • the semiconductor device of this first preferred embodiment when the FWD is switched to the off state from the on state, it is possible to prevent holes from being injected into the p-type anode layer 13 from the first p-type diffusion layer 14 . As a result, it is possible to reduce the recovery current flowing from the first p-type diffusion layer 14 through intermediation of the p-type anode layer 13 to the n-type cathode layer 16 .
  • the semiconductor substrate 11 may be formed of a semiconductor such as silicon (Si), or may be formed of a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), and diamond. This is similarly applicable also in a second preferred embodiment and the following preferred embodiments of the present invention.
  • FIG. 2 is a plan view for illustrating configuration of the semiconductor device according to a second preferred embodiment of the present invention.
  • components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • a second trench 32 crossing with the first trench 31 is arranged in the p-type anode layer 13 .
  • an electrode layer that is the same as the gate electrode layer is arranged with intermediation of an insulation film that is the same as the gate insulation film.
  • an electric field concentrated on a lower side of the first trench 31 is dispersed on a lower side of the second trench 32 .
  • FIG. 3 is a sectional view for illustrating configuration of the semiconductor device according to a third preferred embodiment of the present invention.
  • components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • p-type impurity concentration of the p-type anode layer 13 decreases as approaching to the first p-type diffusion layer 14 .
  • a commonly known method of variation of lateral doping (VLD) may be used, for example, or other methods may be used as well.
  • the p-type anode layer 13 has concentration gradients, thereby being possible to raise resistance 33 between the p-type anode layer 13 and the first p-type diffusion layer 14 as indicated by the imaginary line of FIG. 3 . With this, it is possible to reduce the recovery current flowing from the first p-type diffusion layer 14 through intermediation of the p-type anode layer 13 to the n-type cathode layer.
  • FIG. 4 is a sectional view for illustrating configuration of the semiconductor device according to a fourth preferred embodiment of the present invention.
  • components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • the surface electrode 24 is arranged on an upper side of the withstand-voltage retention region 3 , and is out of contact with the first p-type diffusion layer 14 .
  • an end portion of the interlayer insulation film 23 on the FWD region 1 side protrudes to the FWD region 1 , and the surface electrode 24 and the first p-type diffusion layer 14 are separated apart by the protruding portion.
  • the surface electrode 24 is arranged on the FWD region 1 and the IGBT regions 2 , and is brought into contact with the p-type anode layer 13 , the p-type base layer, and the n-type emitter layer.
  • the semiconductor device of this fourth preferred embodiment it is possible to prevent generation of holes being carriers in the first p-type diffusion layer 14 when the FWD is in the on state. For this reason, when the FWD is switched to the off state from the on state, it is possible to prevent the holes from being injected into the p-type anode layer 13 from the first p-type diffusion layer 14 , thereby being possible to reduce the recovery current.
  • FIG. 5 is a sectional view for illustrating configuration of the semiconductor device according to a fifth preferred embodiment of the present invention.
  • components that are the same or similar to the components already described in the semiconductor device according to the fourth preferred embodiment are denoted by the same reference symbols, and different components are mainly described.
  • the p-type anode layer 13 and the first p-type diffusion layer 14 are separated apart by a portion of the n-type drift layer 12 , and the portion of the n-type drift layer 12 is separated apart from the surface electrode 24 by the protruding portion of the interlayer insulation film 23 .
  • the semiconductor device of this fifth preferred embodiment it is possible to raise resistance 34 between the p-type anode layer 13 and the first p-type diffusion layer 14 as indicated by the imaginary line of FIG. 5 . With this, it is possible to reduce the recovery current flowing from the first p-type diffusion layer 14 through intermediation of the p-type anode layer 13 to the n-type cathode layer.
  • FIG. 6 is a sectional view for illustrating configuration of the semiconductor device according to a sixth preferred embodiment of the present invention.
  • components that are the same or similar to the components already described in the semiconductor device according to the fourth preferred embodiment are denoted by the same reference symbols, and different components are mainly described.
  • the semiconductor substrate 11 further includes a separating region 35 having an n-type.
  • the separating region 35 is interposed between the p-type anode layer 13 and the first p-type diffusion layer 14 , and is arranged on the upper surface of the semiconductor substrate 11 .
  • An upper portion of the separating region 35 is separated apart from the surface electrode 24 by the protruding portion of the interlayer insulation film 23 .
  • n-type impurity concentration of the separating region 35 is higher than the impurity concentration of the n-type drift layer 12 .
  • FIG. 7 is a plan view for illustrating configuration of the semiconductor device according to a seventh preferred embodiment of the present invention
  • FIG. 8 is a sectional view for illustrating the configuration.
  • the first p-type diffusion layer 14 includes a plurality of selective injection layers 14 a and a semiconductor layer 14 b having the plurality of selective injection layers 14 a arranged therein.
  • the plurality of selective injection layers 14 a of a quadrangular shape are arranged in a zigzag pattern along a circumferential direction of the withstand-voltage retention region 3 , and as illustrated in FIG. 8 , the selective injection layers 14 a are arranged on an upper portion of the semiconductor layer 14 b .
  • shapes, positions, and ranges of the plurality of selective injection layers 14 a are not limited to those illustrated in FIG. 7 and FIG. 8 .
  • the first p-type diffusion layer 14 is formed in such a manner that impurity is selectively injected within a region in which the first p-type diffusion layer 14 is to be formed. With this, impurity is injected into the plurality of selective injection layers 14 a , but impurity is not injected into the semiconductor layer 14 b . However, the impurity of the plurality of selective injection layers 14 a is diffused to the semiconductor layer 14 b due to thermal diffusion or the like. For this reason, generally, the impurity concentration of the semiconductor layer 14 b is lower than the impurity concentration of the selective injection layers 14 a .
  • change in impurity concentration along a direction from one of the selective injection layers 14 a and the semiconductor layer 14 b to another may be steep or may be gentle.
  • the first p-type diffusion layer 14 has uneven impurity concentration.
  • the semiconductor device of this seventh preferred embodiment it is possible to have mean impurity concentration in the entire first p-type diffusion layer 14 lower than the impurity concentration of the selective injection layers 14 a . With this, it is possible to prevent the generation of the holes in the first p-type diffusion layer 14 when the FWD is in the on state, thereby being possible to reduce the recovery current.
  • each of the preferred embodiments and each of the modified examples may be freely combined, and each of the preferred embodiments and each of the modified examples may be appropriately modified or omitted within the scope of the invention.

Abstract

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device such as a power semiconductor device and a method of manufacturing the semiconductor device.
    • DESCRIPTION OF THE BACKGROUND ART
  • A power device as a power semiconductor device is used in a wide range of fields such as the fields of home electronic appliances, electric vehicles, and railroads and the fields of solar photovoltaic power generation and wind power generation that have been attracting more attention as power generation of renewable energy. In those fields, an inductive load of an induction motor or the like is driven by an inverter circuit constructed by a power device in many cases. In a configuration of driving an inductive load, a freewheeling diode (hereinafter referred to as an “FWD”) for circulating a current generated due to a counter-electromotive force of an inductive toad is provided. Note that, a typical inverter circuit is formed of a plurality of insulated gate bipolar transistors (hereinafter referred to as “IGBTs”) and a plurality of FWDs.
  • However, the inverter circuit is largely desired to be reduced in size, weight, and cost, and thus it is not desirable to mount a plurality of IGBTs and a plurality of FWDs on the inverter circuit individually. As one countermeasure thereof, an IGBT of a reverse conducting type (hereinafter referred to as an “RC-IGBT”) that integrates the IGBT and the FWD has been developed, and the configuration with the above applied thereto enables reduction of the mounting area of the semiconductor device and reduction in cost.
  • In the RC-IGBT, a p-type collector layer as an IGBT and an n-type cathode layer as an FWD are arranged in a surface only having arranged therein a p-type collector layer of a typical IGBT that does not have reverse conducting property. Further, in a surface opposite to such a surface of the RC-IGBT, a p-type base layer as the IGBT, a p-type anode layer as the FWD, and a p-type diffusion layer of a withstand-voltage retention region surrounding those layers in plan view are arranged. Note that, the RC-IGBT is disclosed in, for example, Takahashi H, et al, “1200V Reverse Conducting IGBT”, Proceedings of ISPSD, 2004, p. 133-136, Japanese Patent Application Laid-Open No. 2008-53648, Japanese Patent Application Laid-Open No. 2008-103590, and Japanese Patent Application Laid-Open No. 2008-109028.
  • However, in the RC-IGBT, a recovery current being an opposite current to a current usually supposed to flow as a diode (forward current) flows when the FWD is turned into an off state from an on state, and there has been a problem in that the recovery current becomes a cause of energy loss.
    • SUMMARY
  • The present invention is made in view of the problems as described above, and has an object to provide a technology capable of reducing a recovery current.
  • The present invention provides a semiconductor device including a semiconductor substrate, a surface electrode, and a back-surface electrode. The semiconductor substrate has a first main surface and a second main surface, and a first region having a freewheeling diode arranged therein, second regions having an insulated gate bipolar transistor (IGBT) arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined in the semiconductor substrate. The surface electrode is arranged on the first main surface of the first region, of the second regions, and of the withstand-voltage retention region. The back-surface electrode is arranged on the second main surface of the first region, of the second regions, and of the withstand-voltage retention region. The semiconductor substrate includes an anode layer having a first conductivity type, a diffusion layer having the first conductivity type, and a cathode layer having a second conductivity type. The anode layer is arranged in the first main surface of the first region. The diffusion layer is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. The cathode layer is arranged in the second main surface of the first region. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.
  • According to the present invention, the first trench is arranged in the first main surface on the side of the anode layer with respect to the boundary between the anode layer and the diffusion layer. With this, it is possible to reduce the recovery current.
  • These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a sectional view for illustrating configuration of a semiconductor device according to a first preferred embodiment of the present invention.
  • FIG. 2 is a plan view for illustrating configuration of the semiconductor device according to a second preferred embodiment of the present invention.
  • FIG. 3 is a sectional view for illustrating configuration of the semiconductor device according to a third preferred embodiment of the present invention.
  • FIG. 4 is a sectional view for illustrating configuration of the semiconductor device according to a fourth preferred embodiment of the present invention.
  • FIG. 5 is a sectional view for illustrating configuration of the semiconductor device according to a fifth preferred embodiment of the present invention.
  • FIG. 6 is a sectional view for illustrating configuration of the semiconductor device according to a sixth preferred embodiment of the present invention.
  • FIG. 7 is a plan view for illustrating configuration of the semiconductor device according to a seventh preferred embodiment of the present invention.
  • FIG. 8 is a sectional view for illustrating the configuration of the semiconductor device according to the seventh preferred embodiment.
  • FIG. 9 is a plan view for illustrating configuration of a related semiconductor device.
  • FIG. 10 is a sectional view for illustrating the configuration of the related semiconductor device.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • <Related Semiconductor Device>
  • First, prior to giving description of a semiconductor device according to preferred embodiments of the present invention, a power semiconductor device related thereto (hereinafter referred to as a “related semiconductor device”) is described.
  • FIG. 9 is a plan view for illustrating configuration of a related semiconductor device, and FIG. 10 is a sectional view for illustrating the configuration taken along the line A1-A2 of FIG. 9.
  • As illustrated in FIG. 9, the related semiconductor device includes a semiconductor substrate 11 in which an FWD region 1 being a first region having an FWD arranged therein, IGBT regions 2 each being a second region having an IGBT arranged therein, and a withstand-voltage retention region 3 are defined. The two IGBT regions 2 interpose the FWD region 1 therebetween in plan view, and the withstand-voltage retention region 3 surrounds the FWD region 1 and the two IGBT regions 2 in plan view. Further, the related semiconductor device includes a gate pad 51 arranged in the IGBT region 2.
  • Description is hereinafter given assuming that a first conductivity type is an n-type and a second conductivity type is a p-type. Further, description is hereinafter given assuming that a first main surface of the semiconductor substrate 11 is an upper surface of the semiconductor substrate 11 of FIG. 10, which encompasses each upper surface of the FWD region 1, the IGBT regions 2, and the withstand-voltage retention region 3, and that a second main surface of the semiconductor substrate 11 is a lower surface of the semiconductor substrate 11 of FIG. 10, which encompasses each lower surface of the FWD region 1, the IGBT regions 2, and the withstand-voltage retention region 3.
  • As illustrated in FIG. 10, the semiconductor substrate 11 of the related semiconductor device includes an n-type drift layer 12, a p-type anode layer 13, a first p-type diffusion layer 14 being a diffusion layer, an n-type buffer layer 15, an n-type cathode layer 16, and a second p-type diffusion layer 17. Further, although not shown, the semiconductor substrate 11 includes components of an IGBT such as an n-type emitter layer, a p-type base layer, and a p-type collector layer, for example.
  • The n-type drift layer 12 has relatively low n-type impurity concentration, and is arranged across the FWD region 1, the IGBT regions 2, and the withstand-voltage retention region 3.
  • The p-type anode layer 13 of the FWD is arranged in the upper surface of the FWD region 1, and is arranged on an upper surface of the n-type drift layer 12.
  • The n-type emitter layer and the p-type base layer of the IGBT (not shown) are arranged in the upper surface of the IGBT region 2, and are arranged on the upper surface of the n-type drift layer 12. Those n-type emitter layer and p-type base layer form a metal oxide semiconductor field effect transistor (MOSFET) being a part of the IGBT. Further, the p-type base layer of the IGBT is arranged adjacently to the p-type anode layer 13 of the FWD.
  • The first p-type diffusion layer 14 is arranged in the upper surface of the withstand-voltage retention region 3, and is arranged on the upper surface of the n-type drift layer 12. Further, the first p-type diffusion layer 14 is arranged adjacently to the p-type anode layer 13 of the FWD. Further, p-type impurity concentration of the first p-type diffusion layer 14 is higher than the impurity concentration of the p-type anode layer 13, and the first p-type diffusion layer 14 is deeper than the impurity of the p-type anode layer 13. Note that, a boundary between the first p-type diffusion layer 14 and the p-type anode layer 13 corresponds to a boundary between the withstand-voltage retention region 3 and the FWD region 1, and the vertically extending dotted line illustrated in FIG. 10 indicates a boundary of an injection region at the time of forming the first p-type diffusion layer 14, that is, a boundary between a mask and an opening region.
  • The n-type buffer layer 15 is arranged in the lower surfaces of the FWD region 1, the IGBT regions 2, and the withstand-voltage retention region 3, and is arranged on a lower surface of the n-type drift layer 12. N-type impurity concentration of the n-type buffer layer 15 is higher than the impurity concentration of the n-type drift layer 12.
  • The n-type cathode layer 16 of the FWD is arranged in the lower surface of the FWD region 1, and is arranged on a lower surface of the n-type buffer layer 15. N-type impurity concentration of the n-type cathode layer 16 is higher than the impurity concentration of the n-type buffer layer 15.
  • The p-type collector layer of the IGBT is arranged in the lower surface of the IGBT region 2, and is arranged on the lower surface of the n-type buffer layer 15. Further, the p-type collector layer of the IGBT is arranged adjacently to the n-type cathode layer 16 of the FWD.
  • The second p-type diffusion layer 17 is arranged in the lower surface of the withstand-voltage retention region 3, and is arranged on the lower surface of the n-type buffer layer 15. Further, the second p-type diffusion layer 17 is arranged adjacently to the n-type cathode layer 16 of the FWD. In the related semiconductor device, an end portion of the second p-type diffusion layer 17 on the FWD region 1 side protrudes to the FWD region 1. A length PW between the end portion of the second p-type diffusion layer 17 on the FWD region 1 side and the vertically extending dotted line illustrated in FIG. 10 is set to be larger than a thickness of a portion of the n-type drift layer 12 below the first p-type diffusion layer 14. With this, it is possible to prevent carriers from reaching the n-type cathode layer 16 from the first p-type diffusion layer 14 passing through the n-type drift layer 12. Note that, the second p-type diffusion layer 17 forms a field limiting ring (FLR) structure, a reduced surface field (RESURF) structure, or the like. However, description of the detailed configuration thereof is herein omitted.
  • The related semiconductor device includes, in addition to the above-mentioned semiconductor substrate 11, interlayer insulation films 21 and 23, a gate electrode layer 22 formed of polysilicon, a surface electrode 24, and a back-surface electrode 25.
  • The interlayer insulation film 21 is arranged in an end portion of the semiconductor substrate 11. The gate electrode layer 22 is arranged on the interlayer insulation film 21, and the interlayer insulation film 23 covers the gate electrode layer 22.
  • The surface electrode 24 is arranged on the upper surfaces of the FWD region 1, of the IGBT regions 2, and of the withstand-voltage retention region 3, and is electrically coupled to the gate pad 51 of FIG. 9. The back-surface electrode 25 is arranged on the lower surfaces of the FWD region 1, of the IGBT regions 2, and of the withstand-voltage retention region 3.
  • The related semiconductor device configured as described above functions as an RC-IGBT. Specifically, in a case where the IGBT is in an on state, a current flows from the p-type collector layer toward the n-type emitter layer (current from the lower side toward the upper side in FIG. 10). In a case where the IGBT is turned into an off state from the on state, a reverse voltage is applied to the RC-IGBT due to an inductive load (not shown) coupled to the RC-IGBT. As a result, the surface electrode 24 side has a high potential to turn the FWD into the on state, causing a current to flow from the p-type anode layer 13 toward the n-type cathode layer 16 (current from the upper side toward the lower side in FIG. 10), that is, causing a current to flow in a reverse direction to the case where the IGBT is in the on state. The reverse voltage is released in such a manner, thereby preventing a failure caused by the reverse voltage and effectively utilizing the reverse voltage in the inductive load.
  • Next, when the FWD is switched to the off state from the on state, which is caused by the IGBT being switched to the on state from the off state, a recovery current adversely continues to flow awhile in a reverse direction to the current having flowed when the FWD is in the on state, due to carriers such as holes of the p-type anode layer 13 that have been injected. The recovery current is in the same direction as the current that is supposed to flow in the RC-IGBT in a case where the IGBT is in the on state, thus being a cause of energy loss.
  • Particularly, in the above-mentioned related semiconductor device, the first p-type diffusion layer 14 having comparatively high concentration is arranged adjacently to the p-type anode layer 13. With such a configuration, when the IGBT is switched to the on state from the off state and the FWD is switched to the off state from the on state, holes are injected into the p-type anode layer 13 from the first p-type diffusion layer 14. As a result, holes that are supposed to be discharged increase, and thus a current in a reverse direction to a moving direction of the holes, that is, a recovery current indicated by an arrow Irr of FIG. 10 adversely increases. As a countermeasure thereof, it is possible to reduce the recovery current by providing the second p-type diffusion layer 17 in the lower surface of the withstand-voltage retention region 3, or making the second p-type diffusion layer 17 to protrude to the FWD region 1. However, further reduction of the recovery current is desired. In view of the above, as in the description below, with a semiconductor device according to first to seventh preferred embodiments of the present invention, it is possible to reduce the recovery current.
    • First Preferred Embodiment
  • FIG. 1 is a sectional view for illustrating configuration of a semiconductor device according to a first preferred embodiment of the present invention. In the following, out of components to be described in this first preferred embodiment, components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • As illustrated in FIG. 1, in a semiconductor device according to this first preferred embodiment, a first trench 31 is arranged in the upper surface of the semiconductor substrate 11 on a side of the p-type anode layer 13 with respect to the boundary between the p-type anode layer 13 and the first p-type diffusion layer 14. That is, the first trench 31 is not brought into contact with the first p-type diffusion layer 14, and is arranged in a portion of the p-type anode layer 13 on the first p-type diffusion layer 14 side. Note that, in this first preferred embodiment, the first trench 31 is formed similarly to a gate electrode structure (not shown) formed at least in the FWD region 1 and the IGBT regions 2. For this reason, inside the first trench 31, an electrode layer that is the same as the gate electrode layer is arranged with intermediation of an insulation film that is the same as the gate insulation film.
  • According to the semiconductor device of this first preferred embodiment as described above, when the FWD is switched to the off state from the on state, it is possible to prevent holes from being injected into the p-type anode layer 13 from the first p-type diffusion layer 14. As a result, it is possible to reduce the recovery current flowing from the first p-type diffusion layer 14 through intermediation of the p-type anode layer 13 to the n-type cathode layer 16.
  • Note that, in this first preferred embodiment, the semiconductor substrate 11 may be formed of a semiconductor such as silicon (Si), or may be formed of a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), and diamond. This is similarly applicable also in a second preferred embodiment and the following preferred embodiments of the present invention.
    • Second Preferred Embodiment
  • FIG. 2 is a plan view for illustrating configuration of the semiconductor device according to a second preferred embodiment of the present invention. In the following, out of components to be described in this second preferred embodiment, components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • As illustrated in FIG. 2, in the semiconductor device according to this second preferred embodiment, a second trench 32 crossing with the first trench 31 is arranged in the p-type anode layer 13. Note that, inside the second trench 32, similarly to the first trench 31, an electrode layer that is the same as the gate electrode layer is arranged with intermediation of an insulation film that is the same as the gate insulation film.
  • According to the semiconductor device of this second preferred embodiment as described above, an electric field concentrated on a lower side of the first trench 31 is dispersed on a lower side of the second trench 32. With this, it is possible to prevent an electric field from being concentrated in the trench, thereby being possible to enhance property of withstanding voltage and prevent deficiency of the trench.
    • Third Preferred Embodiment
  • FIG. 3 is a sectional view for illustrating configuration of the semiconductor device according to a third preferred embodiment of the present invention. In the following, out of components to be described in this third preferred embodiment, components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • In the semiconductor device according to this third preferred embodiment, p-type impurity concentration of the p-type anode layer 13 decreases as approaching to the first p-type diffusion layer 14. Note that, as a method of forming an impurity layer having concentration gradients to be the p-type anode layer 13, a commonly known method of variation of lateral doping (VLD) may be used, for example, or other methods may be used as well.
  • According to the semiconductor device of this third preferred embodiment as described above, the p-type anode layer 13 has concentration gradients, thereby being possible to raise resistance 33 between the p-type anode layer 13 and the first p-type diffusion layer 14 as indicated by the imaginary line of FIG. 3. With this, it is possible to reduce the recovery current flowing from the first p-type diffusion layer 14 through intermediation of the p-type anode layer 13 to the n-type cathode layer.
    • Fourth Preferred Embodiment
  • FIG. 4 is a sectional view for illustrating configuration of the semiconductor device according to a fourth preferred embodiment of the present invention. In the following, out of components to be described in this fourth preferred embodiment, components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • As illustrated in FIG. 4, in the semiconductor device according to this fourth preferred embodiment, the surface electrode 24 is arranged on an upper side of the withstand-voltage retention region 3, and is out of contact with the first p-type diffusion layer 14. Here, an end portion of the interlayer insulation film 23 on the FWD region 1 side protrudes to the FWD region 1, and the surface electrode 24 and the first p-type diffusion layer 14 are separated apart by the protruding portion. Note that, the surface electrode 24 is arranged on the FWD region 1 and the IGBT regions 2, and is brought into contact with the p-type anode layer 13, the p-type base layer, and the n-type emitter layer.
  • According to the semiconductor device of this fourth preferred embodiment as described above, it is possible to prevent generation of holes being carriers in the first p-type diffusion layer 14 when the FWD is in the on state. For this reason, when the FWD is switched to the off state from the on state, it is possible to prevent the holes from being injected into the p-type anode layer 13 from the first p-type diffusion layer 14, thereby being possible to reduce the recovery current.
    • Fifth Preferred Embodiment
  • FIG. 5 is a sectional view for illustrating configuration of the semiconductor device according to a fifth preferred embodiment of the present invention. In the following, out of components to be described in this fifth preferred embodiment, components that are the same or similar to the components already described in the semiconductor device according to the fourth preferred embodiment are denoted by the same reference symbols, and different components are mainly described.
  • As illustrated in FIG. 5, in the semiconductor device according to this fifth preferred embodiment, the p-type anode layer 13 and the first p-type diffusion layer 14 are separated apart by a portion of the n-type drift layer 12, and the portion of the n-type drift layer 12 is separated apart from the surface electrode 24 by the protruding portion of the interlayer insulation film 23.
  • According to the semiconductor device of this fifth preferred embodiment as described above, it is possible to raise resistance 34 between the p-type anode layer 13 and the first p-type diffusion layer 14 as indicated by the imaginary line of FIG. 5. With this, it is possible to reduce the recovery current flowing from the first p-type diffusion layer 14 through intermediation of the p-type anode layer 13 to the n-type cathode layer.
    • Sixth Preferred Embodiment
  • FIG. 6 is a sectional view for illustrating configuration of the semiconductor device according to a sixth preferred embodiment of the present invention. In the following, out of components to be described in this sixth preferred embodiment, components that are the same or similar to the components already described in the semiconductor device according to the fourth preferred embodiment are denoted by the same reference symbols, and different components are mainly described.
  • As illustrated in FIG. 6, the semiconductor substrate 11 according to this sixth preferred embodiment further includes a separating region 35 having an n-type. The separating region 35 is interposed between the p-type anode layer 13 and the first p-type diffusion layer 14, and is arranged on the upper surface of the semiconductor substrate 11. An upper portion of the separating region 35 is separated apart from the surface electrode 24 by the protruding portion of the interlayer insulation film 23. Note that, in this sixth preferred embodiment, n-type impurity concentration of the separating region 35 is higher than the impurity concentration of the n-type drift layer 12.
  • According to the semiconductor device of this sixth preferred embodiment as described above, due to the formation of the separating region 35, manufacturing steps are increased in comparison to the fifth preferred embodiment. However, it is possible to cause a resistance value of resistance 36 between the p-type anode layer 13 and the first p-type diffusion layer 14 as partially indicated by the imaginary line of FIG. 6 to be an intended value. With this, it is possible to reduce the recovery current appropriately.
    • Seventh Preferred Embodiment
  • FIG. 7 is a plan view for illustrating configuration of the semiconductor device according to a seventh preferred embodiment of the present invention, and FIG. 8 is a sectional view for illustrating the configuration. In the following, out of components to be described in this seventh preferred embodiment, components that are the same or similar to the components already described in the related semiconductor device are denoted by the same reference symbols, and different components are mainly described.
  • As illustrated in FIG. 7 and FIG. 8, in the semiconductor device according to this seventh preferred embodiment, the first p-type diffusion layer 14 includes a plurality of selective injection layers 14 a and a semiconductor layer 14 b having the plurality of selective injection layers 14 a arranged therein. As illustrated in FIG. 7, the plurality of selective injection layers 14 a of a quadrangular shape are arranged in a zigzag pattern along a circumferential direction of the withstand-voltage retention region 3, and as illustrated in FIG. 8, the selective injection layers 14 a are arranged on an upper portion of the semiconductor layer 14 b. Note that, shapes, positions, and ranges of the plurality of selective injection layers 14 a are not limited to those illustrated in FIG. 7 and FIG. 8.
  • In this seventh preferred embodiment, the first p-type diffusion layer 14 is formed in such a manner that impurity is selectively injected within a region in which the first p-type diffusion layer 14 is to be formed. With this, impurity is injected into the plurality of selective injection layers 14 a, but impurity is not injected into the semiconductor layer 14 b. However, the impurity of the plurality of selective injection layers 14 a is diffused to the semiconductor layer 14 b due to thermal diffusion or the like. For this reason, generally, the impurity concentration of the semiconductor layer 14 b is lower than the impurity concentration of the selective injection layers 14 a. Note that, change in impurity concentration along a direction from one of the selective injection layers 14 a and the semiconductor layer 14 b to another may be steep or may be gentle. In this seventh preferred embodiment configured as described above, the first p-type diffusion layer 14 has uneven impurity concentration.
  • According to the semiconductor device of this seventh preferred embodiment as described above, it is possible to have mean impurity concentration in the entire first p-type diffusion layer 14 lower than the impurity concentration of the selective injection layers 14 a. With this, it is possible to prevent the generation of the holes in the first p-type diffusion layer 14 when the FWD is in the on state, thereby being possible to reduce the recovery current.
  • Note that, in the present invention, each of the preferred embodiments and each of the modified examples may be freely combined, and each of the preferred embodiments and each of the modified examples may be appropriately modified or omitted within the scope of the invention.
  • While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.

Claims (4)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an insulated gate bipolar transistor (IGBT) arranged therein, and a withstand-voltage retention region surrounding said first region and said second regions in plan view are defined, said semiconductor substrate having a first main surface and a second main surface;
a surface electrode arranged on said first main surface of said first region, of said second regions, and of said withstand-voltage retention region; and
a back-surface electrode arranged on said second main surface of said first region, of said second regions, and of said withstand-voltage retention region,
said semiconductor substrate further comprising:
an anode layer having a first conductivity type, which is arranged in said first main surface of said first region;
a diffusion layer having said first conductivity type, which is arranged in said first main surface of said withstand-voltage retention region adjacently to said anode layer; and
a cathode layer having a second conductivity type, which is arranged in said second main surface of said first region,
wherein a first trench is arranged in said first main surface on a side of said anode layer with respect to a boundary between said anode layer and said diffusion layer.
2. The semiconductor device according to claim 1, wherein a second trench crossing with said first trench is arranged in said anode layer.
3. A semiconductor device, comprising:
a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an insulated gate bipolar transistor (IGBT) arranged therein, and a withstand-voltage retention region surrounding said first region and said second regions in plan view are defined, said semiconductor substrate having a first main surface and a second main surface;
a surface electrode arranged on said first main surface of said first region and of said second regions; and
a back-surface electrode arranged on said second main surface of said first region, of said second regions, and of said withstand-voltage retention region,
said semiconductor substrate further comprising:
an anode layer having a first conductivity type, which is arranged in said first main surface of said first region;
a diffusion layer having said first conductivity type, which is arranged in said first main surface of said withstand-voltage retention region adjacently to said anode layer; and
a cathode layer having a second conductivity type, which is arranged in said second main surface of said first region,
wherein said surface electrode is out of contact with said diffusion layer.
4. A method of manufacturing a semiconductor device, said semiconductor device comprising:
a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an insulated gate bipolar transistor (IGBT) arranged therein, and a withstand-voltage retention region surrounding said first region and said second regions in plan view are defined, said semiconductor substrate having a first main surface and a second main surface;
a surface electrode arranged on said first main surface of said first region, of said second regions, of and said withstand-voltage retention region; and
a back-surface electrode arranged on said second main surface of said first region, said of second regions, and of said withstand-voltage retention region,
said semiconductor substrate further comprising:
an anode layer having a first conductivity type, which is arranged in said first main surface of said first region;
a diffusion layer having said first conductivity type, which is arranged in said first main surface of said withstand-voltage retention region adjacently to said anode layer; and
a cathode layer having a second conductivity type, which is arranged in said second main surface of said first region,
the method comprising forming said diffusion layer in such a manner that impurity is selectively injected within a region in which said diffusion layer is to be formed.
US15/851,447 2017-04-24 2017-12-21 Semiconductor device and method of manufacturing semiconductor device Abandoned US20180308838A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/875,457 US11610882B2 (en) 2017-04-24 2020-05-15 Semiconductor device and method of manufacturing semiconductor device
US18/062,475 US20230106654A1 (en) 2017-04-24 2022-12-06 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-085001 2017-04-24
JP2017085001A JP6804379B2 (en) 2017-04-24 2017-04-24 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/875,457 Division US11610882B2 (en) 2017-04-24 2020-05-15 Semiconductor device and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
US20180308838A1 true US20180308838A1 (en) 2018-10-25

Family

ID=63714384

Family Applications (3)

Application Number Title Priority Date Filing Date
US15/851,447 Abandoned US20180308838A1 (en) 2017-04-24 2017-12-21 Semiconductor device and method of manufacturing semiconductor device
US16/875,457 Active US11610882B2 (en) 2017-04-24 2020-05-15 Semiconductor device and method of manufacturing semiconductor device
US18/062,475 Pending US20230106654A1 (en) 2017-04-24 2022-12-06 Semiconductor device and method of manufacturing semiconductor device

Family Applications After (2)

Application Number Title Priority Date Filing Date
US16/875,457 Active US11610882B2 (en) 2017-04-24 2020-05-15 Semiconductor device and method of manufacturing semiconductor device
US18/062,475 Pending US20230106654A1 (en) 2017-04-24 2022-12-06 Semiconductor device and method of manufacturing semiconductor device

Country Status (4)

Country Link
US (3) US20180308838A1 (en)
JP (1) JP6804379B2 (en)
CN (1) CN108735737B (en)
DE (1) DE102018200136B4 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7192968B2 (en) * 2019-04-01 2022-12-20 三菱電機株式会社 semiconductor equipment
WO2022202009A1 (en) * 2021-03-26 2022-09-29 ローム株式会社 Semiconductor device

Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153586A1 (en) * 2001-04-18 2002-10-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20090001411A1 (en) * 2007-06-14 2009-01-01 Denso Corporation Semiconductor device
US20090242931A1 (en) * 2008-04-01 2009-10-01 Denso Corporation Semiconductor device having IGBT and diode
US20110006338A1 (en) * 2008-02-19 2011-01-13 Toyota Jidosha Kabushiki Kaisha Igbt and method of producing the same
US20110204469A1 (en) * 2010-02-19 2011-08-25 c/o FUJI ELECTRIC SYSTEMS CO., LTD. Semiconductor device and a method of manufacturing the same
US20120043581A1 (en) * 2010-08-17 2012-02-23 Masaki Koyama Semiconductor device
US20130001639A1 (en) * 2010-04-02 2013-01-03 Toyota Jidosha Kabushiki Kaisha Semiconductor device comprising semiconductor substrate having diode region and igbt region
US20130009205A1 (en) * 2011-07-04 2013-01-10 Denso Corporation Semiconductor device
US20130248924A1 (en) * 2012-03-23 2013-09-26 Kabushiki Kaisha Toshiba Semiconductor device
US20140197451A1 (en) * 2011-07-05 2014-07-17 Mitsubishi Electric Corporation Semiconductor device
US20140306267A1 (en) * 2011-11-09 2014-10-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US20140374871A1 (en) * 2012-01-12 2014-12-25 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US20150054118A1 (en) * 2012-03-22 2015-02-26 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US20150155277A1 (en) * 2013-12-04 2015-06-04 Kabushiki Kaisha Toshiba Semiconductor device
US20150349144A1 (en) * 2013-03-21 2015-12-03 Fuji Electric Co., Ltd. Semiconductor device
US20160043073A1 (en) * 2013-10-04 2016-02-11 Fuji Electric Co., Ltd. Semiconductor device
US20160141400A1 (en) * 2014-11-13 2016-05-19 Mitsubishi Electric Corporation Semiconductor device
US20160372584A1 (en) * 2014-02-10 2016-12-22 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US20170069625A1 (en) * 2014-04-28 2017-03-09 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the semiconductor device
US20170084610A1 (en) * 2015-09-17 2017-03-23 Denso Corporation Semiconductor device
US20170236908A1 (en) * 2016-02-16 2017-08-17 Fuji Electric Co., Ltd. Semiconductor device
US20170294526A1 (en) * 2014-12-23 2017-10-12 Abb Schweiz Ag Reverse-conducting semiconductor device
US20180076193A1 (en) * 2016-09-15 2018-03-15 Fuji Electric Co., Ltd. Semiconductor device
US20180108737A1 (en) * 2016-10-14 2018-04-19 Fuji Electric Co., Ltd. Semiconductor device
US9972675B1 (en) * 2016-11-11 2018-05-15 Mitsubishi Electric Corporation Power semiconductor device and method therefor
US20180182754A1 (en) * 2016-03-10 2018-06-28 Fuji Electric Co., Ltd. Semiconductor device
US20180233554A1 (en) * 2017-02-16 2018-08-16 Fuji Electric Co., Ltd. Semiconductor device
US20190019885A1 (en) * 2016-10-17 2019-01-17 Fuji Electric Co.,Ltd. Semiconductor device
US20190157264A1 (en) * 2017-02-15 2019-05-23 Fuji Electric Co., Ltd. Semiconductor device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745557B1 (en) * 1999-02-17 2007-08-02 가부시키가이샤 히타치세이사쿠쇼 Igbt and power conversion device
JP2004363327A (en) 2003-06-04 2004-12-24 Fuji Electric Device Technology Co Ltd Semiconductor device
JP2006173437A (en) 2004-12-17 2006-06-29 Toshiba Corp Semiconductor device
JP5011748B2 (en) * 2006-02-24 2012-08-29 株式会社デンソー Semiconductor device
JP5103830B2 (en) 2006-08-28 2012-12-19 三菱電機株式会社 Insulated gate semiconductor device
JP5052091B2 (en) 2006-10-20 2012-10-17 三菱電機株式会社 Semiconductor device
JP5283326B2 (en) 2006-10-27 2013-09-04 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US8507352B2 (en) * 2008-12-10 2013-08-13 Denso Corporation Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode
JP5515922B2 (en) 2010-03-24 2014-06-11 富士電機株式会社 Semiconductor device
JP5748353B2 (en) * 2011-05-13 2015-07-15 株式会社豊田中央研究所 Horizontal semiconductor device
JP2013026534A (en) 2011-07-25 2013-02-04 Toyota Central R&D Labs Inc Semiconductor device
JP6022774B2 (en) 2012-01-24 2016-11-09 トヨタ自動車株式会社 Semiconductor device
JP2014103376A (en) * 2012-09-24 2014-06-05 Toshiba Corp Semiconductor device
DE112013004846T5 (en) 2012-10-02 2015-06-11 Mitsubishi Electric Corporation Semiconductor device and method for its production
CN104838503A (en) * 2012-12-05 2015-08-12 丰田自动车株式会社 Semiconductor device
JP6668697B2 (en) 2015-05-15 2020-03-18 富士電機株式会社 Semiconductor device
JP6260605B2 (en) * 2015-11-19 2018-01-17 トヨタ自動車株式会社 Semiconductor device
JP6662393B2 (en) * 2015-12-28 2020-03-11 三菱電機株式会社 Semiconductor device and method of manufacturing semiconductor device
DE112017002382T5 (en) * 2016-12-16 2019-02-21 Fuji Electric Co., Ltd. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
JP6820738B2 (en) * 2016-12-27 2021-01-27 三菱電機株式会社 Manufacturing method of semiconductor device, power conversion device and semiconductor device

Patent Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153586A1 (en) * 2001-04-18 2002-10-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20090001411A1 (en) * 2007-06-14 2009-01-01 Denso Corporation Semiconductor device
US20110006338A1 (en) * 2008-02-19 2011-01-13 Toyota Jidosha Kabushiki Kaisha Igbt and method of producing the same
US20090242931A1 (en) * 2008-04-01 2009-10-01 Denso Corporation Semiconductor device having IGBT and diode
US20110204469A1 (en) * 2010-02-19 2011-08-25 c/o FUJI ELECTRIC SYSTEMS CO., LTD. Semiconductor device and a method of manufacturing the same
US20130001639A1 (en) * 2010-04-02 2013-01-03 Toyota Jidosha Kabushiki Kaisha Semiconductor device comprising semiconductor substrate having diode region and igbt region
US20120043581A1 (en) * 2010-08-17 2012-02-23 Masaki Koyama Semiconductor device
US20130009205A1 (en) * 2011-07-04 2013-01-10 Denso Corporation Semiconductor device
US20140197451A1 (en) * 2011-07-05 2014-07-17 Mitsubishi Electric Corporation Semiconductor device
US20140306267A1 (en) * 2011-11-09 2014-10-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US20140374871A1 (en) * 2012-01-12 2014-12-25 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US20150054118A1 (en) * 2012-03-22 2015-02-26 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US20130248924A1 (en) * 2012-03-23 2013-09-26 Kabushiki Kaisha Toshiba Semiconductor device
US20150349144A1 (en) * 2013-03-21 2015-12-03 Fuji Electric Co., Ltd. Semiconductor device
US20160043073A1 (en) * 2013-10-04 2016-02-11 Fuji Electric Co., Ltd. Semiconductor device
US20150155277A1 (en) * 2013-12-04 2015-06-04 Kabushiki Kaisha Toshiba Semiconductor device
US20160372584A1 (en) * 2014-02-10 2016-12-22 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US20170069625A1 (en) * 2014-04-28 2017-03-09 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the semiconductor device
US20160141400A1 (en) * 2014-11-13 2016-05-19 Mitsubishi Electric Corporation Semiconductor device
US20170294526A1 (en) * 2014-12-23 2017-10-12 Abb Schweiz Ag Reverse-conducting semiconductor device
US20170084610A1 (en) * 2015-09-17 2017-03-23 Denso Corporation Semiconductor device
US20170236908A1 (en) * 2016-02-16 2017-08-17 Fuji Electric Co., Ltd. Semiconductor device
US20180182754A1 (en) * 2016-03-10 2018-06-28 Fuji Electric Co., Ltd. Semiconductor device
US20180076193A1 (en) * 2016-09-15 2018-03-15 Fuji Electric Co., Ltd. Semiconductor device
US20180108737A1 (en) * 2016-10-14 2018-04-19 Fuji Electric Co., Ltd. Semiconductor device
US20190019885A1 (en) * 2016-10-17 2019-01-17 Fuji Electric Co.,Ltd. Semiconductor device
US9972675B1 (en) * 2016-11-11 2018-05-15 Mitsubishi Electric Corporation Power semiconductor device and method therefor
US20190157264A1 (en) * 2017-02-15 2019-05-23 Fuji Electric Co., Ltd. Semiconductor device
US20180233554A1 (en) * 2017-02-16 2018-08-16 Fuji Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
CN108735737B (en) 2024-02-27
DE102018200136B4 (en) 2022-11-03
JP6804379B2 (en) 2020-12-23
CN108735737A (en) 2018-11-02
US11610882B2 (en) 2023-03-21
JP2018186111A (en) 2018-11-22
US20230106654A1 (en) 2023-04-06
US20200279843A1 (en) 2020-09-03
DE102018200136A1 (en) 2018-10-25

Similar Documents

Publication Publication Date Title
KR101309674B1 (en) Insulated gate bipolar transistor and manufacturing method thereof
WO2018155566A1 (en) Silicon carbide semiconductor device, and electric power converting device
WO2014199465A1 (en) Semiconductor apparatus
US20230106654A1 (en) Semiconductor device and method of manufacturing semiconductor device
KR101613442B1 (en) Insulating gate-type bipolar transistor
WO2020026401A1 (en) Wide band gap semiconductor device and power conversion device
US20150187877A1 (en) Power semiconductor device
US20120273897A1 (en) Semiconductor Device and Electric Power Conversion Device Using Same
CN108258039B (en) Conductivity modulated drain extension MOSFET
JP2010135646A (en) Semiconductor device
JP5135666B2 (en) Power converter
US9153678B2 (en) Power semiconductor device and method of manufacturing the same
US10186571B2 (en) Power semiconductor device and method therefor
US10404250B2 (en) Transistor device
JP6843952B2 (en) Manufacturing method of semiconductor devices
JP4020871B2 (en) Semiconductor device
US9105486B2 (en) Semiconductor device
JP6002387B2 (en) Diode and power conversion system using the same
JP2001102392A (en) Semiconductor device and power conversion device using the same
US20150187869A1 (en) Power semiconductor device
WO2022224840A1 (en) Semiconductor device, power conversion device using same, and manufacturing method for semiconductor device
KR20230165511A (en) RC IGBT having a structure to suppress snapback
KR20140063327A (en) A insulated gate bipolar transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI ELECTRIC CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKAMURA, HIROYUKI;SONEDA, SHINYA;REEL/FRAME:044466/0851

Effective date: 20171012

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION