JP2018078230A - 電力用半導体装置およびその製造方法 - Google Patents
電力用半導体装置およびその製造方法 Download PDFInfo
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Abstract
Description
本明細書では、第1導電型をn型、第2導電型をp型として説明するが、逆の導電型であっても良い。
<B−1.構成>
図7は、本発明の実施の形態1に係るRC−IGBT101Aのチップ上面図である。RC−IGBT101Aは、IGBT領域2、ダイオード領域3、耐圧保持領域4およびゲートパッド5を備えて構成される点で前提技術に係るRC−IGBT1と同様であるが、ダイオード領域3に囲まれた領域に高電界セル領域13を配置する点がRC−IGBT1と異なる。
RC−IGBT101A,101Bでは、IGBTセル7、ダイオードセル8および耐圧保持構造9よりも意図的に電界強度が高くなるように設計した高電界セル14を、n−型ドリフト層6のうち第2主面側にn型拡散層(n+型拡散層15)が配置されている領域の第1主面側に配置する。これにより、素子耐圧を超えるコレクタ−エミッタ間電圧が印加された際に発生するアバランシェ電流を高電界セル14に誘引することができる。すなわち、アバランシェ電流はアバランシェ破壊に対する耐性が高いp−i−n構造となっている領域で発生することになり、結果としてアバランシェ破壊耐量が向上する。
以上に説明したように、本発明の実施の形態1に係るRC−IGBT101A,101Bは、第1導電型のドリフト層であるn−型ドリフト層6と、n−型ドリフト層6の第1主面上に形成されるIGBTセル7、ダイオードセル8および耐圧保持構造9と、n−型ドリフト層6の第1主面上の、IGBTセル7に囲まれる領域又はダイオードセル8に囲まれる領域に形成される高電界セル14と、n−型ドリフト層6の第1主面とは反対側の第2主面上の、IGBTセル7および耐圧保持構造9に対向する位置に形成される第2導電型のコレクタ層であるp+型コレクタ層11と、n−型ドリフト層6の第2主面上のダイオードセル8に対向する位置に形成される第1導電型のカソード層であるn+型カソード層12と、n−型ドリフト層6の第2主面上の高電界セル14に対向する位置に形成される第1導電型の拡散層であるn+型拡散層15と、を備える。そして、高電界セル14は、主端子間電圧であるエミッタ―コレクタ間電圧を印加した際に発生する最大電界強度がIGBTセル7、ダイオードセル8および耐圧保持構造9よりも高い。また、p+型コレクタ層11と高電界セル14とは平面視において重ならない。従って、本発明の目的である、アバランシェ破壊耐量を確保しつつ、n−型ドリフト層6の厚みを薄くして素子性能を改善する事が実現可能となる。高電界セル14を配置し、かつn−型ドリフト層6の厚みを薄くすると、全体的な素子耐圧が低下してしまうデメリットがあるが、アバランシェ破壊耐量を上げた事によってn−型ドリフト層6の比抵抗を高く設計する事ができるようになるため、それにより素子耐圧の低下を補うことができる。
<C−1.構成>
実施の形態2に係るRC−IGBT102のチップ上面図は、図7に示した実施の形態1に係るRC−IGBT101Aのチップ上面図と同様である。
IGBT領域2にトレンチ構造を形成してIGBT素子の損失性能を良くすることは公知の技術であり、そのトレンチ構造をダイオード領域3にも同時に形成することも公知の技術である。本発明では、高電界セル領域13に形成される一部もしくは全部のトレンチをIGBT領域2およびダイオード領域3のトレンチよりも深くすることで、IGBT領域2およびダイオード領域3よりも高電界セル領域13の電界強度を高く設計することができる。従って、コストアップなく、n−型ドリフト層6を薄くすることによる素子性能の改善と、アバランシェ破壊の耐量の確保とを実現することができる。
<D−1.構成>
実施の形態3に係るRC−IGBT103Aのチップ上面図は、図7に示した実施の形態1に係るRC−IGBT101Aのチップ上面図と同様である。
高電界セル領域13のみトレンチ21のピッチを広げる事で、高電界セル領域13の電界強度をIGBT領域2およびダイオード領域3よりも高く設計することができる。従って、RC−IGBTにおいて、n−型ドリフト層6を薄くすることによる素子性能の改善を実現するとともに、アバランシェ破壊の耐量を確保することができる。
<E−1.構成>
実施の形態4に係るRC−IGBT104のチップ上面図は、図7に示した実施の形態1に係るRC−IGBT101Aのチップ上面図と同様である。RC−IGBT104のIGBT領域2の断面図を図21に、高電界セル領域13の断面図を図22にそれぞれ示す。図21に示すように、RC−IGBT104は、IGBT領域2においてp型ベース層18とn−型ドリフト層6との間にn型のキャリアストア層29を備えている。また、図22に示すように、RC−IGBT104は、高電界セル領域13においてp型アノード層26とn−型ドリフト層6との間にn型のキャリアストア層29を備えている。キャリアストア層29以外のRC−IGBT104の構成は、実施の形態3に係るRC−IGBT103Aと同様である。
IGBT素子の損失性能を良くするためIGBT領域にn型のキャリアストア層を形成する構造は、特許第3288218号で提案されている。キャリアストア層29を備える場合、備えない場合よりもトレンチピッチの拡大により電界が強くなりやすくなる。RC−IGBT104では、高電界セル14にn型のキャリアストア層29を備えるため、トレンチ21のピッチを大きくした際に高電界セル14の電界が高くなりやすい。従って、高電界セル領域13とIGBT領域2およびダイオード領域3との電界差を確保しやすい。
<F−1.構成>
実施の形態5に係るRC−IGBT105のチップ上面図は、図7に示した実施の形態1に係るRC−IGBT101Aのチップ上面図と同様である。
ダイオード領域3にプロトンを照射すると、局所的にシリコンのライフタイムを制御でき、ダイオード素子としての損失性能を良くする事ができる。また、プロトン照射を行うと、それによって同時にn型層30が形成される。従って、ダイオード領域3および高電界セル14にプロトン照射を行うことで、局所的にライフタイムを制御してダイオード素子の損失性能を改善できると共に、同時に形成されるn型層30によって高電界セル14の電界強度を高く設計しやすくなり、他領域との電界強度差を確保しやすくなる。
上記の実施の形態ではRC−IGBTへの本発明の適用例を説明したが、IGBT領域を備えないダイオードにも本発明を適用可能である。
Claims (6)
- 第1導電型のドリフト層と、
前記ドリフト層の第1主面上に形成されるIGBTセル、ダイオードセルおよび耐圧保持構造と、
前記ドリフト層の前記第1主面上の、前記IGBTセルに囲まれる領域又は前記ダイオードセルに囲まれる領域に形成される高電界セルと、
前記ドリフト層の前記第1主面とは反対側の第2主面上の、前記IGBTセルおよび前記耐圧保持構造に対向する位置に形成される第2導電型のコレクタ層と、
前記ドリフト層の前記第2主面上の、前記ダイオードセルに対向する位置に形成される第1導電型のカソード層と、
前記ドリフト層の前記第2主面上の、前記高電界セルに対向する位置に形成される第1導電型の拡散層と、を備え、
前記高電界セルは、主端子間電圧を印加した際に発生する最大電界強度が前記IGBTセル、前記ダイオードセルおよび前記耐圧保持構造より高く、
前記コレクタ層および前記高電界セルは、前記ドリフト層の第1主面に垂直な方向から視た平面視において重ならない、
電力用半導体装置。 - 前記コレクタ層と前記高電界セルとの前記ドリフト層の第1主面に平行な方向の距離は、前記高電界セルで発生したアバランシェ電流が前記ドリフト層中を前記ドリフト層の前記第1主面に平行な方向に拡散する距離よりも長い、
請求項1に記載の電力用半導体装置。 - 前記ドリフト層に至る複数のトレンチが前記IGBTセル、前記ダイオードセル及び前記高電界セルに形成され、
前記高電界セルから前記ドリフト層に至る前記複数のトレンチのうち少なくとも一部のトレンチの深さが、前記IGBTセル及び前記ダイオードセルから前記ドリフト層に至る前記複数のトレンチよりも深い、
請求項1又は2に記載の電力用半導体装置。 - 前記ドリフト層に至る複数のトレンチが前記IGBTセル、前記ダイオードセル及び前記高電界セルに形成され、
前記高電界セルから前記ドリフト層に至るトレンチのピッチのうち少なくとも一部のピッチが、前記IGBTセル及び前記ダイオードセルから前記ドリフト層に至るトレンチのピッチよりも大きい、
請求項1から3のいずれか1項に記載の電力用半導体装置。 - 前記IGBTセルおよび前記高電界セルに第1導電型のキャリアストア層を備え、
前記キャリアストア層における第1導電型不純物のピーク濃度は1×1015/cm3以上である、
請求項4に記載の電力用半導体装置。 - 請求項1から5のいずれか1項に記載の電力用半導体装置の製造方法であって、
前記ダイオードセル上および前記高電界セル上からプロトン照射する工程を備える、
電力用半導体装置の製造方法。
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