CN112768521B - 横向双扩散金属氧化物半导体器件 - Google Patents

横向双扩散金属氧化物半导体器件 Download PDF

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CN112768521B
CN112768521B CN201911001601.3A CN201911001601A CN112768521B CN 112768521 B CN112768521 B CN 112768521B CN 201911001601 A CN201911001601 A CN 201911001601A CN 112768521 B CN112768521 B CN 112768521B
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semiconductor device
metal oxide
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CN112768521A (zh
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祝靖
朱桂闯
何乃龙
张森
李少红
孙伟锋
时龙兴
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Southeast University
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to KR1020227004225A priority patent/KR102649820B1/ko
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Abstract

本发明涉及一种横向双扩散金属氧化物半导体器件包括:漂移区,具有第一导电类型;第一体区,设于所述漂移区上,具有第二导电类型;所述第一导电类型和第二导电类型为相反的导电类型;第一导电类型区,设于所述第一体区内;第二体区,设于所述第一导电类型区内,具有第二导电类型;源极区,设于所述第二体区内,具有第一导电类型;接触区,设于所述第一体区内,具有第二导电类型。本发明解决了LDMOS的体二极管在反向恢复期间,因寄生NPN开启导致的反向恢复失效问题,并且不需要设置沟槽隔离结构。

Description

横向双扩散金属氧化物半导体器件
技术领域
本发明涉及半导体制造领域,特别是涉及一种横向双扩散金属氧化物半导体器件。
背景技术
LDMOS(Laterally Diffused Metal Oxide Semiconductor,横向扩散金属氧化物半导体)器件内部存在体二极管。体二极管在器件续流期间起主导作用,然而在体二极管反向恢复期间,当漂移区的空穴经P-body、源区P+被抽取回源极时,由于P-body区电阻的存在,在P-body和源区N+间会产生一定的压降,当该压降大于由P-body和源区N+构成的PN结的正向导通压降时,由源区N+、P-body和N-drift构成的寄生NPN就会开启,导致电流急剧增加,出现反向恢复失效的现象。如图4,虚线表示反向恢复正常,实线表示反向恢复失效。
如果器件反向恢复失效,在电路的应用中可能会损坏其他器件,严重影响器件与电路的安全性、可靠性。
发明内容
基于此,有必要提供一种能够解决反向恢复失效问题的横向双扩散金属氧化物半导体器件。
一种横向双扩散金属氧化物半导体器件包括:漂移区,具有第一导电类型;第一体区,设于所述漂移区上,具有第二导电类型;所述第一导电类型和第二导电类型为相反的导电类型;第一导电类型区,设于所述第一体区内;第二体区,设于所述第一导电类型区内,具有第二导电类型;源极区,设于所述第二体区内,具有第一导电类型;接触区,设于所述第一体区内,具有第二导电类型。
在其中一个实施例中,还包括设于所述漂移区上的漏极区。
在其中一个实施例中,还包括设于所述漂移区上的缓冲区,所述缓冲区具有第一导电类型,所述缓冲区设于所述漂移区内。
在其中一个实施例中,还包括设于所述源极区和漏极区之间的栅极。
在其中一个实施例中,还包括设于所述源极区和漏极区之间的场氧层,所述栅极包括从所述源极区上延伸至所述场氧层上的多晶硅栅。
在其中一个实施例中,所述第一导电类型是N型,所述第二导电类型是P型。
在其中一个实施例中,所述器件等效于具有第一MOS管、第二MOS管、体二极管及寄生NPN三极管,所述第一MOS管和第二MOS管的栅极包括所述多晶硅栅,所述第一MOS管的源极和第二MOS管的漏极包括所述第一导电类型区,所述第一MOS管的漏极包括所述漏极区,所述第二MOS管的源极包括所述源极区,所述体二极管的阴极包括所述漂移区、阳极包括所述第一体区,所述寄生NPN三极管的基极包括所述第一体区、集电极包括所述漂移区、发射极包括所述第一导电类型区。
在其中一个实施例中,所述漂移区和缓冲区的掺杂浓度低于所述源极区和漏极区的掺杂浓度。
在其中一个实施例中,还包括第二导电类型的衬底和所述衬底上的埋氧层,所述漂移区设于所述埋氧层上。
在其中一个实施例中,所述第一体区的掺杂浓度低于所述接触区的掺杂浓度。
上述横向双扩散金属氧化物半导体器件,通过第二体区和第一导电类型区将源极区与第一体区隔离。这样在LDMOS的体二极管反向恢复期间,即使漂移区的空穴经第一体区、接触区被抽取回源极时,在第一体区和源极区之间产生一定的压降,电子也无法经由源极区注入到第一体区;而空穴可以通过接触区被抽取回源极,由源极区、第一体区和漂移区构成的寄生NPN不会开启,解决了LDMOS的体二极管在反向恢复期间,因寄生NPN开启导致的反向恢复失效问题。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例,可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是示例性的横向双扩散金属氧化物半导体器件的剖面结构示意图;
图2是图1所示器件的等效电路图;
图3是一实施例中横向双扩散金属氧化物半导体器件的剖面结构示意图;
图4是LDMOS的体二极管反向恢复正常和反向恢复失效时示例性的电流曲线;
图5是图3所示器件的等效电路图;
图6是本申请与传统的横向双扩散金属氧化物半导体器件的耐压特性曲线图;
图7是本申请与传统的横向双扩散金属氧化物半导体器件的导通能力特性曲线图;
图8是相同续流电流值下的反向恢复电流(IDS)随时间变化曲线。
具体实施方式
为了便于理解本发明,下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是,本发明可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样,可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此,本发明的实施例不应当局限于在此所示的区的特定形状,而是包括由于例如制造导致的形状偏差。例如,显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度,而不是从注入区到非注入区的二元改变。同样,通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此,图中显示的区实质上是示意性的,它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇,例如对于P型和N型杂质,为区分掺杂浓度,简易的将P+型代表重掺杂浓度的P型,P型代表中掺杂浓度的P型,P-型代表轻掺杂浓度的P型,N+型代表重掺杂浓度的N型,N型代表中掺杂浓度的N型,N-型代表轻掺杂浓度的N型。
对于工作电流较大的器件,对其导通电阻要求较高,需要在保证击穿电压的条件下降低其电阻。一般降低导通电阻的方式是调节漂移区掺杂浓度,但是由于掺杂浓度的提高会导致击穿电压下降,因此还需要采取额外的结构来保证击穿电压,例如场板,STI(浅沟槽隔离)技术;另外还可以调整电流在漂移区的流通途径,即使漂移区电流路径变短,通过减少漂移区长度等实现。目前从这些方面出发还衍生了很多相关新型结构,如RESURF(降低表面电场)技术,分段线性掺杂技术。然而这些结构在降低导通电阻的同时都会随之带来击穿电压的降低,需要额外采取措施保证两者均达到设计指标,这样对器件整体的结构改动较大。
图1是示例性的横向双扩散金属氧化物半导体器件的剖面结构示意图,图2是图1的等效电路图。示例性的横向双扩散金属氧化物半导体器件包括P型衬底(P-sub),埋氧层(BOX),漂移区(N-drift),体区(P-body),缓冲区(N-buffer),漏区N+,源区N+及源区P+。请参照图2,LDMOS的栅、源、漏分别用g、s、d表示,体区和漂移区构成的体二极管D在器件续流期间起主导作用,然而在体二极管D反向恢复期间,当漂移区的空穴经体区、源区P+被抽取回源极时,由于体区电阻Rs的存在,在体区和源区N+间会产生一定的压降,当该压降大于由体区和源区N+构成的PN结的正向导通压降时,由源区N+、体区和漂移区构成的寄生NPN就会开启,导致电流急剧增加,出现反向恢复失效的现象,如图4所示。一种示例性的解决方案是采用沟槽隔离技术,然而这样器件尺寸会变大,并且工艺成本高且较复杂,受条件限制有时候难以实现。
图3是一实施例中横向双扩散金属氧化物半导体器件的剖面结构示意图,包括漂移区3、第一体区10、第一导电类型区13、第二体区12、源极区11及接触区9。漂移区3具有第一导电类型。第一导电类型区13设于第一体区10内。第二体区12设于第一导电类型区13内,具有第二导电类型。源极区11设于第二体区12内,具有第一导电类型。接触区9设于第一体区10内,具有第二导电类型。
在图3所示的实施例中,第一导电类型是N型,第二导电类型是P型;具体地,漂移区3为N型漂移区N-drift,第一体区10和第二体区12均为P型体区,第一导电类型区13为能够在本申请中起隔离作用的N型隔离层,源极区11为源区N型重掺杂N+区,接触区9为源区P型重掺杂P+区。在另一个实施例中,也可以第一导电类型是P型,第二导电类型是N型。
上述横向双扩散金属氧化物半导体器件,通过第二体区12和第一导电类型区13将源极区11与第一体区10隔离。这样在LDMOS的体二极管反向恢复期间,即使漂移区3的空穴经第一体区10、接触区9被抽取回源极时,在第一体区10和源极区11之间产生一定的压降,电子也无法经由源极区11注入到第一体区10;而空穴可以通过接触区9被抽取回源极,由源极区11、第一体区10和漂移区3构成的寄生NPN不会开启,解决了LDMOS的体二极管在反向恢复期间,因寄生NPN开启导致的反向恢复失效问题。
在图3所示的实施例中,横向双扩散金属氧化物半导体器件还包括设于漂移区3上的漏极区5。具体地,漏极区5是漏区N型重掺杂N+区。
在图3所示的实施例中,横向双扩散金属氧化物半导体器件还包括设于漂移区3上的缓冲区4,缓冲区4是设于漂移区3内,缓冲区4具有第一导电类型。
在图3所示的实施例中,横向双扩散金属氧化物半导体器件还包括第二导电类型的衬底1和衬底上的埋氧层2,漂移区3设于埋氧层上。具体地,衬底1是P-sub。
在一个实施例中,横向双扩散金属氧化物半导体器件还包括设于源极区11和漏极区5之间的栅极。在图3所示的实施例中,横向双扩散金属氧化物半导体器件还包括设于源极区11和漏极区5之间的场氧层7,栅极包括从源极区11上延伸至场氧层7上的多晶硅栅8。多晶硅栅8从源极区11上先后经过第二体区12上、第一导电类型区13上、第一体区10上,然后延伸至场氧层7上。在图3所示的实施例中,接触区9与第一导电类型区13之间被第一体区10隔开。
在一个实施例中,漂移区3和缓冲区4的掺杂浓度低于源极区11和漏极区5的掺杂浓度。
在一个实施例中,第一体区10的掺杂浓度低于接触区9的掺杂浓度。
参照图5,在该实施例中,横向双扩散金属氧化物半导体器件等效于具有第一MOS管、第二MOS管、体二极管D及寄生NPN三极管。请一并参照图3,多晶硅栅8作为第一MOS管和第二MOS管的栅极g,第一导电类型区13作为第一MOS管的源极s1、第二MOS管的漏极d2及寄生NPN三极管的发射极,漏极区5作为第一MOS管的漏极d1,源极区11作为第二MOS管的源极S2,漂移区3作为体二极管D的阴极和寄生NPN三极管的集电极,第一体区10作为二极管D阳极和寄生NPN三极管的基极。第一体区10还等效有体区电阻Rs。当器件的栅极接高电位、漏极接高电位、源极接低电位时,多晶硅栅8下的第一体区10和第二体区12可以正常反型出电子沟道,LDMOS可以实现正向导通。当栅极接低电位、漏极接高电位、源极接低电位时,沟道关断,器件内部由第一体区10和漂移区3构成的体二极管D进行耐压。当栅极和源极短接高电位,漏极接低电位,器件内部由第一体区10和漂移区3构成的体二极管D导通,器件可以进行续流。综上,上述横向双扩散金属氧化物半导体器件的工作状态、工作条件和传统LDMOS完全一致。
图6是本申请与传统的横向双扩散金属氧化物半导体器件的耐压特性曲线图,横纵坐标分别是沟道关断的漏源两端的电压VDS和流过的电流IDS;图7是本申请与传统的横向双扩散金属氧化物半导体器件的导通能力特性曲线图,横纵坐标分别是沟道开启的漏源两端的电压VDS和流过的电流IDS。可以看到本申请的横向双扩散金属氧化物半导体器件在解决了体二极管反向恢复失效问题的前提下,导通能力与耐压特性几乎不会有所牺牲。与需要设置沟槽隔离结构来解决体二极管反向恢复失效问题的方案相比,本申请无需设置该沟槽隔离结构,工艺简单,工艺兼容性强,且缩小了器件的尺寸。如图8为相同续流电流值下的反向恢复电流(IDS)随时间变化曲线,di/dt=105A/μs的曲线为一种传统横向双扩散金属氧化物半导体器件,可以看到,传统结构在di/dt=105A/μs时就发生了反向恢复失效。另外三条曲线为本申请的横向双扩散金属氧化物半导体器件,可以看到在di/dt=536A/μs时依旧没有发生反向恢复失效,LDMOS体二极管反向恢复鲁棒性得以大幅提升。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种横向双扩散金属氧化物半导体器件,其特征在于,包括:
漂移区,具有第一导电类型;
第一体区,设于所述漂移区上,具有第二导电类型;所述第一导电类型和第二导电类型为相反的导电类型;
第一导电类型区,设于所述第一体区内;
第二体区,设于所述第一导电类型区内,具有第二导电类型;
源极区,设于所述第二体区内,具有第一导电类型;
接触区,设于所述第一体区内、所述第一导电类型区外,具有第二导电类型。
2.根据权利要求1所述的横向双扩散金属氧化物半导体器件,其特征在于,还包括设于所述漂移区上的漏极区。
3.根据权利要求2所述的横向双扩散金属氧化物半导体器件,其特征在于,还包括设于所述漂移区上的缓冲区,所述缓冲区具有第一导电类型,所述缓冲区设于所述漂移区内。
4.根据权利要求2或3所述的横向双扩散金属氧化物半导体器件,其特征在于,还包括设于所述源极区和漏极区之间的栅极。
5.根据权利要求4所述的横向双扩散金属氧化物半导体器件,其特征在于,还包括设于所述源极区和漏极区之间的场氧层,所述栅极包括从所述源极区上延伸至所述场氧层上的多晶硅栅。
6.根据权利要求5所述的横向双扩散金属氧化物半导体器件,其特征在于,所述第一导电类型是N型,所述第二导电类型是P型。
7.根据权利要求6所述的横向双扩散金属氧化物半导体器件,其特征在于,所述器件等效于具有第一MOS管、第二MOS管、体二极管及寄生NPN三极管,所述第一MOS管和第二MOS管的栅极包括所述多晶硅栅,所述第一MOS管的源极和第二MOS管的漏极包括所述第一导电类型区,所述第一MOS管的漏极包括所述漏极区,所述第二MOS管的源极包括所述源极区,所述体二极管的阴极包括所述漂移区、阳极包括所述第一体区,所述寄生NPN三极管的基极包括所述第一体区、集电极包括所述漂移区、发射极包括所述第一导电类型区。
8.根据权利要求3所述的横向双扩散金属氧化物半导体器件,其特征在于,所述漂移区和缓冲区的掺杂浓度低于所述源极区和漏极区的掺杂浓度。
9.根据权利要求1所述的横向双扩散金属氧化物半导体器件,其特征在于,还包括第二导电类型的衬底和所述衬底上的埋氧层,所述漂移区设于所述埋氧层上。
10.根据权利要求1所述的横向双扩散金属氧化物半导体器件,其特征在于,所述第一体区的掺杂浓度低于所述接触区的掺杂浓度。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107302025A (zh) * 2017-07-27 2017-10-27 电子科技大学 一种具有抗单粒子效应的vdmos器件
CN108878531A (zh) * 2017-05-15 2018-11-23 英飞凌科技股份有限公司 半导体器件、其设计方法和制造方法以及电子电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020179968A1 (en) * 2001-05-30 2002-12-05 Frank Pfirsch Power semiconductor component, compensation component, power transistor, and method for producing power semiconductor components
US7060545B1 (en) 2002-10-31 2006-06-13 Micrel, Inc. Method of making truncated power enhanced drift lateral DMOS device with ground strap
JP5272410B2 (ja) * 2008-01-11 2013-08-28 富士電機株式会社 半導体装置およびその製造方法
CN101587910A (zh) 2009-06-19 2009-11-25 东南大学 N型绝缘体上硅的横向双扩散金属氧化物半导体晶体管
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KR101710599B1 (ko) * 2011-01-12 2017-02-27 삼성전자 주식회사 반도체 장치 및 그 제조 방법
WO2014033991A1 (ja) * 2012-08-30 2014-03-06 パナソニック株式会社 半導体装置
JP2014207324A (ja) * 2013-04-12 2014-10-30 旭化成エレクトロニクス株式会社 半導体装置及びその製造方法
DE102019104070A1 (de) * 2018-02-20 2019-08-22 Maxim Integrated Products, Inc. Multi-Transistor-Vorrichtungen
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878531A (zh) * 2017-05-15 2018-11-23 英飞凌科技股份有限公司 半导体器件、其设计方法和制造方法以及电子电路
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