CN1812120A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1812120A
CN1812120A CNA2005100229187A CN200510022918A CN1812120A CN 1812120 A CN1812120 A CN 1812120A CN A2005100229187 A CNA2005100229187 A CN A2005100229187A CN 200510022918 A CN200510022918 A CN 200510022918A CN 1812120 A CN1812120 A CN 1812120A
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China
Prior art keywords
mentioned
layer
semiconductor device
field plate
film
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CNA2005100229187A
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English (en)
Inventor
渡边充
福井哲也
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Toshiba Corp
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Toshiba Corp
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Publication of CN1812120A publication Critical patent/CN1812120A/zh
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Abstract

本发明提供一种没有因焊接而导致的特性劣化的半导体装置。本发明的半导体装置具有：半导体元件芯片、和利用焊锡材料分别接合了半导体元件芯片的上下端子电极的上下导体框架，上述半导体元件芯片具有：第一导电型的半导体层；在上述半导体层上有选择地形成的第二导电型扩散层；在上述半导体层的上述第二导电型扩散层的外侧形成的第二导电型的多个护圈层；形成在上述半导体层上的绝缘膜；以及埋设在上述绝缘膜中的、由多晶硅膜形成的场极板。

Description

半导体装置
技术领域
本发明涉及具有耐高压用的护圈结构的半导体装置，特别是涉及利用焊锡材料将平面型半导体元件芯片的上下端子电极与上下导体框架接合的半导体装置。
背景技术
在电力用半导体元件的领域中，已知为了控制延伸到高阻半导体层内的耗尽层以实现高耐压，以环绕端子扩散层的方式形成护圈层，进一步在护圈层上部配置场极板的技术(例如，参照专利文献1)。
图11是具有护圈结构的平面型半导体元件，示出应用了引线接合方式的一例的主要部分截面图。该半导体元件芯片是二极管，将高阻的N型半导体基板101作为基极半导体层，在其表面上有选择性地形成有具有P型扩散层的阳极层102，在背面形成有N+型阴极层103。
在N型基极层101的表面上，以环绕阳极层102的周围的方式形成有具有P型扩散层的多个护圈层104。在芯片的最外周表面形成有N+型的沟道截断层105。
元件表面由硅氧化膜等绝缘膜106覆盖，在元件表面上形成开口，形成与阳极层102接触的阳极电极107。阳极电极107的一部分在绝缘膜106上延长，成为位于第一个护圈层上的场极板107a。此外，与阳极电极107同时形成覆盖第二个和第三个护圈层的场极板108、以及一端与沟道截断层105连接并在绝缘膜106上延长的等电位环(Equipotential Ring：EQPR)电极109。
在形成了阳极电极107、场极板108和EQPR电极109的面上，形成钝化膜110。钝化膜110是通过等离子CVD等形成的硅氮化膜和硅氧化膜、或者聚酰亚胺膜。在该钝化膜110上形成开口，引线112与阳极电极107接合。
如上所述的引线接合方式的耐高压半导体元件有因接合引线而难以薄型化，难以保证耐高电流量的问题。为了解决这些问题，最好是使用通过焊锡材料将半导体元件芯片与导体框架接合的焊接方式。
但是，若在平面型半导体元件上使用这样的焊接方式，就产生另外的问题。图12示出通过焊锡材料111将与图11相同的半导体元件芯片的阳极电极107与导体框架113接合的例子。为了进行这样的焊接，在阳极电极107等的端子电极上需要使用例如以V/Ni/Au等的Ni为主体的层叠金属膜来取代通常使用的Al电极。
但是，若使用这样的层叠金属电极，就不能使用如图11中说明的钝化膜110。这是因为，在形成了阳极电极之后，如果进行需要高于等于300℃的高温的钝化膜形成工序，就产生Ni的熔融和Au的氧化等，阳极电极的焊锡粘结性就劣化。
从而，图12中例示了在没有覆盖阳极电极107和场极板108的保护膜的状态下焊接阳极电极107和框架113之间的例子。但是，该情况下，如图12所示，能够产生分散的焊锡材料111a使阳极电极107与场极板108之间短路的情况。这种施加反偏压时的耗尽层的延伸方式与期望的状态不同，导致耐压特性劣化。
另外，在图12的结构中没有钝化膜，在施加高电压时，在场极板108与EQPR电极109之间容易产生空间放电(火花)。这导致绝缘破坏和元件特性的劣化。
这样，要在平面型半导体元件中进行双面焊接，就存在各种问题。因此，现有的双面焊接高耐压半导体元件不是平面型，一般使用台面型。但是，台面型半导体元件由于PN结在台斜面上终止，因此，反向偏压时的泄漏电流比平面型大，在高温环境下容易产生热失控等的不稳定的因素很多。
专利文献1：日本特开2003-101039号公报
发明内容
本发明的目的在于，提供一种没有因焊接而导致的特性劣化的半导体装置。
根据本发明的一个方式的半导体装置，具有半导体元件芯片、和利用焊锡材料将半导体元件芯片的上下端子电极分别接合的上下导体框架，上述半导体元件芯片具有：
第一导电型的半导体层；
在上述半导体层上有选择地形成的第二导电型扩散层；
在上述半导体层的上述第二导电型扩散层的外侧形成的第二导电型的多个护圈层；
形成在上述半导体层上的绝缘膜；
埋设在上述绝缘膜中的、由多晶硅膜形成的场极板。
发明效果
根据本发明，能够提供一种没有因焊接而导致的特性劣化的半导体装置。
附图说明
图1是本发明的实施方式的半导体元件芯片的俯视图；
图2是图1的II-II’截面图；
图3是示出上述半导体元件芯片的场极板和截断电极的形成工序的图；
图4是示出上述半导体元件芯片的CVD氧化膜形成工序的图；
图5是示出上述半导体元件芯片的阳极电极形成工序的图；
图6是示出上述半导体元件芯片的框架搭载状态的俯视图；
图7是图6的I-I’截面图；
图8是图6的I-I’截面图的其他例子；
图9是示出半导体元件芯片的其他的框架搭载状态的俯视图；
图10是示出半导体元件芯片的其他的框架搭载状态的俯视图；
图11是现有的具有护圈结构的平面型半导体元件的截面图；
图12是对图11的平面型半导体元件的基本结构应用焊接方式的情况的截面图。
具体实施方式
以下，参照附图说明本发明的实施方式。
图6是根据一个实施方式的半导体装置的俯视图，图7或图8是其I-I’截面图。半导体元件芯片1是耐高压的平面型半导体元件，其上下端子电极分别利用焊锡材料4与由Cu等构成的上下导体框架2、3接合。半导体元件芯片1和导体框架2、3被塑封树脂5密封。
图1是一分为四的半导体元件芯片1的俯视图，图2是它的II-II’截面图。该半导体元件芯片1是整流用PN结二极管，将高阻的N型半导体衬底11作为基极半导体层，在其上面有选择地形成由P型扩散层构成的阳极层12，在底面上形成有N+型阴极层13。
在基极半导体层11的上面，以环绕阳极层12的周围的方式，按规定间隔形成有具有P型扩散层的多个护圈层14。在此示出了设置3个护圈层14的例子，但也可以是大于等于2个。在芯片的最外周表面上形成有具有N+型扩散层的沟道截断层(EQPR层)15。
形成有扩散层的元件芯片上面由硅氧化膜等绝缘膜16覆盖，在该绝缘膜16上形成开口，形成与阳极层12接触的上部端子电极即阳极电极19。阳极电极19由与焊锡的粘结性良好的层叠金属膜形成。例如，作为层叠金属膜，使用表现为下层/中间层/上层的、V/Ni/Au、Ti/Ni/Au、V/Ni/Ag等的、以Ni为主体的金属膜。或者，也可以取代Ni，也可以是使用了Fe或Co的层叠金属膜。
在绝缘膜16上以延长到覆盖最初的护圈层14的位置的方式形成阳极电极19的一部分，该延伸部分成为与阳极同电位的场极板19a。
在元件芯片底面上形成N+型阴极层13，在其面上形成有阴极电极20。阴极电极20也如前所述地与导体框架焊接，因此由与阳极电极19同样的层叠金属膜来形成。
在基极层11的覆盖第二、第三个护圈层14的范围的上部，形成有埋入绝缘膜16中的、具有多晶硅膜的场极板17。在绝缘膜16的内部，与场极板17同时埋入等电位环电极(EQPR电极)18，该等电位环电极18使用相同的多晶硅膜，一端与n+型截断层15接触。
在图1和图2中示出了仅配置了一个电性悬浮的场极板107的例子，但在耐高压用途的半导体元件的情况下，配置大于等于4个护圈层14，与之对应地并列大于等于2个场极板。
场极板17和成为EQPR电极18的多晶硅膜是在形成膜的同时、或形成膜后掺杂了P、B、As等杂质的电阻膜，其厚度可以在10nm～3000nm的范围内适当选择。
参照图3至图5，说明在元件芯片上面形成场极板17和阳极电极19的工序如下。利用选择性的杂质掺杂，在元件芯片1的上面形成阳极扩散层12和环绕它的护圈层14。在护圈层14的外侧即芯片外周部形成N+型截断层15。可以适当选择这些扩散层形成工序顺序。
在这样地形成了扩散层的元件芯片1的上面，如图3所示地利用热氧化形成硅氧化膜16a。接着，在利用RIE(Reactive Ion Etching即，反应离子刻蚀)在氧化膜16a上形成与N+型阻挡层15相对的接触孔后，利用CVD(ChemicalVapor Deposition即，化学气相沉积)法沉积多晶硅膜，并将其利用RIE来构图，形成EQPR电极18和场极板17。再有，在上述的接触孔开孔和构图中使用的刻蚀方法不限于RIF，也可以是CDE(Chemical Dry Etching即，化学干法刻蚀)和湿法刻蚀。多晶硅膜掺杂了P、As、B等杂质，但也可以利用膜形成后的离子注入或者与形成膜同时进行杂质的掺杂。
之后，如图4所示，利用CVD法沉积硅氧化膜16b。接着，如图5所示，在阳极层12上开设接触孔，形成阳极电极19。阳极电极19如前所述，是与焊锡的粘结性良好的V/Ni/Au等的层叠金属膜。
通过以上工序，在氧化膜16(16a、16b)内埋入场极板17和电极18，就得到阳极电极19露出的元件表面状态。为了不损坏阳极电极19与焊锡的粘结性，之后不进行钝化膜的形成。然后，如图2所示，利用焊锡材料接合阳极电极19与上侧导体框架2之间。
图2中用虚线示出了在对二极管施加了反向偏压时伸到N型基极层11内的耗尽层。如图所示，耗尽层因护圈层14、场极板19a及17的作用而横向延伸，由此缓冲电场集中。在施加该反向偏压时，场极板17成为阳极/阴极间电压的中间电位，它起到帮助耗尽层沿着护圈层14横向延伸的作用。
沟道截断层15具有防止耗尽层在芯片侧面终止而在此形成没用的沟道的情况的作用。此外，一端与该截断层15连接的EQPR电极18具有延长部(MOS结构部)，该延长部隔着绝缘膜16(下部氧化膜16a)，同与N型基极层11的阻挡层15邻接的部分相对置。这样，EQPR电极18具有施加反向偏压时控制N型基极层11的表面电位，并缓冲从阳极层12横向延伸的耗尽层顶端部的电场的作用。
根据本实施方式，由于场极板17和EQPR电极18被埋入氧化膜16中，因此，即使在阳极电极侧的焊接时焊锡飞散，也不会发生如图12中说明的、场极板和阳极电极短路的事故。在元件芯片表面上没有附着焊锡的金属，由氧化膜16隔离。
此外，不形成钝化膜，但由于场极板17和截断电极18被埋设在氧化膜16内，因此，也不产生它们之间的火花。
另外，与图12的情况不同，由于在氧化膜16上没有因金属电极产生的凹凸而很平整，因此，树脂塑封时树脂容易进入导体框架2和元件芯片1间的空间。组装之后，若导体框架与元件之间剩余树脂未填充空间，就成为施加高电压时产生火花的原因。根据本实施方式，防止产生这样的火花和因此引起的绝缘破坏、特性劣化和可靠性劣化等。
另外，由于本实施方式是焊接方式，因此，与引线接合方式相比，可以实现产品的薄型化。此外，由于上侧导体框架能够发挥比引线接合优良的导热作用，因此，元件散热性也比引线接合方式优良，有利于大电流规格的半导体元件。
本发明不限于上述实施方式。例如，图9示出了将上侧导体框架2的芯片接合部分分为2条的例子。此外，在实施方式中示出了整流二极管的例子，但本发明也可以同样地适用于耐高压用的双极型晶体管和MOS晶体管及包括它们的IC。例如，在晶体管的情况下，如图10所示，准备两个上侧导体框架2a、2b，将它们与配置在芯片上面的发射极电极和基极电极连接。

Claims (17)

1.一种半导体装置，具有半导体元件芯片、和利用焊锡材料分别接合了上述半导体元件芯片的上下端子电极的上下导体框架，其特征在于，
上述半导体元件芯片具有：
第一导电型的半导体层；
在上述半导体层上选择性地形成的第二导电型扩散层；
在上述半导体层的上述第二导电型扩散层的外侧形成的第二导电型的多个护圈层；
形成在上述半导体层上的绝缘膜；以及
埋设在上述绝缘膜中的、由多晶硅膜形成的场极板。
2.如权利要求1所述的半导体装置，其特征在于，
上述场极板由在成膜时或成膜后掺杂了杂质的多晶硅膜形成。
3.如权利要求1所述的半导体装置，其特征在于，
上述半导体元件芯片还具有：
在芯片外周部的上述半导体层上形成的第一导电型的沟道截断层；和
等电位电极，被埋入上述绝缘膜中并由与上述场极板相同的多晶硅膜形成，与上述沟道截断层接触并且在与上述半导体层的上述沟道截断层邻接的部分的上部延长。
4.如权利要求1所述的半导体装置，其特征在于，
上述半导体元件芯片的上部端子电极与上述第二导电型扩散层接触，由从Ni、Fe、Co中选择的一个作为主体的层叠金属膜形成。
5.如权利要求4所述的半导体装置，其特征在于，
上述上部端子电极其一部分在上述绝缘膜上以覆盖接近上述第二导电型扩散层的护圈层的方式延长，来构成场极板。
6.如权利要求1所述的半导体装置，其特征在于，
上述绝缘膜由2层硅氧化膜形成，
上述场极板由夹在该2层硅氧化膜之间的多晶硅膜形成。
7.如权利要求1所述的半导体装置，其特征在于，
具有密封上述半导体元件芯片和上下导体框架的塑封树脂。
8.如权利要求1所述的半导体装置，其特征在于，
上述半导体元件芯片是PN结二极管芯片，该PN结二极管芯片将有选择地形成在上述半导体层的上面的上述第二导电型扩散层作为阳极层，在上述半导体层的底面上形成有第一导电型阴极层。
9.一种半导体装置，具有平面型二极管、利用焊锡材料将上述平面型二极管的上下端子电极分别接合的上下导体框架、以及密封这些二极管和上下导体框架的塑封树脂，其特征在于，
上述二极管具有：
第一导电型的基极半导体层；
在上述基极半导体层的上面有选择地形成的第二导电型的第一端子扩散层；
在上述基极半导体层的底面上形成的第一导电型的第二端子扩散层；
在上述基极半导体层的上述第一端子扩散层的外侧形成的第二导电型的多个护圈层；
在上述基极半导体层的上面覆盖上述护圈层而形成的绝缘膜；以及
埋设在上述绝缘膜中的、由掺杂质多晶硅膜形成的场极板。
10.如权利要求9所述的半导体装置，其特征在于，
上述二极管还具有：
在芯片外周部的上述基极半导体层上面形成的第一导电型的沟道截断层；和
等电位电极，被埋入上述绝缘膜中并由与上述场极板相同的多晶硅膜形成，与上述沟道截断层接触并且在与上述基极半导体层的上述沟道截断层邻接的部分的上部延长。
11.如权利要求9所述的半导体装置，其特征在于，
上述二极管的上部端子电极与上述第一端子扩散层接触，由以Ni、Fe、Co中的至少一个为主体的层叠金属膜形成。
12.如权利要求11所述的半导体装置，其特征在于，
上述上部端子电极其一部分在上述绝缘膜上以覆盖与上述第一端子扩散层接近的护圈层的方式延长，来构成场极板。
13.如权利要求9所述的半导体装置，其特征在于，
上述绝缘膜由2层硅氧化膜形成，
上述场极板由夹在该2层硅氧化膜之间的掺杂质多晶硅膜形成。
14.一种平面型半导体装置的制造方法，其特征在于，具有：
在第一导电型的基极半导体层的上面有选择地形成第二导电型的端子扩散层、和环绕它的第二导电型的多个护圈层的工序；
在上述基极半导体层上形成第一硅氧化膜的工序；
通过掺杂质多晶硅膜的沉积和构图，在上述第一硅氧化膜上形成场极板的工序；
形成覆盖上述场极板的第二硅氧化膜的工序；
在上述第一和第二硅氧化膜上形成接触孔的工序；以及
形成上部端子电极的工序，该上部端子电极通过上述接触孔与上述端子扩散层接触，并具有以Ni、Fe、Co中的至少一个为主体的层叠金属膜。
15.如权利要求14所述的制造方法，其特征在于，具有：
在上述基极半导体层的上述护圈层的外侧形成第一导电型的沟道截断层的工序；以及
使用上述多晶硅膜与上述场极板同时形成电极的工序，该电极与上述沟道截断层接触，并且在与沟道截断层邻接的基极半导体层上部延长。
16.如权利要求14所述的制造方法，其特征在于，
上述上部端子电极被构图为，在最接近上述端子扩散层的护圈层的上部延长而构成场极板。
17.如权利要求14所述的制造方法，其特征在于，具有：
在形成上述上部端子电极后不进行钝化工序，而利用焊锡材料将上述半导体装置的上下面与上下导体框架接合的工序；和
将上述半导体装置和上下导体框架树脂密封的工序。
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