JP5376365B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5376365B2 JP5376365B2 JP2009099997A JP2009099997A JP5376365B2 JP 5376365 B2 JP5376365 B2 JP 5376365B2 JP 2009099997 A JP2009099997 A JP 2009099997A JP 2009099997 A JP2009099997 A JP 2009099997A JP 5376365 B2 JP5376365 B2 JP 5376365B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 27
- 239000003990 capacitor Substances 0.000 description 23
- 230000005684 electric field Effects 0.000 description 21
- 239000011229 interlayer Substances 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Manufacturing & Machinery (AREA)
Description
(実施の形態1)
最初に、本発明の実施の形態1の半導体装置の構成について説明する。
本実施の形態の半導体装置20では、キャパシタC1によってガードリング電極7eとフィールドプレート9aとが容量結合している。キャパシタC4によってフィールドプレート9bとチャネルストッパ電極7fとが容量結合している。キャパシタC2によってフィールドプレート9aとフィールドプレート10とが容量結合している。キャパシタC3によってフィールドプレート9bとフィールドプレート10とが容量結合している。
界のピークが発生する。しかし、フィールドプレート9a,9b,10によって、最外周のガードリング2eに付随するガードリング電極7eの直下での電界集中が緩和され、半導体基板1の表面電位が安定する。
図7を参照して、比較例の半導体装置は、本実施の形態と比較して、フィールドプレート9a,9b,10が形成されていない点で主に異なっている。この比較例の半導体装置20では、最外周のガードリング2eに付随するガードリング電極7eの直下の点Xで電界のピークが最大となる。
本発明の実施の形態2の半導体装置は、実施の形態1の半導体装置と比較して、フィールドプレートの構成が主に異なっている。
している。
本発明の実施の形態3の半導体装置は、実施の形態1の半導体装置と比較して、フィールドプレートの構成が主に異なっている。
であり、フィールドプレート9a,9bとフィールドプレート9cとを1層で形成することが可能である。
本発明の実施の形態4の半導体装置は、実施の形態1の半導体装置と比較して、フィールドプレートの構成が主に異なっている。
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。
Claims (6)
- 主表面を有し、前記主表面に素子形成領域を有する半導体基板と、
平面視において前記素子形成領域の周囲を取り囲むように前記半導体基板の前記主表面に形成されたガードリングと、
前記半導体基板の前記主表面上に形成され、かつ前記ガードリングに電気的に接続されたガードリング電極と、
平面視において前記ガードリングの外周側に位置するように前記半導体基板の前記主表面に形成されたチャネルストッパ領域と、
前記半導体基板の前記主表面上に形成され、かつ前記チャネルストッパ領域に電気的に接続されたチャネルストッパ電極と、
前記半導体基板上に絶縁状態で配置され、フローティング電位であり、前記ガードリング電極と容量結合しており、かつ前記チャネルストッパ電極と容量結合しているフィールドプレートとを備え、
前記フィールドプレートは、前記半導体基板の前記主表面と前記ガードリング電極との間に位置する第1の部分と、前記半導体基板の前記主表面と前記チャネルストッパ電極との間に位置する第2の部分とを含み、
前記第1の部分は、平面視において前記ガードリング電極と重なり合う部分を有し、
前記第2の部分は、平面視において前記チャネルストッパ電極と重なり合う部分を有している、半導体装置。 - 前記フィールドプレートは、前記第1の部分および前記第2の部分以外の第3の部分を含み、
前記第3の部分は、平面視において前記第1の部分および前記第2の部分の少なくともいずれかと重なり合う部分を有している、請求項1に記載の半導体装置。 - 前記フィールドプレートの前記第3の部分は、前記ガードリング電極および前記チャネルストッパ電極と同一の層に属している、請求項2に記載の半導体装置。
- 前記フィールドプレートの前記第3の部分は、前記ガードリング電極および前記チャネルストッパ電極より下層に形成されている、請求項2に記載の半導体装置。
- 前記フィールドプレートは、前記第1の部分および前記第2の部分以外の第3の部分を含み、
前記第1の部分、前記第2の部分および前記第3の部分は、前記主表面の延びる方向に沿って並んでいる、請求項1に記載の半導体装置。 - 前記フィールドプレートは、下層電極と、前記下層電極上に接して配置された上層埋め込み電極とを含んでいる、請求項5に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009099997A JP5376365B2 (ja) | 2009-04-16 | 2009-04-16 | 半導体装置 |
US12/651,055 US9236436B2 (en) | 2009-04-16 | 2009-12-31 | Semiconductor device |
KR1020100021139A KR101121045B1 (ko) | 2009-04-16 | 2010-03-10 | 반도체장치 |
DE102010011259.3A DE102010011259B4 (de) | 2009-04-16 | 2010-03-12 | Halbleitervorrichtung |
CN2010101500942A CN101866946B (zh) | 2009-04-16 | 2010-03-15 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009099997A JP5376365B2 (ja) | 2009-04-16 | 2009-04-16 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010251553A JP2010251553A (ja) | 2010-11-04 |
JP5376365B2 true JP5376365B2 (ja) | 2013-12-25 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2009099997A Expired - Fee Related JP5376365B2 (ja) | 2009-04-16 | 2009-04-16 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9236436B2 (ja) |
JP (1) | JP5376365B2 (ja) |
KR (1) | KR101121045B1 (ja) |
CN (1) | CN101866946B (ja) |
DE (1) | DE102010011259B4 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5716591B2 (ja) * | 2011-07-26 | 2015-05-13 | 三菱電機株式会社 | 半導体装置 |
CN103703565B (zh) * | 2011-09-28 | 2017-09-01 | 三菱电机株式会社 | 半导体装置 |
JP5640969B2 (ja) * | 2011-12-26 | 2014-12-17 | 三菱電機株式会社 | 半導体素子 |
US9385188B2 (en) | 2012-01-12 | 2016-07-05 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device with termination region having floating electrodes in an insulating layer |
US9818742B2 (en) * | 2012-05-11 | 2017-11-14 | Polar Semiconductor, Llc | Semiconductor device isolation using an aligned diffusion and polysilicon field plate |
CN102723278B (zh) * | 2012-06-26 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | 半导体结构形成方法 |
WO2014084124A1 (ja) * | 2012-11-29 | 2014-06-05 | 富士電機株式会社 | 半導体装置 |
JP2014204038A (ja) * | 2013-04-08 | 2014-10-27 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP6129117B2 (ja) * | 2013-05-29 | 2017-05-17 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP2014236124A (ja) * | 2013-06-03 | 2014-12-15 | 三菱電機株式会社 | 半導体装置、半導体装置の検査方法 |
JP6231778B2 (ja) * | 2013-06-05 | 2017-11-15 | キヤノン株式会社 | 電気デバイスおよび放射線検査装置 |
DE102014005879B4 (de) * | 2014-04-16 | 2021-12-16 | Infineon Technologies Ag | Vertikale Halbleitervorrichtung |
CN111106168B (zh) * | 2018-10-26 | 2022-07-01 | 珠海零边界集成电路有限公司 | 半导体器件的终端耐压结构、半导体器件及其制造方法 |
CN111554677B (zh) * | 2020-05-06 | 2024-02-27 | 四川立泰电子有限公司 | 电磁干扰低的功率器件终端结构 |
Family Cites Families (17)
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JP2634929B2 (ja) * | 1990-06-14 | 1997-07-30 | 三菱電機株式会社 | シリコンプレーナ型半導体装置 |
JP2739004B2 (ja) | 1992-01-16 | 1998-04-08 | 三菱電機株式会社 | 半導体装置 |
JP3217488B2 (ja) | 1992-08-28 | 2001-10-09 | 株式会社リコー | 高耐圧半導体装置 |
JP3397356B2 (ja) * | 1993-02-05 | 2003-04-14 | 株式会社東芝 | 半導体装置 |
JP3591301B2 (ja) | 1998-05-07 | 2004-11-17 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
JP2000269520A (ja) | 1999-03-15 | 2000-09-29 | Toshiba Corp | 高耐圧型半導体装置 |
JP4357753B2 (ja) * | 2001-01-26 | 2009-11-04 | 株式会社東芝 | 高耐圧半導体装置 |
KR100535062B1 (ko) * | 2001-06-04 | 2005-12-07 | 마츠시타 덴끼 산교 가부시키가이샤 | 고내압 반도체장치 |
JP2003347547A (ja) | 2002-05-27 | 2003-12-05 | Mitsubishi Electric Corp | 電力用半導体装置及びその製造方法 |
JP2005005443A (ja) * | 2003-06-11 | 2005-01-06 | Toshiba Corp | 高耐圧半導体装置 |
JP4269863B2 (ja) | 2003-09-25 | 2009-05-27 | 富士電機デバイステクノロジー株式会社 | 双方向高耐圧プレーナ型半導体装置 |
JP4731816B2 (ja) | 2004-01-26 | 2011-07-27 | 三菱電機株式会社 | 半導体装置 |
JP2006173437A (ja) | 2004-12-17 | 2006-06-29 | Toshiba Corp | 半導体装置 |
US20070029573A1 (en) | 2005-08-08 | 2007-02-08 | Lin Cheng | Vertical-channel junction field-effect transistors having buried gates and methods of making |
JP4935192B2 (ja) * | 2006-05-31 | 2012-05-23 | 三菱電機株式会社 | 半導体装置 |
JP2008187125A (ja) | 2007-01-31 | 2008-08-14 | Toshiba Corp | 半導体装置 |
JP2009004681A (ja) | 2007-06-25 | 2009-01-08 | Toshiba Corp | 半導体装置 |
-
2009
- 2009-04-16 JP JP2009099997A patent/JP5376365B2/ja not_active Expired - Fee Related
- 2009-12-31 US US12/651,055 patent/US9236436B2/en active Active
-
2010
- 2010-03-10 KR KR1020100021139A patent/KR101121045B1/ko active IP Right Grant
- 2010-03-12 DE DE102010011259.3A patent/DE102010011259B4/de active Active
- 2010-03-15 CN CN2010101500942A patent/CN101866946B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE102010011259A1 (de) | 2010-10-28 |
KR20100114820A (ko) | 2010-10-26 |
KR101121045B1 (ko) | 2012-03-20 |
CN101866946A (zh) | 2010-10-20 |
JP2010251553A (ja) | 2010-11-04 |
CN101866946B (zh) | 2013-06-05 |
US20100264507A1 (en) | 2010-10-21 |
US9236436B2 (en) | 2016-01-12 |
DE102010011259B4 (de) | 2015-05-28 |
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