JP5716591B2 - 半導体装置 - Google Patents
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- JP5716591B2 JP5716591B2 JP2011163420A JP2011163420A JP5716591B2 JP 5716591 B2 JP5716591 B2 JP 5716591B2 JP 2011163420 A JP2011163420 A JP 2011163420A JP 2011163420 A JP2011163420 A JP 2011163420A JP 5716591 B2 JP5716591 B2 JP 5716591B2
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- 239000004065 semiconductor Substances 0.000 title claims description 157
- 239000000758 substrate Substances 0.000 claims description 69
- 238000009792 diffusion process Methods 0.000 claims description 17
- 230000000087 stabilizing effect Effects 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 21
- 239000012535 impurity Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Description
本願の発明に係る他の半導体装置は、第1導電型の半導体基板と、該半導体基板に形成された半導体素子と、該半導体基板の主面に該半導体素子を囲むように形成されたトレンチ溝の内壁に沿って、第2導電型の拡散層で形成された溝内ガードリングと、該半導体基板の主面に該半導体素子を囲むように形成されたガードリングと、を備えたことを特徴とする。
図1は、本発明の実施の形態1に係る半導体装置の平面図である。本発明の実施の形態1に係る半導体装置10の中央部分には、導電膜12が形成されている。また、導電膜12を囲むように絶縁膜14が形成されている。
図8は、本発明の実施の形態2に係る半導体装置の断面図である。図8は前述の図2に対応する図である。本発明の実施の形態2に係る半導体装置は、前述の半導体装置10との相違点を中心に説明する。
図12は、本発明の実施の形態3に係る半導体装置の断面図である。図12は前述の図8に対応する図である。本発明の実施の形態3に係る半導体装置は、本発明の実施の形態2に係る半導体装置との相違点を中心に説明する。
Claims (8)
- 第1導電型の半導体基板と、
前記半導体基板に形成された半導体素子と、
前記半導体基板に、前記半導体素子を囲むように、第2導電型の拡散層で形成されたガードリングと、
前記半導体基板に、前記ガードリングを囲むように、前記半導体基板の主面より一段低く形成された低地部分と、
前記低地部分の内壁に沿って第1導電型の拡散層で形成されたチャネルストッパと、
を備えたことを特徴とする半導体装置。 - 前記半導体基板の主面に前記半導体素子を囲むように形成されたトレンチ溝の内壁に沿って、第2導電型の拡散層で形成された溝内ガードリングを備えたことを特徴とする請求項1に記載の半導体装置。
- 第1導電型の半導体基板と、
前記半導体基板に形成された半導体素子と、
前記半導体基板の主面に前記半導体素子を囲むように形成された複数のトレンチ溝の内壁に沿って、第2導電型の拡散層で形成された複数の溝内ガードリングと、
前記複数のトレンチ溝の少なくとも1つを埋めるように形成された第2導電型の導電膜と、
前記複数のトレンチ溝の少なくとも1つを埋めるように形成された絶縁膜と、
前記絶縁膜の主面の上方に前記半導体素子を囲むように形成されたフローティングフィールドプレートと、
を備えたことを特徴とする半導体装置。 - 前記導電膜の上方に、前記導電膜と接続された第2導電型の電位安定化導電膜を備えたことを特徴とする請求項3に記載の半導体装置。
- 前記半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。
- 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、又はダイヤモンドであることを特徴とする請求項5に記載の半導体装置。
- 前記半導体基板の主面に形成された第2導電型のアノードを備え、
前記溝内ガードリングは前記アノードよりも前記半導体基板の深い位置まで及んでいることを特徴とする請求項2、3、4のいずれか1項に記載の半導体装置。 - 第1導電型の半導体基板と、
前記半導体基板に形成された半導体素子と、
前記半導体基板の主面に前記半導体素子を囲むように形成されたトレンチ溝の内壁に沿って、第2導電型の拡散層で形成された溝内ガードリングと、
前記半導体基板の主面に前記半導体素子を囲むように形成されたガードリングと、を備えたことを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011163420A JP5716591B2 (ja) | 2011-07-26 | 2011-07-26 | 半導体装置 |
DE201210212515 DE102012212515A1 (de) | 2011-07-26 | 2012-07-17 | Halbleitervorrichtung |
CN201210259128.0A CN102903760B (zh) | 2011-07-26 | 2012-07-25 | 半导体装置 |
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JP2011163420A JP5716591B2 (ja) | 2011-07-26 | 2011-07-26 | 半導体装置 |
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JP2013030501A JP2013030501A (ja) | 2013-02-07 |
JP5716591B2 true JP5716591B2 (ja) | 2015-05-13 |
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JP2011163420A Active JP5716591B2 (ja) | 2011-07-26 | 2011-07-26 | 半導体装置 |
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JP (1) | JP5716591B2 (ja) |
CN (1) | CN102903760B (ja) |
DE (1) | DE102012212515A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11600692B2 (en) | 2020-09-18 | 2023-03-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
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JP6047429B2 (ja) * | 2013-03-08 | 2016-12-21 | 株式会社 日立パワーデバイス | 半導体装置およびそれを用いた電力変換装置 |
JP2015019014A (ja) * | 2013-07-12 | 2015-01-29 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
CN104810384A (zh) * | 2014-01-29 | 2015-07-29 | 北大方正集团有限公司 | 功率半导体器件及制造方法和截止环 |
CN104810385A (zh) * | 2014-01-29 | 2015-07-29 | 北大方正集团有限公司 | 功率半导体器件及制造方法和截止环 |
US20200279947A1 (en) * | 2017-11-13 | 2020-09-03 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device |
JP6681935B2 (ja) * | 2018-04-16 | 2020-04-15 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
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JPH01272152A (ja) * | 1988-04-25 | 1989-10-31 | Matsushita Electric Works Ltd | ガードリングを有する半導体素子 |
JP4049971B2 (ja) * | 2000-06-15 | 2008-02-20 | 株式会社三社電機製作所 | 半導体素子、半導体素子の製造方法 |
DE10316222B3 (de) * | 2003-04-09 | 2005-01-20 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Verfahren zur Herstellung eines robusten Halbleiterbauelements und damit hergestelltes Halbleiterbauelement |
JP2005183891A (ja) | 2003-12-19 | 2005-07-07 | Success International Kk | 双方向ブロック型プレーナデバイスの構造と製法 |
JP4731816B2 (ja) * | 2004-01-26 | 2011-07-27 | 三菱電機株式会社 | 半導体装置 |
KR100748342B1 (ko) * | 2005-09-14 | 2007-08-09 | 매그나칩 반도체 유한회사 | 씨모스 이미지 센서의 제조방법 |
JP4935192B2 (ja) * | 2006-05-31 | 2012-05-23 | 三菱電機株式会社 | 半導体装置 |
JP5376365B2 (ja) * | 2009-04-16 | 2013-12-25 | 三菱電機株式会社 | 半導体装置 |
JP5574639B2 (ja) * | 2009-08-21 | 2014-08-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5748188B2 (ja) * | 2009-09-29 | 2015-07-15 | 富士電機株式会社 | 半導体装置 |
CN201611658U (zh) * | 2010-01-08 | 2010-10-20 | 无锡新洁能功率半导体有限公司 | 一种深沟槽功率mos器件 |
JP2011163420A (ja) | 2010-02-08 | 2011-08-25 | Mitsubishi Heavy Ind Ltd | 軸受構造、及び、ダイレクトドライブ型風力発電装置 |
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- 2012-07-17 DE DE201210212515 patent/DE102012212515A1/de active Pending
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Cited By (1)
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US11600692B2 (en) | 2020-09-18 | 2023-03-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
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JP2013030501A (ja) | 2013-02-07 |
CN102903760A (zh) | 2013-01-30 |
CN102903760B (zh) | 2015-06-03 |
DE102012212515A1 (de) | 2013-01-31 |
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