CN102903760B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN102903760B
CN102903760B CN201210259128.0A CN201210259128A CN102903760B CN 102903760 B CN102903760 B CN 102903760B CN 201210259128 A CN201210259128 A CN 201210259128A CN 102903760 B CN102903760 B CN 102903760B
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semiconductor substrate
semiconductor device
groove
guard ring
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CN102903760A (zh
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星子高广
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Rohm Co Ltd
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于提供一种能够提高半导体装置的耐压以及耐压稳定性的半导体装置。本发明的半导体装置的特征在于,具备:第一导电型的半导体衬底;半导体元件,形成于该半导体衬底;保护环,在该半导体衬底上以包围该半导体元件的方式由第二导电型的扩散层形成;低洼部分,在该半导体衬底上以包围该保护环的方式形成得比该半导体衬底的主面低;沟道停止层,沿着该低洼部分的内壁由第一导电型的扩散层形成。

Description

半导体装置
技术领域
本发明涉及在例如大电流的开关等中使用的半导体装置。
背景技术
在专利文献1中公开了在半导体衬底上形成有保护环和沟道停止层(channel stopper)的半导体装置。保护环和沟道停止层是为了提高半导体装置的耐压而形成的。
专利文献
专利文献1:日本特开2005-183891号公报。
在专利文献1所公开的半导体装置中不能够充分地提高耐压以及耐压稳定性。
发明内容
本发明是为了解决上述那样的课题而提出的,其目的在于提供一种能够提高半导体装置的耐压以及耐压稳定性的半导体装置。
本发明提供一种半导体装置,其特征在于,具备:第一导电型的半导体衬底;半导体元件,形成于该半导体衬底;保护环,在该半导体衬底上以包围该半导体元件的方式由第二导电型的扩散层形成;低洼部分,在该半导体衬底上以包围该保护环的方式形成得比该半导体衬底的主面低;沟道停止层,沿着该低洼部分的内壁由第一导电型的扩散层形成。
本发明的另一半导体装置的特征在于,具备:第一导电型的半导体衬底;半导体元件,形成于该半导体衬底;槽内保护环,沿着在该半导体衬底的主面以包围该半导体元件的方式形成的沟槽的内壁由第二导电型的扩散层形成;第二导电型的导电膜,以填埋该沟槽的方式形成;浮置场板(floating field plate),在该半导体衬底的主面的上方以包围该半导体元件的方式形成。
根据本发明,由于将沟道停止层或保护环以到达衬底的较深的位置的方式形成,所以,能够提高半导体装置的耐压以及耐压稳定性。
附图说明
图1是本发明的实施方式1的半导体装置的平面图。
图2是图1的2-2虚线的剖面图。
图3是表示阳极和保护环形成前的状态的剖面图。
图4是表示形成了阳极和保护环的剖面图。
图5是表示低洼部分形成前的状态的剖面图。
图6是表示形成了低洼部分的剖面图。
图7是表示形成了沟道停止层的剖面图。
图8是本发明的实施方式2的半导体装置的剖面图。
图9是表示形成了沟槽的剖面图。
图10是表示形成了阳极、保护环以及槽内保护环的剖面图。
图11是表示形成了沟道停止层的剖面图。
图12是本发明的实施方式3的半导体装置的剖面图。
图13是表示形成了阳极和槽内保护环的剖面图。
图14是表示用绝缘膜埋入了沟槽的剖面图。
图15是表示用导电膜埋入了沟槽的剖面图。
图16是表示形成了沟道停止层的剖面图。
图17是表示形成了绝缘膜的剖面图。
具体实施方式
实施方式1
图1是本发明的实施方式1的半导体装置的平面图。在本发明的实施方式1的半导体装置10的中央部分形成有导电膜12。此外,以包围导电膜12的方式形成有绝缘膜14。
图2是图1的2-2虚线的剖面图。半导体装置10具备N型(以下,称为第一导电型)的半导体衬底20。在半导体衬底20上形成有P型(以下,称为第二导电型)的阳极22。该阳极22起到二极管的阳极的作用。在阳极22的外侧形成有保护环24。保护环24以包围二极管的方式形成于半导体衬底20的主面。保护环24由第二导电层的扩散层形成。
在半导体衬底20上以包围保护环24的方式形成有低洼部分26。低洼部分26是以比半导体衬底20的主面低的方式形成的部分。沿着该低洼部分26的内壁形成有沟道停止层28。沟道停止层28由第一导电型的扩散层形成。
半导体装置10具备:形成有二极管的元件区域40;形成有保护环24的保护环区域42;形成有沟道停止层28的沟道停止层区域44。在保护环区域42以及沟道停止层28、元件区域40的一部分形成有绝缘膜30。绝缘膜30一体形成。导电膜12形成在阳极22之上。此外,导电膜12的一部分也形成在绝缘膜30的一部分之上。绝缘膜14形成在绝缘膜30之上。此外,绝缘膜14的一部分也形成在导电膜12的一部分之上。并且,图2中的虚线示出半导体衬底20内的耗尽层的延伸方式。
以下,对本发明的实施方式1的半导体装置的制造方法进行说明。首先,形成用于形成阳极和保护环的图案。图3是表示阳极和保护环形成前的状态的剖面图。以使形成保护环的部分以及形成阳极的部分开口的方式形成绝缘膜50。
接着,形成阳极和保护环。图4是表示形成了阳极和保护环的剖面图。首先,利用离子注入法,将绝缘膜50作为掩模向半导体衬底20注入第二导电型的杂质。之后,使该杂质热扩散,形成阳极22和保护环24。而且,在进入到下一处理之前将绝缘膜50除去。
接着,形成低洼部分。图5是表示低洼部分形成前的状态的剖面图。在半导体衬底20上形成绝缘膜52。以使半导体衬底20的外周部开口的方式对绝缘膜52进行构图。
接着,将绝缘膜52作为掩模对半导体衬底20的外周部进行刻蚀,形成低洼部分26。图6是表示形成了低洼部分的剖面图。
接着,形成沟道停止层。图7是表示形成了沟道停止层的剖面图。首先,将绝缘膜52作为掩模利用离子注入法向低洼部分26注入第一导电型的杂质。以第一导电型的杂质密度比半导体衬底20高的方式向低洼部分26注入杂质。之后,使该杂质热扩散,以沿着低洼部分26的内壁的方式形成沟道停止层28。而且,在进入到下一处理之前将绝缘膜52除去。接着,依次形成绝缘膜30、导电膜12以及绝缘膜14,从而完成图1的半导体装置。
但是,若对阳极施加反向电压,则在半导体衬底中形成耗尽层,电场集中,所以,存在半导体装置劣化的情况。为了防止半导体装置的劣化,需要提高半导体装置的耐压以及耐压稳定性(例如,耐压的时间变动的稳定性)。为了提高耐压以及耐压稳定性,需要将成为保护环或沟道停止层的杂质在衬底的纵向较深地扩散而形成。但是,为了使杂质在衬底的纵向较深地扩散,必须在高温下进行长时间的杂质扩散,使生产率降低。进而,若长时间地使杂质扩散,则杂质也在横向广泛地扩散,难以实现半导体装置的尺寸的缩小。
但是,根据本发明的实施方式1的半导体装置10,预先形成比半导体衬底20的主面低的低洼部分26,以沿着低洼部分26的内壁的方式形成沟道停止层28。因此,将沟道停止层28形成至半导体衬底20的深处,能够提高半导体装置的耐压以及耐压稳定性。此外,由于不需要使杂质长时间扩散,所以,能够抑制杂质的横向的扩散,能够缩小半导体装置的尺寸。具体地说,能够缩小参照图2说明了的保护环区域42和沟道停止层区域44的尺寸。
如果低洼部分26形成得比半导体衬底20的主面低,则能够得到上述的效果。因此,低洼部分26不限定于上述的形状,例如以槽形成也可以。
在本发明的实施方式1的半导体装置10中,在元件区域40形成了二极管,但是,形成例如IGBT或功率MOSFET等半导体元件也可以。此外,在本发明的实施方式1的半导体装置10中,将N型作为第一导电型,将P型作为第二导电型。但是,使它们的导电型反转,将N型作为第二导电型并且将P型作为第一导电型也可以。
为了防止由于离子注入导致对半导体衬底造成损伤,也可以在离子注入之前在半导体衬底的表面形成薄的绝缘膜。此外,也可以利用离子注入以外的方法形成扩散层。
通常半导体衬底20由硅形成。但是,由带隙比硅大的宽带隙半导体形成半导体衬底20也可以。作为宽带隙半导体,例如有碳化硅、氮化镓类材料、金刚石。
实施方式2
图8是本发明的实施方式2的半导体装置的剖面图。图8是与上述的图2对应的图。以与上述的半导体装置10的不同点为中心对本发明的实施方式2的半导体装置进行说明。
本发明的实施方式2的半导体装置具备沟槽60。沟槽60以包围半导体元件(二极管)的方式形成于半导体衬底20的主面。沟槽60被绝缘膜30填埋。此外,沿着沟槽60的内壁形成有槽内保护环62。槽内保护环62由第二导电型的扩散层形成。该槽内保护环62从半导体衬底20的主面起达到比阳极22深的位置。其它结构与本发明的实施方式1的半导体装置相同。
以下,对本发明的实施方式2的半导体装置的制造方法进行说明。图9是表示形成了沟槽的剖面图。首先,在半导体衬底20上以具有开口部的方式形成构图后的绝缘膜70。接着,对利用该开口部而露出的半导体衬底20进行刻蚀,形成沟槽60。而且,在进入到下一处理之前将绝缘膜70除去。
接着,形成阳极、保护环以及槽内保护环。图10是表示形成了阳极、保护环以及槽内保护环的剖面图。利用离子注入法,将构图后的绝缘膜72作为掩模向半导体衬底20注入第二导电型的杂质。之后,使该杂质热扩散,形成阳极22、保护环24、槽内保护环62。槽内保护环62沿着沟槽60的内壁形成。而且,在进入到下一处理之前将绝缘膜72除去。
接着,形成沟道停止层。图11是表示形成了沟道停止层的剖面图。首先,以具有开口部分的方式形成构图后的绝缘膜74。接着,对该开口部分进行刻蚀,形成低洼部分26。之后,如在实施方式1中所说明的那样,沿着低洼部分26的内壁形成沟道停止层28。而且,在进入到下一处理之前将绝缘膜74除去。
接着,以填埋沟槽的方式形成绝缘膜30。进而,依次形成导电膜12以及绝缘膜14,从而完成图8的半导体装置。
根据本发明的实施方式2的半导体装置10,由于槽内保护环62从半导体衬底20的主面起达到比阳极22深的位置,所以,耗尽层形成至半导体衬底20的深处。因此,能够提高半导体装置10的耐压以及耐压稳定性,并且,与上述的半导体装置10相比,能够缩小保护环区域。
此外,根据本发明的实施方式2的半导体装置,能够形成深度不同的两种保护环(保护环24和槽内保护环62)。因此,通过使沟槽60的深度以及槽内保护环62和保护环24的配置最佳化,从而能够调整在对阳极22施加了反向电压的情况下的耗尽层的延伸方式。因此,与本发明的实施方式1的半导体装置10相比,能够提高耐压以及耐压稳定性。
在本发明的实施方法2的半导体装置中,形成了保护环24和槽内保护环62,但是,也能够不形成保护环24。此外,本发明的实施方式2的半导体装置能够进行至少与本发明的实施方式1的半导体装置相同程度的变形。
实施方式3
图12是本发明的实施方式3的半导体装置的剖面图。图12是与上述的图8对应的图。以与本发明的实施方式2的半导体装置的不同点为中心对本发明的实施方式3的半导体装置进行说明。
本发明的实施方式3的半导体装置具备沟槽80。沟槽80以包围半导体元件(二极管)的方式形成于半导体衬底20的主面。沟槽80被第二导电型的导电膜82a填埋。沿着沟槽80的内壁形成有槽内保护环84。槽内保护环84由第二导电型的扩散层形成。在导电膜82a的上方连接有第二导电型的电位稳定化导电膜92。电位稳定化导电膜92是为了将导电膜82a引出到半导体衬底20的上方并且将各槽内保护环保持为相同电位而形成的。
沟槽60被绝缘膜86填埋。因此,本发明的实施方式3的半导体装置具备被导电膜82a填埋的沟槽80和被绝缘膜86填埋的沟槽60。在绝缘膜86之上形成有第二导电型的浮置场板82b。浮置场板82b以包围半导体元件(二极管)的方式形成在半导体衬底20的主面的上方。并且,沟道停止层28形成在半导体衬底20的主面。
以下,对本发明的实施方式3的半导体装置的制造方法进行说明。图13是表示形成了阳极和槽内保护环的剖面图。在以具有开口部的方式形成了构图后的绝缘膜100之后,形成沟槽60以及80。接着,利用离子注入法,将绝缘膜100作为掩模向半导体衬底20注入第二导电型的杂质。之后,使该杂质热扩散,形成阳极22、槽内保护环84以及槽内保护环62。而且,在进入到下一处理之前将绝缘膜100除去。
接着,用绝缘膜埋入沟槽60。图14是表示用绝缘膜埋入了沟槽的剖面图。沟槽60用绝缘膜102埋入。绝缘膜102以埋入沟槽60并且使沟槽80开口的方式形成在半导体衬底20的主面。
接着,用导电膜埋入沟槽80。图15是表示用导电膜埋入了沟槽的剖面图。沟槽80用第二导电型的导电膜82a埋入。导电膜82a也形成在绝缘膜102之上。在形成导电膜82a的同时,在绝缘膜102之上形成浮置场板82b。导电膜82a和浮置场板82b在同一工序中同时形成。
接着,形成沟道停止层。图16是表示形成了沟道停止层的剖面图。对上述的绝缘膜102的外周部分进行刻蚀,形成绝缘膜104。对利用绝缘膜104的开口而露出的半导体衬底20的表面离子注入第一导电型的杂质,实施热扩散,形成沟道停止层28。
接着,形成新的绝缘膜。图17是表示形成了绝缘膜的剖面图。首先,对绝缘膜104中的阳极22上的部分进行刻蚀,形成绝缘膜86。接着,以覆盖浮置场板82b并且使导电膜82a的一部分露出的方式形成绝缘膜90。
接着,以与从绝缘膜90露出的导电膜82a连接的方式形成第二导电型的电位稳定化导电膜92。接着,依次形成导电膜12以及绝缘膜14,从而完成图12的半导体装置。
根据本发明的第三实施方式的半导体装置,能够提高半导体装置的耐压以及耐压稳定性,并且,能够通过用导电膜82a埋入沟槽80而缓和针对半导体衬底20的机械性的应力。因此,能够使半导体装置的泄漏特性提高。此外,由于导电膜82a利用电位稳定化导电膜92连接于半导体衬底20的上方,所以,能够成为在将各槽内保护环保持为相同电位方面有利的结构。而且,能够利用浮置场板82b提高半导体装置的耐压稳定性。
本发明的实施方式3的半导体装置能够进行至少与本发明的实施方式1的半导体装置相同程度的变形。
附图标记的说明:
10 半导体装置;12 导电膜;14 绝缘膜;20 半导体衬底;22 阳极;24 保护环;26 低洼部分;28 沟道停止层;30 绝缘膜;60 沟槽;62 槽内保护环;70 绝缘膜;80 沟槽;82a 导电膜;82b 浮置场板;84 槽内保护环;86 绝缘膜;92 电位稳定化导电膜。

Claims (6)

1.一种半导体装置,其特征在于,具备:
第一导电型的半导体衬底;
半导体元件,形成于所述半导体衬底;
保护环,在所述半导体衬底上以包围所述半导体元件的方式由第二导电型的扩散层形成;
低洼部分,在所述半导体衬底上以包围所述保护环的方式形成得比所述半导体衬底的主面低;以及
沟道停止层,沿着所述低洼部分的内壁由第一导电型的扩散层形成。
2.如权利要求1所述的半导体装置,其特征在于,
具备槽内保护环,该槽内保护环沿着在所述半导体衬底的主面以包围所述半导体元件的方式形成的沟槽的内壁由第二导电型的扩散层形成。
3.一种半导体装置,其特征在于,具备:
第一导电型的半导体衬底;
半导体元件,形成于所述半导体衬底;
多个槽内保护环,沿着在所述半导体衬底的主面以包围所述半导体元件的方式形成的多个沟槽的内壁、由第二导电型的扩散层形成;
第二导电型的导电膜,以填埋所述多个沟槽中的至少一个的方式形成;
绝缘膜,以填埋所述多个沟槽中的至少一个的方式形成;以及
浮置场板,在所述绝缘膜的上方以包围所述半导体元件的方式形成。
4.如权利要求3所述的半导体装置,其特征在于,
在所述导电膜的上方具备与所述导电膜连接的第二导电型的电位稳定化导电膜。
5.如权利要求1至4的任一项所述的半导体装置,其特征在于,
所述半导体衬底由宽带隙半导体形成。
6.如权利要求5所述的半导体装置,其特征在于,
所述宽带隙半导体是碳化硅、氮化镓类材料、或者金刚石。
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JP6047429B2 (ja) * 2013-03-08 2016-12-21 株式会社 日立パワーデバイス 半導体装置およびそれを用いた電力変換装置
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CN104810384A (zh) * 2014-01-29 2015-07-29 北大方正集团有限公司 功率半导体器件及制造方法和截止环
CN104810385A (zh) * 2014-01-29 2015-07-29 北大方正集团有限公司 功率半导体器件及制造方法和截止环
CN111316406A (zh) * 2017-11-13 2020-06-19 三菱电机株式会社 碳化硅半导体装置以及碳化硅半导体装置的制造方法
JP6681935B2 (ja) * 2018-04-16 2020-04-15 三菱電機株式会社 半導体装置およびその製造方法
CN114203795A (zh) 2020-09-18 2022-03-18 株式会社东芝 半导体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649168A (zh) * 2004-01-26 2005-08-03 三菱电机株式会社 半导体器件
CN1933167A (zh) * 2005-09-14 2007-03-21 美格纳半导体有限会社 互补金属氧化物半导体图像传感器及其制造方法
CN201611658U (zh) * 2010-01-08 2010-10-20 无锡新洁能功率半导体有限公司 一种深沟槽功率mos器件
CN101996976A (zh) * 2009-08-21 2011-03-30 三菱电机株式会社 半导体装置及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01272152A (ja) * 1988-04-25 1989-10-31 Matsushita Electric Works Ltd ガードリングを有する半導体素子
JP4049971B2 (ja) * 2000-06-15 2008-02-20 株式会社三社電機製作所 半導体素子、半導体素子の製造方法
DE10316222B3 (de) * 2003-04-09 2005-01-20 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Verfahren zur Herstellung eines robusten Halbleiterbauelements und damit hergestelltes Halbleiterbauelement
JP2005183891A (ja) 2003-12-19 2005-07-07 Success International Kk 双方向ブロック型プレーナデバイスの構造と製法
JP4935192B2 (ja) * 2006-05-31 2012-05-23 三菱電機株式会社 半導体装置
JP5376365B2 (ja) * 2009-04-16 2013-12-25 三菱電機株式会社 半導体装置
JP5748188B2 (ja) * 2009-09-29 2015-07-15 富士電機株式会社 半導体装置
JP2011163420A (ja) 2010-02-08 2011-08-25 Mitsubishi Heavy Ind Ltd 軸受構造、及び、ダイレクトドライブ型風力発電装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649168A (zh) * 2004-01-26 2005-08-03 三菱电机株式会社 半导体器件
CN1933167A (zh) * 2005-09-14 2007-03-21 美格纳半导体有限会社 互补金属氧化物半导体图像传感器及其制造方法
CN101996976A (zh) * 2009-08-21 2011-03-30 三菱电机株式会社 半导体装置及其制造方法
CN201611658U (zh) * 2010-01-08 2010-10-20 无锡新洁能功率半导体有限公司 一种深沟槽功率mos器件

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