JP5640969B2 - 半導体素子 - Google Patents
半導体素子 Download PDFInfo
- Publication number
- JP5640969B2 JP5640969B2 JP2011283871A JP2011283871A JP5640969B2 JP 5640969 B2 JP5640969 B2 JP 5640969B2 JP 2011283871 A JP2011283871 A JP 2011283871A JP 2011283871 A JP2011283871 A JP 2011283871A JP 5640969 B2 JP5640969 B2 JP 5640969B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- semiconductor element
- resurf layer
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 166
- 239000012535 impurity Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 39
- 230000002040 relaxant effect Effects 0.000 claims description 11
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 42
- 108091006146 Channels Proteins 0.000 description 25
- 230000015556 catabolic process Effects 0.000 description 17
- 238000000034 method Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 12
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Description
実施の形態1.
図1は、本発明の実施の形態1に係る半導体素子の平面図である。半導体素子10は、チップ中央部分に素子形成領域が設けられ、その表面にはエミッタ電極12とゲート電極パッド14が形成されている。この素子形成領域を囲むように、つまりチップの外周部分に電界緩和領域が設けられ、その表面をパッシベーション膜16で覆っている。
図6は、本発明の実施の形態2に係る半導体素子の断面図である。本発明の実施の形態2に係る半導体素子は、実施の形態1に係る半導体素子と共通点が多い。そのため、以後、実施の形態1に係る半導体素子との相違点を説明する。
図8は、本発明の実施の形態3に係る半導体素子の断面図である。本発明の実施の形態3に係る半導体素子は、実施の形態1に係る半導体素子と共通点が多い。そのため、以後、実施の形態1に係る半導体素子との相違点を説明する。
図10は、本発明の実施の形態4に係る半導体素子の断面図である。本発明の実施の形態4に係る半導体素子は、実施の形態3に係る半導体素子と共通点が多い。そのため、以後、実施の形態3に係る半導体素子との相違点を説明する。
図12は、本発明の実施の形態5に係る半導体素子の断面図である。本発明の実施の形態5に係る半導体素子は、実施の形態3に係る半導体素子と共通点が多い。そのため、以後、実施の形態3に係る半導体素子との相違点を説明する。
図13は、本発明の実施の形態6に係る半導体素子の断面図である。本発明の実施の形態6に係る半導体素子は、半導体基板20の上の構成は本発明の実施の形態1に係る半導体素子と同様であり、リサーフ層の構成は本発明の実施の形態3に係る半導体素子と同様である。
図16は、本発明の実施の形態7に係る半導体素子の断面図である。本発明の実施の形態7に係る半導体素子は、図13に示す実施の形態6に係る半導体素子と共通点が多い。そのため、以後、実施の形態6に係る半導体素子との相違点を説明する。
図19は、本発明の実施の形態8に係る半導体素子の断面図である。本発明の実施の形態8に係る半導体素子は、図6に示す実施の形態2に係る半導体素子と共通点が多い。そのため、以後、実施の形態2に係る半導体素子との相違点を説明する。
Claims (10)
- 主面を有する半導体基板と、
前記半導体基板内に形成された第1導電型の第1不純物領域と、
前記半導体基板内に前記主面に沿って形成された、第2導電型のリサーフ層と、
前記半導体基板内の前記リサーフ層の隣に前記主面に沿って形成された、第2導電型のウエル層と、
前記半導体基板内に前記第1不純物領域を介して前記リサーフ層に接するように前記主面に沿って形成された、第1導電型のチャネルストッパと、
前記ウエル層と前記リサーフ層との境界を含む領域である第1境界領域の上、及び前記リサーフ層と前記第1不純物領域との境界を含む領域である第2境界領域の上とを一体的に覆うように前記主面上に形成された絶縁膜と、
前記絶縁膜中に複数形成された下部フィールドプレートと、を備え、
前記下部フィールドプレートはすべてが前記第1境界領域の直上及び前記第2境界領域の直上を避けて形成されたことを特徴とする半導体素子。 - 前記ウエル層と接し、かつ前記絶縁膜上であって前記第1境界領域の直上に伸びるように形成されたエミッタ電極と、
前記チャネルストッパと接し、かつ前記絶縁膜上であって前記第2境界領域の直上に伸びるように形成されたチャネルストッパ電極と、
を備えたことを特徴とする請求項1に記載の半導体素子。 - 前記絶縁膜上に複数形成された上部フィールドプレートを備え、
前記下部フィールドプレートのうち前記第1境界領域に最も近い第1下部フィールドプレートと前記エミッタ電極で形成される第1静電容量、及び前記下部フィールドプレートのうち前記第2境界領域に最も近い第2下部フィールドプレートと前記チャネルストッパ電極で形成される第2静電容量は、前記下部フィールドプレートのいずれか1つと前記上部フィールドプレートのいずれか1つで形成される第3静電容量よりも大きいことを特徴とする請求項2に記載の半導体素子。 - 前記リサーフ層は、複数の第2導電型の領域で形成されたことを特徴とする請求項1乃至3のいずれか1項に記載の半導体素子。
- 前記リサーフ層は、前記ウエル層側から前記チャネルストッパ側へかけて徐々に第2導電型の不純物濃度が低減するように形成されたことを特徴とする請求項1乃至4のいずれか1項に記載の半導体素子。
- 前記ウエル層の前記リサーフ層と隣り合う部分には、前記ウエル層と前記リサーフ層との第2導電型の不純物濃度勾配を緩和するように濃度勾配緩和部が形成されたことを特徴とする請求項1乃至5のいずれか1項に記載の半導体素子。
- 主面を有する半導体基板と、
前記半導体基板内に形成された第1導電型の第1不純物領域と、
前記半導体基板内に前記主面に沿って形成された、第2導電型のリサーフ層と、
前記半導体基板内の前記リサーフ層の隣に前記主面に沿って形成された、第2導電型のウエル層と、
前記ウエル層の前記リサーフ層と隣り合う部分に、前記ウエル層と前記リサーフ層との第2導電型の不純物濃度勾配を緩和するように形成された濃度勾配緩和部と、
前記濃度勾配緩和部の直上領域に形成されたゲート配線と、
を備えたことを特徴とする半導体素子。 - 前記濃度勾配緩和部の直上領域に形成された、エミッタ電極と接続されたエミッタ接地電極を備えたことを特徴とする請求項7に記載の半導体素子。
- 前記半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1乃至8のいずれか1項に記載の半導体素子。
- 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、又はダイヤモンドであることを特徴とする請求項9に記載の半導体素子。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011283871A JP5640969B2 (ja) | 2011-12-26 | 2011-12-26 | 半導体素子 |
US13/619,565 US9349811B2 (en) | 2011-12-26 | 2012-09-14 | Field plate configuration of a semiconductor device |
DE102012219644.7A DE102012219644B4 (de) | 2011-12-26 | 2012-10-26 | Halbleitervorrichtung |
KR1020120139329A KR101516650B1 (ko) | 2011-12-26 | 2012-12-04 | 반도체 소자 |
US15/131,230 US20160260826A1 (en) | 2011-12-26 | 2016-04-18 | Field plate configuration of a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011283871A JP5640969B2 (ja) | 2011-12-26 | 2011-12-26 | 半導体素子 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013135062A JP2013135062A (ja) | 2013-07-08 |
JP5640969B2 true JP5640969B2 (ja) | 2014-12-17 |
Family
ID=48575817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011283871A Active JP5640969B2 (ja) | 2011-12-26 | 2011-12-26 | 半導体素子 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9349811B2 (ja) |
JP (1) | JP5640969B2 (ja) |
KR (1) | KR101516650B1 (ja) |
DE (1) | DE102012219644B4 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10861932B2 (en) | 2018-10-23 | 2020-12-08 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing semiconductor device |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014060361A (ja) * | 2012-09-19 | 2014-04-03 | Toshiba Corp | 半導体装置 |
JP2014204038A (ja) * | 2013-04-08 | 2014-10-27 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP2014241367A (ja) * | 2013-06-12 | 2014-12-25 | 三菱電機株式会社 | 半導体素子、半導体素子の製造方法 |
JP6091395B2 (ja) * | 2013-10-07 | 2017-03-08 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP6168961B2 (ja) | 2013-10-10 | 2017-07-26 | 三菱電機株式会社 | 半導体装置 |
DE112014006296T5 (de) * | 2014-01-29 | 2017-03-16 | Mitsubishi Electric Corporation | Leistungshalbleitervorrichtung |
WO2015132847A1 (ja) * | 2014-03-03 | 2015-09-11 | 株式会社日立製作所 | Igbt,パワーモジュール,パワーモジュールの製造方法,および電力変換装置 |
JP6019367B2 (ja) * | 2015-01-13 | 2016-11-02 | 株式会社野田スクリーン | 半導体装置 |
JP6460127B2 (ja) * | 2015-01-14 | 2019-01-30 | 富士電機株式会社 | 半導体装置 |
JP6421675B2 (ja) * | 2015-03-30 | 2018-11-14 | サンケン電気株式会社 | 半導体装置 |
JP7150539B2 (ja) * | 2018-09-15 | 2022-10-11 | 株式会社東芝 | 半導体装置 |
JP7085959B2 (ja) * | 2018-10-22 | 2022-06-17 | 三菱電機株式会社 | 半導体装置 |
JP7001050B2 (ja) * | 2018-12-28 | 2022-01-19 | 三菱電機株式会社 | 半導体装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2739004B2 (ja) | 1992-01-16 | 1998-04-08 | 三菱電機株式会社 | 半導体装置 |
EP0702411B1 (en) * | 1994-09-16 | 2002-11-27 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device with a buried MOS-gate structure |
JP2002231944A (ja) | 2001-01-31 | 2002-08-16 | Sanken Electric Co Ltd | 電力用半導体装置 |
JP2002261283A (ja) | 2001-02-27 | 2002-09-13 | Denso Corp | 半導体装置 |
JP4230681B2 (ja) | 2001-07-06 | 2009-02-25 | 株式会社東芝 | 高耐圧半導体装置 |
JP2006173437A (ja) | 2004-12-17 | 2006-06-29 | Toshiba Corp | 半導体装置 |
JP4783050B2 (ja) * | 2005-04-13 | 2011-09-28 | パナソニック株式会社 | 半導体装置及びその製造方法 |
DE102005030886B3 (de) * | 2005-07-01 | 2007-02-08 | Infineon Technologies Ag | Schaltungsanordnung mit einem Transistorbauelement und einem Freilaufelement |
JP2008103529A (ja) | 2006-10-19 | 2008-05-01 | Toyota Central R&D Labs Inc | 半導体装置 |
DE102006061103B4 (de) * | 2006-12-22 | 2008-11-06 | Clariant International Ltd. | Dispersionen polymerer Öladditive |
JP2009004668A (ja) * | 2007-06-25 | 2009-01-08 | Toshiba Corp | 半導体装置 |
JP5391447B2 (ja) | 2009-04-06 | 2014-01-15 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5376365B2 (ja) * | 2009-04-16 | 2013-12-25 | 三菱電機株式会社 | 半導体装置 |
JP5517688B2 (ja) * | 2010-03-24 | 2014-06-11 | 三菱電機株式会社 | 半導体装置 |
JP5515922B2 (ja) * | 2010-03-24 | 2014-06-11 | 富士電機株式会社 | 半導体装置 |
-
2011
- 2011-12-26 JP JP2011283871A patent/JP5640969B2/ja active Active
-
2012
- 2012-09-14 US US13/619,565 patent/US9349811B2/en active Active
- 2012-10-26 DE DE102012219644.7A patent/DE102012219644B4/de active Active
- 2012-12-04 KR KR1020120139329A patent/KR101516650B1/ko active IP Right Grant
-
2016
- 2016-04-18 US US15/131,230 patent/US20160260826A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10861932B2 (en) | 2018-10-23 | 2020-12-08 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2013135062A (ja) | 2013-07-08 |
US9349811B2 (en) | 2016-05-24 |
US20130161645A1 (en) | 2013-06-27 |
DE102012219644A1 (de) | 2013-06-27 |
US20160260826A1 (en) | 2016-09-08 |
KR20130074746A (ko) | 2013-07-04 |
DE102012219644B4 (de) | 2017-06-29 |
KR101516650B1 (ko) | 2015-05-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5640969B2 (ja) | 半導体素子 | |
US11482613B2 (en) | Hybrid active-field gap extended drain MOS transistor | |
US8541834B2 (en) | Semiconductor device and method for manufacturing same | |
KR101598060B1 (ko) | 쉴드형 게이트 mosfet 내 쉴드 콘택들 및 그 형성 방법 | |
US8362550B2 (en) | Trench power MOSFET with reduced on-resistance | |
US8994141B2 (en) | Semiconductor device and method for fabricating the same | |
WO2016152058A1 (ja) | 半導体装置 | |
JP5537996B2 (ja) | 半導体装置 | |
JP5136578B2 (ja) | 半導体装置 | |
JP2019165094A (ja) | 半導体装置 | |
US8017494B2 (en) | Termination trench structure for mosgated device and process for its manufacture | |
CN110010687B (zh) | 半导体器件 | |
US20170194485A1 (en) | Split-gate superjunction power transistor | |
TWI503893B (zh) | 半導體結構及其製作方法 | |
US20090206395A1 (en) | Trench mosfet with double epitaxial structure | |
US20110284923A1 (en) | Semiconductor device and manufacturing method of the same | |
JP2017147393A (ja) | Rb‐igbt | |
JP2021040105A (ja) | 半導体装置およびその製造方法 | |
KR101371495B1 (ko) | 반도체 소자 및 그 제조 방법 | |
JP2021082770A (ja) | 半導体装置 | |
JPWO2003092078A1 (ja) | 半導体素子及びその製造方法 | |
JP2006196545A (ja) | 半導体装置の製造方法 | |
TWI525825B (zh) | 橫向擴散半導體裝置及其製作方法 | |
JP2011049408A (ja) | リセスゲート型炭化珪素電界効果トランジスタおよびその製造方法 | |
TWI578534B (zh) | 高壓金氧半導體電晶體元件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131217 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140418 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140422 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140528 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140930 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141013 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5640969 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |