CN1190832C - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN1190832C
CN1190832C CNB008089345A CN00808934A CN1190832C CN 1190832 C CN1190832 C CN 1190832C CN B008089345 A CNB008089345 A CN B008089345A CN 00808934 A CN00808934 A CN 00808934A CN 1190832 C CN1190832 C CN 1190832C
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layer
raceway groove
semiconductor structure
substrate
heavily doped
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CN1355934A (zh
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H·舍丁
A·舍德贝里
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Infineon Technologies AG
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Abstract

一种半导体元件，该元件包括在衬底层上的高掺杂层并被从元件表面延伸穿过高掺杂层的至少一个沟道所限定，该元件还包括衬底层和高掺杂层之间的子层。所述的子层用与掩埋集电极相同类型的掺杂剂掺杂，但是浓度更低。还公开了制造这种元件的方法。子层使衬底层和子集电极层内的电位线分布更均匀，由此避免形成特别致密的电位线区域。因为电位线致密的区域击穿电压低，避免太致密的电位线意味着增加元件的击穿电压。

Description

半导体结构
技术领域
本发明涉及半导体元件，特别涉及用于这种元件的隔离技术。
背景
为了实现芯片上的集成电路(IC)元件的隔离，目前存在两种主要的方法：结隔离和绝缘体上的硅(SOI)。
在结隔离技术中，从元件到周围的隔离区和到衬底施加反向电压。通常衬底与隔离区是相连的。这种技术有几个缺点，例如到衬底的漏电流，和寄生晶体管的形成。并且，元件的电压越高，外延层的厚度必定更厚。因为隔离区必须延伸穿过整个外延层，对于高电压元件，隔离区同样也变宽，使得整个元件不必要地增大。
在SOI技术中，元件放置在绝缘氧化层上并借助沟道彼此隔离。与结隔离技术相比，这些减小元件的尺寸到50％，有时甚至更多。主要的缺点是作为起始材料的SOI基片的价格和由氧化层产生热绝缘。热绝缘导致元件升温，这种升温可能影响元件的寿命，并且在热失控时存在元件被损坏的风险。
第三种方法是对体硅应用隔离沟道，在低压应用中使用这种方法以节省空间或增强元件的频率特性。沟道壁通常用绝缘体例如氧化物覆盖，并且沟道的其余部分用多晶硅填满。
对于这种高压元件倾向于非常低的击穿电压。
发明目的
本发明的目的是增强在体硅上使用沟道的高压半导体元件的性能。
发明概要
本发明是通过提供一种用于高压半导体元件的半导体结构实现的，该半导体结构包括衬底层，在衬底层上的子集电极层，在子集电极层上的高掺杂层，以及覆盖高掺杂层的外延层，该高掺杂层的掺杂类型与衬底层相反，至少一个沟道从该结构表面延伸穿过高掺杂层来限定半导体结构，其特征在于衬底层是低掺杂的并且子集电极层用与高掺杂层相同类型的掺杂剂掺杂，但是是对最高浓度范围5×1015离子/cm3-1017离子/cm3中的一个较低浓度进行的。
附图简述
图1展示已有技术元件的剖面。
图2展示根据本发明的元件的剖面。
图3A示意图1所示的元件的网点掺杂。
图3B表示与图1所示元件相同的元件的电位分布。
图4A示意图2所示元件的网点掺杂。
图4B表示与图2所示元件相同的元件的电位分布。
图5表示根据本发明第二实施例的元件。
图6表示根据本发明第三实施例的元件。
图7表示根据本发明的优选实施例，包括几个元件的芯片。
实施例详细描述
图1展示根据已有技术的体沟道双极晶体管的剖面。p型硅衬底1上的n掺杂层构成掩埋集电极3，且掩埋集电极3的顶上有n型外延层5，该外延层5包括含有n+掺杂发射极9的p+掺杂基极7。在外延层5中还有集电极区11。具有基极7、发射极9和集电极11的元件借助沟道13与周围的元件(未示出)隔离。每个沟道都具有覆盖壁和底部的绝缘层15，并且它的内部17用多晶硅填满。
沟道的两侧存在由于n+掺杂掩埋集电极层而形成寄生MOS元件的风险。对于低电压元件，沟道壁上的绝缘层15可以足以阻止围绕沟道形成寄生MOS元件。如果这样不够充分，可以在沟道的底部设置p+掺杂区19以增加电路的馈送电压上的阈值电压。
对于高压元件，这些措施并不够充分。因此整个沟道的内部必须用绝缘材料填满、或沟道内部的多晶硅必须连接到设在芯片上的最低电位基层(found)，最低电位基层通常是衬底1。通过在沟道的顶上应用大量的接触、或在多晶硅被应用到沟道的内部之前在沟道的底部刻蚀一个穿过氧化层15的孔就可以实现沟道的内部17和衬底1之间的接触。用这些方法将沟道连接到衬底1的低电位。如上所述，这些接触可以用几种不同的方法制得。重要的是衬底层和沟道中的多晶硅大约等电位。
术语“掩埋集电极”指用作使衬底电流最小的屏蔽的高掺杂层。它不必具有集电极的作用。
在衬底层1邻近掩埋集电极3的部分形成一个强电场，该电场可能减小元件的击穿电压。这些可以通过保持衬底低掺杂以致耗尽区能够延伸到衬底层内来阻止。延伸多深取决于衬底掺杂。在沟道截断掩埋集电极的区域附近，仍然产生强电场，且击穿电压低。可以通过增加沟道内氧化层的厚度增加击穿电压，但是当晶片进行热处理时，如果氧化层太厚，由氧化物和硅之间的热失配引起的机械张力将导致例如滑动线缺陷产生。
根据本发明，正好在掩埋集电极之下衬底层部分用n型掺杂剂掺杂，但是比掩埋层3的浓度低。所得的元件如图2所示。
如上所述，p型硅衬底101支撑构成掩埋集电极103的n掺杂层，且掩埋集电极的顶上有n型外延层105，该外延层包括其内有n+掺杂发射极109的p+掺杂基极107。在外延层105中还有一个集电极区111。具有基极107、发射极109和集电极111的元件借助沟道113与周围的元件(未示出)隔离。每个沟道都具有覆盖壁和底部的绝缘层115，且沟道的内部117用多晶硅填满。如上所述，整个沟道可以用绝缘体例如氧化物填充来代替。随意地，可以在沟道的底部设置p+掺杂区119以增加电路的馈送电压上的阐值电压。如果沟道是连接到固定电压，这些p+掺杂区119是非必要的。
根据本发明，轻n掺杂子集电极层121正好设置在掩埋集电极下。如图3B和4B所示，这些层121用来使电位分布更均匀，并且由此避免形成击穿电压特别低的元件区域，亦即，那些特别容易击穿的区域。
图3A表示沿水平轴，用点线代表图1所示元件的A-A剖面。最左边的曲线对应于图1的外延层5的表面，最右边的曲线对应于衬底层1的底部。垂直轴表示根据对数刻度的网点掺杂。如图所示，通过外延层下至大约16μm处即对应于掩埋集电极的重n掺杂区起始之处的掺杂几乎是恒定的。n掺杂区在大约20μm处有一个峰值。在大约25μm处有由掩埋层3和衬底层1之间的pn结引起的尖锐负峰值。
因此，图1所示元件的电位分布一般如图3B所示。在图3B的左边部分，表示半个沟道，沟道壁上有绝缘层15，并且其内部17用多晶硅填满。在沟道内部17的多晶硅和衬底1设为等电位。n+层3比衬底电位高。用3表示的电位线跟随绝缘层15下至掩埋集电极的水平，在那里电位线弯曲并在掩埋集电极下的衬底内水平延伸。在电位线弯曲的地方，产生一个强电场，这样在衬底层的这些区域将产生低的击穿电压。
图4A表示沿水平轴，用点线代表图2所示元件的B-B剖面。最左边的曲线对应于外延层105的表面。最右边的曲线对应于衬底层101的底部。垂直轴表示根据对数刻度的网点掺杂。如图所示，该剖面实际上与图3A所示的一样，20μm处向下至峰值对应于掩埋集电极。在那之下，掺杂比图3A下降慢。在大约30μm处存在对应于衬底层101和子集电极层121之间的pn结的负峰值。
所得的电位分布如图4B所示。在图4B的左边部分表示半个沟道，沟道壁上有绝缘层115，其内部117用多晶硅填满。用103表示的电位线跟随绝缘层115向下至掩埋集电极的水平，在那里电位线弯曲并在掩埋集电极下衬底的n掺杂层内水平延伸。如图所示，与图3B相比较，图4B的电位线更平滑和分布更均匀，意味着直到施加电压相当高时才会达到临界电场强度。这些表明，根据本发明图2所示的元件的击穿电压将比图1所示的已有技术的元件的击穿电压显著增加。
图5表示另一可选实施例，其中在沟道底部的p+掺杂区已被连续的p+掺杂层取代。如图2所示，在p型硅衬底201上支撑构成掩埋集电极203的n掺杂层，掩埋集电极的顶上有n型外延层205，该外延层包括含有n+掺杂发射极209的p+掺杂基极207。在外延层205中还有一个集电极区211。具有基极207、发射极209和集电极211的元件借助沟道213与周围的元件(未示出)隔离。每个沟道都具有覆盖壁和底部的绝缘层215，且沟道的内部217用多晶硅填满。如上所述，整个沟道可以用绝缘体例如氧化物填充来代替。代替图2中的p+掺杂区119，以沟道213的底部所达到的水平在衬底层201内设置一层p+掺杂层219。如上所述，P+掺杂层用来增加阈值电压以避免形成漏寄生MOS元件。根据本发明的轻n掺杂子集电极层221正好设置在掩埋集电极下。
如图6所示，掩埋集电极不必延伸穿过整个元件。与前面的图一样，图6表示在p型硅衬底301上支撑构成掩埋集电极303的n掺杂层，且掩埋集电极的顶上是n外延层305，该外延层包括含有n+掺杂发射极309的p+掺杂基极307。然而，在该实施例中，掩埋集电极303没在整个元件上延伸。在外延层305中还有一个集电极区311。具有基极307、发射极309和集电极311的元件借助沟道313与周围的元件(未示出)隔离。每个沟道都具有覆盖壁和底部的绝缘层315，并且沟道的内部317用多晶硅填满。如上所述，整个沟道可以用绝缘体例如氧化物填充来代替。如图5所示，以沟道313的底部可以到达的水平在衬底层301内设置一层p+掺杂层319。显然可以用围绕沟道底部的p+掺杂区(图2中的119)来代替，或者p+掺杂区是不必要的。根据本发明的轻n掺杂子集电极层321正好设置在掩埋集电极下。
根据本发明引入的子集电极层121，221，321可与掩埋集电极同时、或之前或之后制作。
如果在掩埋集电极之前制作，可以使用慢扩散掺杂剂，例如砷和锑。这些需要一个额外的热扩散步骤，但是具有优点：在包括高温的随后处理步骤中掺杂分布不会改变太大。在这种情况下，首先掺杂衬底101以生成子集电极层121，然后再掺杂以生成掩埋集电极103。
如果使用快扩散掺杂剂，例如磷，子集电极层121可以与掩埋集电极103同时掺杂，或者在子集电极层121和掩埋集电极103的掺杂期间不用热处理。由于热处理意味着在800℃以上的温度处理。当然也可以用与慢扩散掺杂剂相类似的方法首先掺杂子集电极层121，但是用较低的温度和/或较短的时间。使用快扩散掺杂剂时，子集电极层121也可以在掩埋集电极103之后掺杂。
不论选择何种方法，在子集电极层121和掩埋集电极103的掺杂之后，都是在掩埋集电极的顶上生长外延层105。
为了保持沟道内部的多晶硅处于低电位，沟道内的多晶硅可以借助表面触点与衬底层电接触。在包括几个元件的芯片上，如果沟道是彼此连接的，需要的触点数目可以减少。图7是包括四个元件401，403，405，407的芯片的俯视图，每个元件都分别被沟道402，404，406，408围绕。四个元件的沟道已相互连接形成不规则的网状，并且使用仅示意性地示出的两个触点409，411连接四个沟道402，404，406，408到衬底层。当然，一个触点就足够了，但是如果希望也可以使用更多的触点。

Claims (8)

1.一种用于高压半导体元件的半导体结构，包括衬底层(101、201、301)，在衬底层(101、201、301)上的子集电极层(121、221、321)，在子集电极层上的高掺杂层，以及覆盖高掺杂层(103、203、303)的外延层，该高掺杂层的掺杂类型与衬底层(101、201、301)相反，至少一个沟道(113、213、313)从该结构表面延伸穿过高掺杂层(103、103、203)来限定半导体结构，其特征在于衬底层(101、201、301)是低掺杂的并且子集电极层(121、221、321)用与高掺杂层(103、103、203)相同类型的掺杂剂掺杂，但是是对最高浓度范围5×1015离子/cm3-1017离子/cm3中的一个较低浓度进行的。
2.根据权利要求1的半导体结构，其特征在于子集电极层(121、221、321)的厚度在2μm和10μm之间。
3.根据权利要求1或2的半导体结构，其特征在于一个围绕所述至少一个沟道(113、213、313)的底部而不与子集电极层(121、221、321)相接触的区域(119、219、319)，所述区域用与高掺杂层(103、203、303)相反类型的掺杂剂掺杂。
4.根据权利要求1的半导体结构，其特征在于所述至少一个沟道(113、213、313)的壁用氧化层(115、215、315)覆盖，且沟道的内部(117、217、317)用多晶硅填满，多晶硅与衬底层(101、201、301)电接触。
5.根据权利要求1的半导体结构，其特征在于高掺杂层(103、203、303)是用砷或锑掺杂的。
6.根据权利要求1的半导体结构，其特征在于子集电极层(121、221、321)是用磷掺杂的。
7.根据权利要求1的半导体结构，其特征在于子集电极层(121、221、321)是用砷或锑掺杂的。
8.根据权利要求1的半导体结构，其特征在于所述至少一个沟道连接到限定至少一个其它结构的至少一个其它沟道。
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