JP6289683B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6289683B2 JP6289683B2 JP2016571549A JP2016571549A JP6289683B2 JP 6289683 B2 JP6289683 B2 JP 6289683B2 JP 2016571549 A JP2016571549 A JP 2016571549A JP 2016571549 A JP2016571549 A JP 2016571549A JP 6289683 B2 JP6289683 B2 JP 6289683B2
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Description
本発明は、パワーモジュール(耐圧(定格電圧)が600V以上)のキーコンポーネントであるパワー半導体素子であるIGBT及びダイオードで代表される、バイポーラ系パワー半導体素子を有する半導体装置において、以下の特徴(a) 〜(c)を有する縦構造領域に関している。
(b) ターンオフ動作終焉での電圧跳ね上がり現象(以下、「snap-off現象」と略記する)や、それをトリガーとする発振現象抑制する縦構造領域、
(c) ターンオフ動作時の遮断能力向上する縦構造領域である。
実施の形態1の半導体装置は、IGBT及びダイオードで代表される縦型半導体装置の縦構造領域27(縦構造領域27G及び縦構造領域27D)におけるNバッファ層15に関する技術であり、ターンオン動作時のsnap-off現象やその後の発振現象の抑制効果を有し、オフ状態の耐圧遮断能力を上げ、かつ高温でのリーク電流低減し、低オフロスや高温動作を実現する。
実施の形態2として、実施の形態1と同じ効果の得られるNバッファ層15の構造技術を説明する。
図34〜図46は実施の形態1あるいは実施の形態2におけるIGBT(図10(a) )の製造方法(その1)を示す断面図である。なお、これらの図面は活性セル領域R1における製造方法を示している。
図47〜図54は実施の形態1あるいは実施の形態2における第2種ダイオード(図10(c))の製造方法(その2)を示す断面図である。
実施の形態3の半導体装置は、図3に示すパワー半導体の構成要素と実施の形態1及び実施の形態2に示す特徴的なNバッファ層15との関係により、IGBT及びダイオードのターンオフ時の遮断能力のさらなる向上を図った技術である。
Claims (19)
- 一方主面及び他方主面を有し、第1の導電型のドリフト層(14)を主要構成部として含む半導体基体と、
前記半導体基体内において、前記ドリフト層に対し他方主面側に前記ドリフト層に隣接して形成される第1の導電型のバッファ層(15)と、
前記半導体基体の他方主面上に形成される、第1及び第2の導電型のうち少なくとも一つの導電型を有する活性層(16,17,18,19)と、
前記半導体基体の一方主面上に形成される第1の電極(5E,5A)と、
前記活性層上に形成される第2の電極(23C,23K)とを備え、
前記バッファ層内で不純物の濃度勾配を有する主要部において、一方主面から他方主面に向かう方向における濃度勾配δは、深さ量をTB(μm)、不純物濃度をCB(cm−3)とした変位により以下の式(1)で表され、
半導体装置。 - 請求項1記載の半導体装置であって、
前記濃度勾配δは、{0.03≦δ≦0.2}で規定される最適濃度勾配条件を満足することを特徴とする、
半導体装置。 - 請求項1記載の半導体装置であって、
前記バッファ層の第1の導電型の不純物のピーク濃度PCは、{2×1014(cm−3)≦PC≦1.0×1016(cm−3)}で規定されるピーク不純物濃度条件を満足することを特徴とする、
半導体装置。 - 請求項1記載の半導体装置であって、
前記ドリフト層と前記バッファ層との接合部の前記第2の電極と前記活性層との接合面からの距離である形成深さtNB(μm)は、{4.0≦JD≦50.0(μm)}で規定される形成深さ条件を満足することを特徴とする、
半導体装置。 - 請求項1から請求項4のうち、いずれか1項に記載の半導体装置であって、
前記半導体基体内において、前記バッファ層に対し他方主面側に前記バッファ層に隣接して形成される、第1の導電型のバッファ補助層(29)をさらに備え、
前記活性層は前記バッファ補助層上に形成され、
前記バッファ補助層に関し、前記バッファ層との間における第1の導電型の不純物注入比率Tαは、前記バッファ層への第1の導電型の不純物注入量をDose・NB1、前記バッファ補助層への第1の導電型の不純物注入量をDose・NB2としたとき、以下の式(2)で表され、
半導体装置。 - 一方主面及び他方主面を有し、第1の導電型のドリフト層(14)を主要構成部として含む半導体基体と、
前記半導体基体内において、前記ドリフト層に対し他方主面側に前記ドリフト層に隣接して形成される第1の導電型のバッファ層(15)と、
前記半導体基体の他方主面上に形成される、第1及び第2の導電型のうち少なくとも一つの導電性を有する活性層(16,17,18,19)と、
前記半導体基体の一方主面上に形成される第1の電極(5E,5A)と、
前記活性層上に形成される第2の電極(23C,23K)とを備え、
前記バッファ層における第1の導電型の不純物濃度のプロファイルは複数のピーク濃度値を有する複数ピークプロファイルを呈し、前記バッファ層内で前記複数ピークプロファイルを呈する主要部において、一方主面から他方主面に向かう方向における前記複数のピーク濃度値に基づき想定される仮想濃度勾配Pδは、深さ量をPTB(μm)、不純物濃度をPCB(cm−3)としたとき、以下の式(3)で表され、
半導体装置。 - 請求項6記載の半導体装置であって、
前記複数ピークプロファイルは、前記複数のピーク濃度値間における谷の領域において、他方主面から一方主面に向けて不純物濃度が低くなる濃度傾斜を有している、
半導体装置。 - 請求項7記載の半導体装置であって、
前記複数ピークプロファイルにおいて、第1の導電型の不純物濃度の最小値は前記ドリフト層の第1の導電型の不純物濃度よりも高く設定される、
半導体装置。 - 請求項6から請求項8のうち、いずれか1項に記載の半導体装置であって、
前記バッファ層の前記複数ピークプロファイルにおいて、第1の導電型の不純物のピーク濃度PCは、{2×1014(cm−3)≦PC≦1.0×1016(cm−3)}で規定されるピーク不純物濃度条件を満足することを特徴とする、
半導体装置。 - 請求項6から請求項8のうち、いずれか1項に記載の半導体装置であって、
前記ドリフト層と前記バッファ層との接合部の前記第2の電極と前記活性層との接合面からの距離である形成深さtNB(μm)は、{4.0≦JD≦50.0}で規定される形成深さ条件を満足することを特徴とする、
半導体装置。 - 請求項6から請求項8のうち、いずれか1項に記載の半導体装置であって、
前記半導体基体内において、前記バッファ層に対し他方主面側に前記バッファ層に隣接して形成される、第1の導電型のバッファ補助層(29)をさらに備え、
前記活性層は前記バッファ補助層上に形成され、
前記バッファ補助層に関し、前記バッファ層との間における第1の導電型の不純物注入比率PTαは、前記バッファ層への第1の導電型のトータルの不純物注入量をDose・NB3、前記バッファ補助層の第1の導電型の不純物注入量をDose・NB4としたとき、以下の式(4)で表され、
半導体装置。 - 請求項1から請求項3及び請求項6から請求項8のうち、いずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第1の導電型の絶縁ゲート型のトランジスタ形成領域(7,9,11,12,13)を有し、
前記活性層(16)は第2の導電型を呈し、
前記半導体装置は、
前記トランジスタ形成領域、前記バッファ層、前記活性層、並びに前記第1及び第2の電極によりIGBTが形成される素子形成領域(R1)と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域(R2,R3)とを有する、
半導体装置。 - 請求項12記載の半導体装置であって、
前記活性層は前記素子形成領域のみに形成され、
前記周辺領域において前記バッファ層上に前記第2の電極が設けられる、
半導体装置。 - 請求項1から請求項3及び請求項6から請求項8のうち、いずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第2の導電型の一方電極領域(10)を有し、
前記活性層(17)は第1の導電型を呈し、第1の導電型の不純物濃度が前記バッファ層より高く設定され、前記活性層が他方電極領域として機能し、
前記半導体装置は、
前記一方電極領域、前記バッファ層、前記活性層、並びに前記第1及び第2の電極によりダイオードが形成される素子形成領域(R1)と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域(R2,R3)とを有する、
半導体装置。 - 請求項14記載の半導体装置であって、
前記活性層は前記素子形成領域のみに形成され、
前記周辺領域において前記バッファ層上に前記第2の電極が設けられる、
半導体装置。 - 請求項1から請求項3及び請求項6から請求項8のうち、いずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第2の導電型の一方電極領域(10)を有し、
前記活性層は第1の導電型の第1の部分活性層(19)と、第2の導電型の第2の部分活性層(18)とを含み、前記第1の部分活性層の第1の不純物濃度は前記バッファ層より高く設定され、前記第1の部分活性層が他方電極領域として機能し、
前記半導体装置は、
前記一方電極領域、前記バッファ層、前記第1及び第2の部分活性層、並びに前記第1及び第2の電極によりダイオードが形成される素子形成領域(R1)と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域(R2,R3)とを有する、
半導体装置。 - 請求項16記載の半導体装置であって、
前記素子形成領域において前記第1及び第2の部分活性層が形成され、
前記周辺領域において前記第2の部分活性層のみが形成される、
半導体装置。 - 請求項16記載の半導体装置であって、
前記第1及び第2の部分活性層は前記素子形成領域のみに形成され、
前記周辺領域において前記バッファ層上に前記第2の電極が設けられる、
半導体装置。 - 請求項16記載の半導体装置であって、
前記素子形成領域において前記第1及び第2の部分活性層が形成され、
前記周辺領域において前記第1の部分活性層のみが形成される、
半導体装置。
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