CN109065627A - 一种具有多晶硅岛的ldmos器件 - Google Patents
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
本发明提供一种具有多晶硅岛的LDMOS器件,N型漂移区的内部上表面有沟槽,沟槽内填有绝缘介质层,沟槽内有多个多晶硅岛,多晶硅岛沿着水平方向等间距排列,多晶硅岛中存储有负电荷,且负电荷的存储量沿着N型漏极接触区到P型体区的方向逐渐减少;本发明当器件反向阻断时,N型漂移区与多晶硅岛之间有纵向电场,辅助耗尽N型漂移区,在相同的耐压下,N型漂移区可采用更高的掺杂浓度,降低器件的导通电阻;同时由于N型漂移区从右往左电势不断降低,而多晶硅岛中的负电荷量从右往左不断减少,这样就使得N型漂移区的纵向电场分布更加均匀,从而横向电场更加接近矩形分布,提高LDMOS的击穿电压。
Description
技术领域
本发明涉及功率半导体技术,具体涉及一种具有多晶硅岛的LDMOS器件。
背景技术
随着半导体行业的不断发展,以横向双扩散金属氧化物半导体器件(LDMOS)为代表的横向器件得到广泛应用。在LDMOS器件的设计中,击穿电压BV和比导通电阻Ron,sp是非常关键的电学参数,而这两者之间存在相互制约的硅极限问题:Ron,sp∝BV2.5,这一矛盾关系大大限制了LDMOS在高压大电流领域的应用。为了解决这个问题,人们提出了Resurf技术。
Resurf(Reduced Surface Field,降低表面电场)技术是在设计横向高压、低导通电阻器件中最广泛使用的技术,运用该技术可以设计出20V-1200V的集成高压器件。该技术通过让漂移区全部耗尽,将表面的电场峰值降低,从而让器件体内的电场峰值比表面电场峰值先达到极值,以提高击穿电压。对于体硅Single Resurf LDMOS器件,电子从源区移动到漏区,器件电流主要从表面由漏区流向源区,LDMOS器件漂移区承载的耐压主要由漏区和漂移区形成的反向PN结承担,器件耐压不大。为了提升体硅结构下的LDMOS器件的耐压,必须降低漂移区掺杂浓度,然而因漂移区掺杂浓度下降,又将增大整个器件的导通电阻,这一矛盾关系是此类结构器件共同拥有的。为了保持耐压不降低,同时又能降低器件导通电阻,人们又提出了Double Resurf技术。该技术是通过在漂移区上方增加了P-top层,辅助耗尽漂移区,在提高击穿电压的同时,降低导通电阻。该结构优化了器件耐压和比导通电阻的矛盾关系,因而得到了广泛应用。但是,该结构也存在一定的缺陷,其漂移区的横向电场如图1所示,可以看出,由于整个P-top层上的电位相同,漂移区内的横向电场沿着水平方向下降,制约了击穿电压的进一步提高。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种具有多晶硅岛的LDMOS器件。
为实现上述发明目的,本发明技术方案如下:
一种具有多晶硅岛的LDMOS器件,包括P型衬底、P型外延层、P型体区、N型漂移区、栅极结构;其中,所述P型外延层位于P型衬底的上表面;所述P型体区和N型漂移区位于P型外延层的内部上表面;所述P型体区和N型漂移区的侧面接触;所述P型体区的内部上表面有重掺杂的P型源极接触区和重掺杂的N型源极接触区;所述P型源极接触区和重掺杂的N型源极接触区的侧面接触;所述P型源极接触区和重掺杂的N型源极接触区的内部上表面有源极接触;所述P型体区的上表面有栅极结构,所述栅极结构包括侧墙和栅氧化层以及多晶硅栅电极;所述栅氧化层与P型体区相接触;所述多晶硅栅电极位于栅氧化层的上表面;所述侧墙分立于栅氧化层和多晶硅栅电极的两侧;所述N型漂移区的内部上表面远离P型体区的一侧有重掺杂的N型漏极接触区;所述N型漏极接触区的内部上表面有漏极接触;所述N型漂移区的内部上表面有沟槽,所述沟槽位于P型体区和N型漏极接触区之间且与N型漏极接触区不接触;所述沟槽内填有绝缘介质层,所述沟槽内有多个多晶硅岛,所述多晶硅岛沿着水平方向等间距排列,所述多晶硅岛中存储有负电荷,且负电荷的存储量沿着N型漏极接触区到P型体区的方向逐渐减少。
作为优选方式,所述源极接触和漏极接触的材料是金属硅化物。
作为优选方式,所述源极接触和漏极接触的材料选自CoSi2,NiSi2,TiSi2和PtSi。
作为优选方式,所述多晶硅岛中的负电荷通过淀积或离子注入负电性材料形成。
作为优选方式,沟槽内填充的绝缘介质层材料是二氧化硅。
作为优选方式,所述多晶硅岛的个数是三个或者三个以上。
本发明的有益效果为:相比于之前的Double Resurf LDMOS结构,本发明所提供的一种具有多晶硅岛的LDMOS器件结构具有两个或者两个以上的多晶硅岛,多晶硅岛中存储有负电荷。当器件反向阻断时,N型漂移区与多晶硅岛之间有纵向电场,辅助耗尽N型漂移区,在相同的耐压下,N型漂移区可采用更高的掺杂浓度,降低器件的导通电阻;同时由于N型漂移区从右往左电势不断降低,而多晶硅岛中的负电荷量从右往左不断减少,这样就可以使得N型漂移区的纵向电场分布更加均匀,从而横向电场更加接近矩形分布,提高LDMOS的击穿电压。
附图说明
图1是传统的Double Resurf LDMOS的结构示意图及其在反向偏压时N型漂移区的表面横向电场分布图;
图2是本发明提供的一种具有多晶硅岛的LDMOS器件的剖面结构示意图;
图3是本发明提供的一种具有多晶硅岛的LDMOS器件在反向偏压时N型漂移区的电场分布图;
图4-图9是本发明提供的一种具有多晶硅岛的LDMOS器件在制造过程中的关键工艺步骤;
1为P型衬底,2为P型外延层,3为P型体区,4为P型源极接触区,5为N型源极接触区,6为源极接触,7为侧墙,8为栅氧化层,9为多晶硅栅电极,10为N型漂移区,11为N型漏极接触区,12为漏极接触,13为沟槽,14为多晶硅岛。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
实施例
如图2所示,一种具有多晶硅岛的LDMOS器件,包括P型衬底1、P型外延层2、P型体区3、N型漂移区10、栅极结构;其中,所述P型外延层2位于P型衬底1的上表面;所述P型体区3和N型漂移区10位于P型外延层2的内部上表面;所述P型体区3和N型漂移区10的侧面接触;所述P型体区3的内部上表面有重掺杂的P型源极接触区4和重掺杂的N型源极接触区5;所述P型源极接触区4和重掺杂的N型源极接触区5的侧面接触;所述P型源极接触区4和重掺杂的N型源极接触区5的内部上表面有源极接触6;所述P型体区3的上表面有栅极结构,所述栅极结构包括侧墙7和栅氧化层8以及多晶硅栅电极9;所述栅氧化层8与P型体区3相接触;所述多晶硅栅电极9位于栅氧化层8的上表面;所述侧墙7分立于栅氧化层8和多晶硅栅电极9的两侧;所述N型漂移区10的内部上表面远离P型体区3的一侧有重掺杂的N型漏极接触区11;所述N型漏极接触区11的内部上表面有漏极接触12;所述N型漂移区10的内部上表面有沟槽13,所述沟槽13位于P型体区3和N型漏极接触区11之间且与N型漏极接触区11不接触;所述沟槽13内填有绝缘介质层,所述沟槽13内有多个多晶硅岛14,所述多晶硅岛14沿着水平方向等间距排列,所述多晶硅岛14中存储有负电荷,且负电荷的存储量沿着N型漏极接触区11到P型体区3的方向逐渐减少。
进一步的,所述源极接触6和漏极接触12的材料是金属硅化物。
进一步的,所述源极接触6和漏极接触12的材料选自CoSi2,NiSi2,TiSi2和PtSi。
进一步的,所述多晶硅岛14中的负电荷通过淀积或离子注入负电性材料形成。
进一步的,沟槽13内填充的绝缘介质层材料是二氧化硅。
进一步的,所述多晶硅岛14的个数是三个或者三个以上。
本实施例的工作原理如下:
本发明提供的一种具有多晶硅岛的LDMOS器件,其反向阻断时的电极连接方式为:源极接触6和多晶硅栅电极9短接且接地,漏极接触12接高电位。
当器件反向阻断时,N型漂移区与绝缘介质层中的多晶硅岛之间有纵向电场,辅助耗尽N型漂移区;同时,由于漏极接触接高电位,源极接触接地,N型漂移区从右往左的电势不断降低,而绝缘介质层中的多晶硅岛的负电荷量从右往左不断减少,这样就可以使得N型漂移区与多晶硅岛之间的纵向电场沿着水平方向基本保持不变,从而横向电场更加接近矩形分布,如图3所示。相较于传统的Double Resurf LDMOS器件在反向阻断时的N型漂移区在水平方向上的电场分布,电场斜率减小,电场线E(x)与X轴之间所围面积增大,器件的击穿电压BV得到提高。
本发明提供的一种具有多晶硅岛的LDMOS器件在制造过程中的关键工艺步骤如下:
1、单晶硅准备及外延生长。选用P型重掺杂单晶硅衬底,晶向为<100>。在P型衬底1上生长一定厚度和掺杂浓度的P型外延层2,如图4所示;
2、光刻及注入,通过光刻,确定N型漂移区10,注入N型杂质,推阱,形成N型漂移区10;通过光刻,确定P型体区3,注入P型杂质,推阱,形成P型体区3,如图5所示;
3、刻蚀N型漂移区10,形成表面沟槽13,在沟槽13中生长绝缘介质层,生长完成后进行化学机械抛光CMP,如图6所示;
4、在沟槽13内刻蚀深度更浅的沟槽,通过淀积或离子注入负电性材料在沟槽13内形成多晶硅岛14,重复上述步骤,形成两个或两个以上带有负电荷的多晶硅岛14,多晶硅岛14沿着水平方向等间距排列,相邻的多晶硅岛通过绝缘介质层隔绝,多晶硅岛内负电荷的存储量沿着N型漏极接触区11到P型体区3的方向逐渐减少,如图7所示;
5、制备栅极结构,热生长栅氧化层8,淀积多晶硅栅电极9,光刻刻蚀多晶硅和栅氧化层;制备侧墙,在硅片表面淀积二氧化硅,利用干法刻蚀工艺反刻掉二氧化硅,当多晶硅栅电极9露出来即停止反刻,如图8所示;
6、光刻及注入,通过光刻、中等能量地注入N型杂质,形成N型源极接触区5和N型漏极接触区11;通过光刻、中等能量地注入P型杂质,形成P性源极接触区4,如图9所示;
7、淀积金属,形成金属硅化物,作为源极接触6和漏极接触12,如图1所示。
本发明提出的一种具有多晶硅岛的LDMOS器件,同样适用于碳化硅、砷化镓、磷化铟或锗硅等半导体材料的器件。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (6)
1.一种具有多晶硅岛的LDMOS器件,其特征在于:包括P型衬底(1)、P型外延层(2)、P型体区(3)、N型漂移区(10)、栅极结构;其中,所述P型外延层(2)位于P型衬底(1)的上表面;所述P型体区(3)和N型漂移区(10)位于P型外延层(2)的内部上表面;所述P型体区(3)和N型漂移区(10)的侧面接触;所述P型体区(3)的内部上表面有重掺杂的P型源极接触区(4)和重掺杂的N型源极接触区(5);所述P型源极接触区(4)和重掺杂的N型源极接触区(5)的侧面接触;所述P型源极接触区(4)和重掺杂的N型源极接触区(5)的内部上表面有源极接触(6);所述P型体区(3)的上表面有栅极结构,所述栅极结构包括侧墙(7)和栅氧化层(8)以及多晶硅栅电极(9);所述栅氧化层(8)与P型体区(3)相接触;所述多晶硅栅电极(9)位于栅氧化层(8)的上表面;所述侧墙(7)分立于栅氧化层(8)和多晶硅栅电极(9)的两侧;所述N型漂移区(10)的内部上表面远离P型体区(3)的一侧有重掺杂的N型漏极接触区(11);所述N型漏极接触区(11)的内部上表面有漏极接触(12);所述N型漂移区(10)的内部上表面有沟槽(13),所述沟槽(13)位于P型体区(3)和N型漏极接触区(11)之间且与N型漏极接触区(11)不接触;所述沟槽(13)内填有绝缘介质层,所述沟槽(13)内有多个多晶硅岛(14),所述多晶硅岛(14)沿着水平方向等间距排列,所述多晶硅岛(14)中存储有负电荷,且负电荷的存储量沿着N型漏极接触区(11)到P型体区(3)的方向逐渐减少。
2.根据权利要求1所述的一种具有多晶硅岛的LDMOS器件,其特征在于:所述源极接触(6)和漏极接触(12)的材料是金属硅化物。
3.根据权利要求2所述的一种具有多晶硅岛的LDMOS器件,其特征在于:所述源极接触(6)和漏极接触(12)的材料选自CoSi2,NiSi2,TiSi2和PtSi。
4.根据权利要求1所述的一种具有多晶硅岛的LDMOS器件,其特征在于:所述多晶硅岛(14)中的负电荷通过淀积或离子注入负电性材料形成。
5.根据权利要求1所述的一种具有多晶硅岛的LDMOS器件,其特征在于:沟槽(13)内填充的绝缘介质层材料是二氧化硅。
6.根据权利要求1所述的一种具有多晶硅岛的LDMOS器件,其特征在于:所述多晶硅岛(14)的个数是三个或者三个以上。
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109728076A (zh) * | 2018-12-28 | 2019-05-07 | 电子科技大学 | 一种横向抗辐射功率器件结构 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060006386A1 (en) * | 2003-08-27 | 2006-01-12 | Franz Hirler | Lateral semiconductor component with a drift zone having at least one field electrode |
CN101673763A (zh) * | 2008-09-09 | 2010-03-17 | 上海华虹Nec电子有限公司 | Ldmos晶体管及其制备方法 |
CN106098781A (zh) * | 2016-08-17 | 2016-11-09 | 电子科技大学 | 一种沟槽结构的vdmos |
-
2018
- 2018-08-21 CN CN201810955274.4A patent/CN109065627A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060006386A1 (en) * | 2003-08-27 | 2006-01-12 | Franz Hirler | Lateral semiconductor component with a drift zone having at least one field electrode |
CN101673763A (zh) * | 2008-09-09 | 2010-03-17 | 上海华虹Nec电子有限公司 | Ldmos晶体管及其制备方法 |
CN106098781A (zh) * | 2016-08-17 | 2016-11-09 | 电子科技大学 | 一种沟槽结构的vdmos |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109728076A (zh) * | 2018-12-28 | 2019-05-07 | 电子科技大学 | 一种横向抗辐射功率器件结构 |
CN113410298A (zh) * | 2020-03-16 | 2021-09-17 | 电子科技大学 | 一种具有表面耐压结构的n沟道LDMOS器件及其制备方法 |
CN113410299A (zh) * | 2020-03-16 | 2021-09-17 | 电子科技大学 | 一种高耐压的n沟道LDMOS器件及其制备方法 |
CN113410281A (zh) * | 2020-03-16 | 2021-09-17 | 电子科技大学 | 一种具有表面耐压结构的p沟道LDMOS器件及其制备方法 |
CN113410300A (zh) * | 2020-03-16 | 2021-09-17 | 电子科技大学 | 一种高耐压的p沟道LDMOS器件及其制备方法 |
CN111640785A (zh) * | 2020-06-12 | 2020-09-08 | 电子科技大学 | 一种具有多沟槽的ligbt器件 |
CN112071896A (zh) * | 2020-07-30 | 2020-12-11 | 浙江大学 | 一种横向4H-SiC MOSFET功率器件 |
CN113270500A (zh) * | 2021-05-17 | 2021-08-17 | 电子科技大学 | 一种功率半导体器件 |
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