DE60127052D1 - Herstellungsverfahren einer integrierten Halbleiterschaltung - Google Patents

Herstellungsverfahren einer integrierten Halbleiterschaltung

Info

Publication number
DE60127052D1
DE60127052D1 DE60127052T DE60127052T DE60127052D1 DE 60127052 D1 DE60127052 D1 DE 60127052D1 DE 60127052 T DE60127052 T DE 60127052T DE 60127052 T DE60127052 T DE 60127052T DE 60127052 D1 DE60127052 D1 DE 60127052D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
semiconductor integrated
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60127052T
Other languages
English (en)
Other versions
DE60127052T2 (de
Inventor
Tadayoshi Takada
Osamu Kitamura
Shigeaki Okawa
Hirotsugu Hata
Chikao Fujinuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Application granted granted Critical
Publication of DE60127052D1 publication Critical patent/DE60127052D1/de
Publication of DE60127052T2 publication Critical patent/DE60127052T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE60127052T 2000-09-07 2001-09-06 Herstellungsverfahren einer integrierten Halbleiterschaltung Expired - Fee Related DE60127052T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000271381 2000-09-07
JP2000271381A JP2002083876A (ja) 2000-09-07 2000-09-07 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
DE60127052D1 true DE60127052D1 (de) 2007-04-19
DE60127052T2 DE60127052T2 (de) 2007-12-13

Family

ID=18757679

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60127052T Expired - Fee Related DE60127052T2 (de) 2000-09-07 2001-09-06 Herstellungsverfahren einer integrierten Halbleiterschaltung

Country Status (7)

Country Link
US (1) US6528379B2 (de)
EP (1) EP1187194B1 (de)
JP (1) JP2002083876A (de)
KR (1) KR100582146B1 (de)
CN (1) CN1213474C (de)
DE (1) DE60127052T2 (de)
TW (1) TW503572B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100854077B1 (ko) * 2002-05-28 2008-08-25 페어차일드코리아반도체 주식회사 웨이퍼 본딩을 이용한 ｓｏｉ 기판 제조 방법과 이 ｓｏｉ기판을 사용한 상보형 고전압 바이폴라 트랜지스터 제조방법
KR100477396B1 (ko) * 2002-09-04 2005-03-28 한국전기연구원 금속 게이트 전극을 갖는 탄화규소 모스펫 소자 및 그제조방법
KR100474859B1 (ko) * 2002-11-05 2005-03-11 매그나칩 반도체 유한회사 반도체 소자의 소자 분리막 형성 방법
JP2006270009A (ja) * 2005-02-25 2006-10-05 Seiko Epson Corp 電子装置の製造方法
CN100457674C (zh) * 2006-12-02 2009-02-04 桂林工学院 粉煤灰红砂岩烧结的建筑用砖及其制备工艺
JP6084226B2 (ja) * 2011-10-14 2017-02-22 ディフテック レーザーズ インコーポレイテッド 基板上に位置付けられる平坦化された半導体粒子
US9209019B2 (en) 2013-09-05 2015-12-08 Diftek Lasers, Inc. Method and system for manufacturing a semi-conducting backplane
US9455307B2 (en) 2011-10-14 2016-09-27 Diftek Lasers, Inc. Active matrix electro-optical device and method of making thereof
US10312310B2 (en) 2016-01-19 2019-06-04 Diftek Lasers, Inc. OLED display and method of fabrication thereof
CN109643729B (zh) * 2016-09-01 2022-03-29 美国亚德诺半导体公司 用于pga或pgia的低电容开关
US10707330B2 (en) * 2018-02-15 2020-07-07 Globalfoundries Inc. Semiconductor device with interconnect to source/drain
CN110544689B (zh) * 2019-08-29 2021-07-20 华南理工大学 射频前端模块中有源器件和无源单晶器件及单片集成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4146905A (en) * 1974-06-18 1979-03-27 U.S. Philips Corporation Semiconductor device having complementary transistor structures and method of manufacturing same
GB2060252B (en) * 1979-09-17 1984-02-22 Nippon Telegraph & Telephone Mutually isolated complementary semiconductor elements
JPS56131942A (en) * 1980-03-19 1981-10-15 Fujitsu Ltd Manufacture of semiconductor device
JPS6081839A (ja) * 1983-10-12 1985-05-09 Fujitsu Ltd 半導体装置の製造方法
JPH0783050B2 (ja) * 1985-06-21 1995-09-06 株式会社東芝 半導体素子の製造方法
JPH11354535A (ja) 1998-06-11 1999-12-24 Sony Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US6528379B2 (en) 2003-03-04
JP2002083876A (ja) 2002-03-22
DE60127052T2 (de) 2007-12-13
CN1213474C (zh) 2005-08-03
US20020028551A1 (en) 2002-03-07
KR20020020215A (ko) 2002-03-14
EP1187194B1 (de) 2007-03-07
KR100582146B1 (ko) 2006-05-23
EP1187194A2 (de) 2002-03-13
TW503572B (en) 2002-09-21
EP1187194A3 (de) 2004-11-10
CN1341961A (zh) 2002-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HOEFER & PARTNER, 81543 MUENCHEN

8339 Ceased/non-payment of the annual fee