DE60238583D1 - Herstellungsverfahren eines Halbleiterbauelements - Google Patents

Herstellungsverfahren eines Halbleiterbauelements

Info

Publication number
DE60238583D1
DE60238583D1 DE60238583T DE60238583T DE60238583D1 DE 60238583 D1 DE60238583 D1 DE 60238583D1 DE 60238583 T DE60238583 T DE 60238583T DE 60238583 T DE60238583 T DE 60238583T DE 60238583 D1 DE60238583 D1 DE 60238583D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60238583T
Other languages
English (en)
Inventor
Takada Kazuhiko
Sugatani Shinji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Application granted granted Critical
Publication of DE60238583D1 publication Critical patent/DE60238583D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE60238583T 2001-06-26 2002-03-04 Herstellungsverfahren eines Halbleiterbauelements Expired - Lifetime DE60238583D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001192825A JP2003007869A (ja) 2001-06-26 2001-06-26 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE60238583D1 true DE60238583D1 (de) 2011-01-27

Family

ID=19031219

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60238583T Expired - Lifetime DE60238583D1 (de) 2001-06-26 2002-03-04 Herstellungsverfahren eines Halbleiterbauelements

Country Status (7)

Country Link
US (1) US6649965B2 (de)
EP (1) EP1276148B1 (de)
JP (1) JP2003007869A (de)
KR (1) KR100818873B1 (de)
CN (1) CN1189947C (de)
DE (1) DE60238583D1 (de)
TW (1) TW531895B (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020091982A (ko) * 2001-06-01 2002-12-11 삼성전자 주식회사 얕은 트렌치 소자분리 구조를 가지는 비휘발성 메모리소자 및 그 제조방법
US6559008B2 (en) * 2001-10-04 2003-05-06 Hynix Semiconductor America, Inc. Non-volatile memory cells with selectively formed floating gate
AU2003242901A1 (en) * 2002-06-20 2004-01-06 Koninklijke Philips Electronics N.V. Conductive spacers extended floating gates
KR100454135B1 (ko) * 2002-10-10 2004-10-26 삼성전자주식회사 비휘발성 기억소자의 형성방법
ITTO20020997A1 (it) * 2002-11-15 2004-05-16 St Microelectronics Srl Procedimento autoalllineato per la fabbricazione di
KR100471575B1 (ko) * 2002-12-26 2005-03-10 주식회사 하이닉스반도체 플래시 메모리 소자의 제조방법
JP2004235313A (ja) * 2003-01-29 2004-08-19 Renesas Technology Corp 半導体装置
JP2005197363A (ja) * 2004-01-05 2005-07-21 Toshiba Corp 不揮発性半導体メモリセル及びその製造方法
KR100734261B1 (ko) * 2004-05-21 2007-07-02 삼성전자주식회사 커플링비를 향상시킬 수 있는 비휘발성 반도체 메모리 소자
JP4671775B2 (ja) * 2004-06-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4488947B2 (ja) 2005-04-08 2010-06-23 株式会社東芝 不揮発性半導体記憶装置の製造方法
KR100689203B1 (ko) * 2005-04-22 2007-03-08 경북대학교 산학협력단 플래시 메모리 소자
US7348256B2 (en) * 2005-07-25 2008-03-25 Atmel Corporation Methods of forming reduced electric field DMOS using self-aligned trench isolation
JP2007134598A (ja) * 2005-11-11 2007-05-31 Toshiba Corp 半導体装置の製造方法
JP2007165862A (ja) * 2005-11-15 2007-06-28 Toshiba Corp 半導体装置の製造方法
JP4745039B2 (ja) * 2005-12-02 2011-08-10 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
KR100740612B1 (ko) * 2006-02-15 2007-07-18 삼성전자주식회사 반도체 장치 및 그 형성 방법
JP4521366B2 (ja) * 2006-02-22 2010-08-11 株式会社東芝 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
JP2007258510A (ja) * 2006-03-24 2007-10-04 Toshiba Corp 半導体装置の製造方法
US7998809B2 (en) * 2006-05-15 2011-08-16 Micron Technology, Inc. Method for forming a floating gate using chemical mechanical planarization
US7675104B2 (en) * 2006-07-31 2010-03-09 Spansion Llc Integrated circuit memory system employing silicon rich layers
KR101169396B1 (ko) * 2006-12-22 2012-07-30 삼성전자주식회사 비휘발성 메모리 소자 및 그 동작 방법
KR100814408B1 (ko) * 2007-04-04 2008-03-18 삼성전자주식회사 비휘발성 메모리 소자 및 이의 제조 방법.
KR101108711B1 (ko) * 2007-08-23 2012-01-30 삼성전자주식회사 액티브 패턴 구조물 및 그 형성 방법, 비휘발성 메모리소자 및 그 제조 방법.
US8148230B2 (en) 2009-07-15 2012-04-03 Sandisk 3D Llc Method of making damascene diodes using selective etching methods
US7927977B2 (en) * 2009-07-15 2011-04-19 Sandisk 3D Llc Method of making damascene diodes using sacrificial material
US20110133266A1 (en) * 2009-12-03 2011-06-09 Sanh Tang Flash Memory Having a Floating Gate in the Shape of a Curved Section
KR20120024199A (ko) * 2010-09-06 2012-03-14 주식회사 유진테크 반도체 소자의 제조 방법
US9082654B2 (en) 2013-05-30 2015-07-14 Rohm Co., Ltd. Method of manufacturing non-volatile memory cell with simplified step of forming floating gate
JP2017224857A (ja) * 2017-09-13 2017-12-21 ローム株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344034A (ja) 1989-07-12 1991-02-25 Sony Corp 多層配線形成方法
JPH04192422A (ja) 1990-11-27 1992-07-10 Canon Inc 半導体装置およびその製造方法
JPH0536991A (ja) * 1991-07-31 1993-02-12 Nippon Steel Corp 半導体記憶装置
JPH09505945A (ja) * 1994-09-13 1997-06-10 マクロニクス インターナショナル カンパニイ リミテッド フラッシュ・イーピーロム・トランジスタ・アレイおよびその製造方法
JP3991383B2 (ja) 1997-03-07 2007-10-17 ソニー株式会社 半導体記憶装置及びその製造方法
JPH11163304A (ja) 1997-11-28 1999-06-18 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JPH11297863A (ja) * 1998-04-10 1999-10-29 Nec Corp コンタクトレスアレイ構成の不揮発性メモリおよびその製造方法
JP2000012813A (ja) 1998-04-22 2000-01-14 Sony Corp 半導体不揮発性記憶装置およびその製造方法
KR100316709B1 (ko) * 1998-07-13 2001-12-12 윤종용 불휘발성 메모리 장치 제조 방법
JP4237344B2 (ja) * 1998-09-29 2009-03-11 株式会社東芝 半導体装置及びその製造方法
KR100318683B1 (ko) * 1998-12-17 2001-12-28 윤종용 산화막/질화막/산화막 유전층의 형성방법
JP3875455B2 (ja) * 1999-04-28 2007-01-31 株式会社東芝 半導体装置の製造方法
KR100304710B1 (ko) * 1999-08-30 2001-11-01 윤종용 셀 어레이 영역내에 벌크 바이어스 콘택 구조를 구비하는 비휘발성 메모리소자
JP3785003B2 (ja) * 1999-09-20 2006-06-14 株式会社東芝 不揮発性半導体記憶装置の製造方法
FR2799050A1 (fr) * 1999-09-24 2001-03-30 St Microelectronics Sa Procede de fabrication de points memoire eprom a surface reduite
KR100331556B1 (ko) * 1999-10-05 2002-04-06 윤종용 자기 정렬된 트랜치를 갖는 플레시 메모리 및 그 제조방법
JP3878374B2 (ja) * 1999-12-01 2007-02-07 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
EP1276148A3 (de) 2007-12-26
KR100818873B1 (ko) 2008-04-01
CN1189947C (zh) 2005-02-16
EP1276148B1 (de) 2010-12-15
JP2003007869A (ja) 2003-01-10
EP1276148A2 (de) 2003-01-15
TW531895B (en) 2003-05-11
KR20030001230A (ko) 2003-01-06
US6649965B2 (en) 2003-11-18
US20020195645A1 (en) 2002-12-26
CN1393937A (zh) 2003-01-29

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Legal Events

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