ITTO20020997A1 - Procedimento autoalllineato per la fabbricazione di - Google Patents

Procedimento autoalllineato per la fabbricazione di

Info

Publication number
ITTO20020997A1
ITTO20020997A1 IT000997A ITTO20020997A ITTO20020997A1 IT TO20020997 A1 ITTO20020997 A1 IT TO20020997A1 IT 000997 A IT000997 A IT 000997A IT TO20020997 A ITTO20020997 A IT TO20020997A IT TO20020997 A1 ITTO20020997 A1 IT TO20020997A1
Authority
IT
Italy
Prior art keywords
self
manufacture
aligned
procedure
aligned procedure
Prior art date
Application number
IT000997A
Other languages
English (en)
Inventor
Roberto Bez
Alessandro Grossi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000997A priority Critical patent/ITTO20020997A1/it
Priority to EP03104191A priority patent/EP1420442A3/en
Priority to US10/713,538 priority patent/US7468535B2/en
Publication of ITTO20020997A1 publication Critical patent/ITTO20020997A1/it
Priority to US12/006,706 priority patent/US7772084B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT000997A 2002-11-15 2002-11-15 Procedimento autoalllineato per la fabbricazione di ITTO20020997A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT000997A ITTO20020997A1 (it) 2002-11-15 2002-11-15 Procedimento autoalllineato per la fabbricazione di
EP03104191A EP1420442A3 (en) 2002-11-15 2003-11-13 Process for self-aligned manufacture of integrated electronic devices
US10/713,538 US7468535B2 (en) 2002-11-15 2003-11-14 Self-aligned integrated electronic devices
US12/006,706 US7772084B2 (en) 2002-11-15 2008-01-04 Process for self-aligned manufacture of integrated electronic devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000997A ITTO20020997A1 (it) 2002-11-15 2002-11-15 Procedimento autoalllineato per la fabbricazione di

Publications (1)

Publication Number Publication Date
ITTO20020997A1 true ITTO20020997A1 (it) 2004-05-16

Family

ID=32170757

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000997A ITTO20020997A1 (it) 2002-11-15 2002-11-15 Procedimento autoalllineato per la fabbricazione di

Country Status (3)

Country Link
US (2) US7468535B2 (it)
EP (1) EP1420442A3 (it)
IT (1) ITTO20020997A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7306552B2 (en) * 2004-12-03 2007-12-11 Samsung Electronics Co., Ltd. Semiconductor device having load resistor and method of fabricating the same
JP2012043856A (ja) * 2010-08-16 2012-03-01 Toshiba Corp 半導体装置およびその製造方法
KR101770585B1 (ko) * 2010-09-03 2017-08-24 삼성전자주식회사 저항 어레이 및 이를 포함하는 반도체 장치
US10622073B2 (en) * 2018-05-11 2020-04-14 Texas Instruments Incorporated Integrated circuit including vertical capacitors

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970000717B1 (ko) * 1993-07-27 1997-01-18 현대전자산업 주식회사 캐패시터 제조방법
US6090661A (en) * 1998-03-19 2000-07-18 Lsi Logic Corporation Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls
US6403421B1 (en) * 1998-04-22 2002-06-11 Sony Corporation Semiconductor nonvolatile memory device and method of producing the same
US6468855B2 (en) * 1998-08-14 2002-10-22 Monolithic System Technology, Inc. Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
US6420729B2 (en) * 1999-03-16 2002-07-16 Texas Instruments Incorporated Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics
KR100319618B1 (ko) * 1999-04-20 2002-01-05 김영환 반도체 소자의 커패시터 및 제조방법
KR100314473B1 (ko) * 1999-12-23 2001-11-15 한신혁 반도체 소자 제조 방법
US6448606B1 (en) 2000-02-24 2002-09-10 Advanced Micro Devices, Inc. Semiconductor with increased gate coupling coefficient
US6323104B1 (en) * 2000-03-01 2001-11-27 Micron Technology, Inc. Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry
US6362071B1 (en) * 2000-04-05 2002-03-26 Motorola, Inc. Method for forming a semiconductor device with an opening in a dielectric layer
JP2002064157A (ja) * 2000-06-09 2002-02-28 Toshiba Corp 半導体メモリ集積回路及びその製造方法
US6420749B1 (en) * 2000-06-23 2002-07-16 International Business Machines Corporation Trench field shield in trench isolation
JP2002043384A (ja) * 2000-07-24 2002-02-08 Mitsubishi Electric Corp 層間絶縁膜の評価用ｔｅｇを含む半導体装置とその製造方法及び層間絶縁膜の評価方法
KR100335999B1 (ko) * 2000-07-25 2002-05-08 윤종용 자기정렬된 셸로우 트렌치 소자분리 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법
JP2003007869A (ja) * 2001-06-26 2003-01-10 Fujitsu Ltd 半導体装置及びその製造方法
US6737333B2 (en) * 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
US6696742B2 (en) * 2001-10-16 2004-02-24 Infineon Technologies Ag Semiconductor memory device
US6682977B2 (en) * 2002-02-11 2004-01-27 Winbond Electronics Corporation Method for fabricating a gate structure of a flash memory
KR101110191B1 (ko) * 2002-06-19 2012-02-15 쌘디스크 코포레이션 스케일 낸드용 인접셀들 사이의 크로스 커플링을 실드하기위한 딥 워드라인 트렌치
US6974708B2 (en) * 2004-04-08 2005-12-13 Headway Technologies, Inc. Oxidation structure/method to fabricate a high-performance magnetic tunneling junction MRAM

Also Published As

Publication number Publication date
US20080108200A1 (en) 2008-05-08
US7468535B2 (en) 2008-12-23
US7772084B2 (en) 2010-08-10
EP1420442A2 (en) 2004-05-19
US20040173869A1 (en) 2004-09-09
EP1420442A3 (en) 2004-12-22

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