ITTO20020997A1 - Procedimento autoalllineato per la fabbricazione di - Google Patents
Procedimento autoalllineato per la fabbricazione diInfo
- Publication number
- ITTO20020997A1 ITTO20020997A1 IT000997A ITTO20020997A ITTO20020997A1 IT TO20020997 A1 ITTO20020997 A1 IT TO20020997A1 IT 000997 A IT000997 A IT 000997A IT TO20020997 A ITTO20020997 A IT TO20020997A IT TO20020997 A1 ITTO20020997 A1 IT TO20020997A1
- Authority
- IT
- Italy
- Prior art keywords
- self
- manufacture
- aligned
- procedure
- aligned procedure
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT000997A ITTO20020997A1 (it) | 2002-11-15 | 2002-11-15 | Procedimento autoalllineato per la fabbricazione di |
EP03104191A EP1420442A3 (en) | 2002-11-15 | 2003-11-13 | Process for self-aligned manufacture of integrated electronic devices |
US10/713,538 US7468535B2 (en) | 2002-11-15 | 2003-11-14 | Self-aligned integrated electronic devices |
US12/006,706 US7772084B2 (en) | 2002-11-15 | 2008-01-04 | Process for self-aligned manufacture of integrated electronic devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT000997A ITTO20020997A1 (it) | 2002-11-15 | 2002-11-15 | Procedimento autoalllineato per la fabbricazione di |
Publications (1)
Publication Number | Publication Date |
---|---|
ITTO20020997A1 true ITTO20020997A1 (it) | 2004-05-16 |
Family
ID=32170757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT000997A ITTO20020997A1 (it) | 2002-11-15 | 2002-11-15 | Procedimento autoalllineato per la fabbricazione di |
Country Status (3)
Country | Link |
---|---|
US (2) | US7468535B2 (it) |
EP (1) | EP1420442A3 (it) |
IT (1) | ITTO20020997A1 (it) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7306552B2 (en) * | 2004-12-03 | 2007-12-11 | Samsung Electronics Co., Ltd. | Semiconductor device having load resistor and method of fabricating the same |
JP2012043856A (ja) * | 2010-08-16 | 2012-03-01 | Toshiba Corp | 半導体装置およびその製造方法 |
KR101770585B1 (ko) * | 2010-09-03 | 2017-08-24 | 삼성전자주식회사 | 저항 어레이 및 이를 포함하는 반도체 장치 |
US10622073B2 (en) | 2018-05-11 | 2020-04-14 | Texas Instruments Incorporated | Integrated circuit including vertical capacitors |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970000717B1 (ko) * | 1993-07-27 | 1997-01-18 | 현대전자산업 주식회사 | 캐패시터 제조방법 |
US6090661A (en) * | 1998-03-19 | 2000-07-18 | Lsi Logic Corporation | Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls |
US6403421B1 (en) * | 1998-04-22 | 2002-06-11 | Sony Corporation | Semiconductor nonvolatile memory device and method of producing the same |
US6468855B2 (en) * | 1998-08-14 | 2002-10-22 | Monolithic System Technology, Inc. | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
US6420729B2 (en) * | 1999-03-16 | 2002-07-16 | Texas Instruments Incorporated | Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics |
KR100319618B1 (ko) * | 1999-04-20 | 2002-01-05 | 김영환 | 반도체 소자의 커패시터 및 제조방법 |
KR100314473B1 (ko) * | 1999-12-23 | 2001-11-15 | 한신혁 | 반도체 소자 제조 방법 |
US6448606B1 (en) | 2000-02-24 | 2002-09-10 | Advanced Micro Devices, Inc. | Semiconductor with increased gate coupling coefficient |
US6323104B1 (en) * | 2000-03-01 | 2001-11-27 | Micron Technology, Inc. | Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry |
US6362071B1 (en) * | 2000-04-05 | 2002-03-26 | Motorola, Inc. | Method for forming a semiconductor device with an opening in a dielectric layer |
JP2002064157A (ja) * | 2000-06-09 | 2002-02-28 | Toshiba Corp | 半導体メモリ集積回路及びその製造方法 |
US6420749B1 (en) * | 2000-06-23 | 2002-07-16 | International Business Machines Corporation | Trench field shield in trench isolation |
JP2002043384A (ja) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | 層間絶縁膜の評価用tegを含む半導体装置とその製造方法及び層間絶縁膜の評価方法 |
KR100335999B1 (ko) * | 2000-07-25 | 2002-05-08 | 윤종용 | 자기정렬된 셸로우 트렌치 소자분리 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법 |
JP2003007869A (ja) * | 2001-06-26 | 2003-01-10 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6737333B2 (en) * | 2001-07-03 | 2004-05-18 | Texas Instruments Incorporated | Semiconductor device isolation structure and method of forming |
US6696742B2 (en) * | 2001-10-16 | 2004-02-24 | Infineon Technologies Ag | Semiconductor memory device |
US6682977B2 (en) * | 2002-02-11 | 2004-01-27 | Winbond Electronics Corporation | Method for fabricating a gate structure of a flash memory |
EP1514309B1 (en) * | 2002-06-19 | 2013-11-27 | SanDisk Technologies Inc. | Deep wordline trench to shield cross coupling between adjacent cells of nand memory |
US6974708B2 (en) * | 2004-04-08 | 2005-12-13 | Headway Technologies, Inc. | Oxidation structure/method to fabricate a high-performance magnetic tunneling junction MRAM |
-
2002
- 2002-11-15 IT IT000997A patent/ITTO20020997A1/it unknown
-
2003
- 2003-11-13 EP EP03104191A patent/EP1420442A3/en not_active Withdrawn
- 2003-11-14 US US10/713,538 patent/US7468535B2/en not_active Expired - Lifetime
-
2008
- 2008-01-04 US US12/006,706 patent/US7772084B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1420442A2 (en) | 2004-05-19 |
US7772084B2 (en) | 2010-08-10 |
US20080108200A1 (en) | 2008-05-08 |
US20040173869A1 (en) | 2004-09-09 |
US7468535B2 (en) | 2008-12-23 |
EP1420442A3 (en) | 2004-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60316652D1 (de) | Endoskop | |
ITTO20030629A1 (it) | Procedimento di realizzazione di collegamenti ad | |
ITTO20030269A1 (it) | Procedimento per la fabbricazione di un dispositivo | |
DE60327274D1 (de) | Selbstjustiertes Mikro-Scharnier | |
ES1053304Y (es) | Disposicion mejorada para la fijacion de fregaderos. | |
ITMI20022704A1 (it) | Procedimento per la produzione di mesitilene e durene. | |
ITMI20020933A0 (it) | Procedimento per la sintesi di clopidogrel | |
ITMI20010954A0 (it) | Procedimento di iodurazione | |
FR2837224B1 (fr) | Bonde traitante | |
ITMI20031994A1 (it) | Procedimento per la preparazione di fludarabina fosfato | |
ITTO20020997A1 (it) | Procedimento autoalllineato per la fabbricazione di | |
ITMI20030346A1 (it) | Procedimento per la produzione di mesitilene. | |
ITMI20030479A1 (it) | Procedimento per la preparazione di un ciano-isobenzofurano. | |
ITMI20030018A1 (it) | Procedimento per la preparazione di composti mono- | |
ITMI20020295A0 (it) | Procedimento di pacciamatura | |
IT1338456B1 (it) | Procedimento per la preparazione di alchiluree da o ,d-dimetil ditiocarbonato | |
ITMI20030019A1 (it) | Procedimento per la preparazione di composti mono- | |
ITVR20030088A1 (it) | Procedimento per la realizzazione di fasce anti-implosione per cinescopi | |
ITTO20020465A0 (it) | Procedimento per la preparazione di doxofillina. | |
ITMI20020620A1 (it) | Procedimento per la preparazione di alchil-benzoati per esterificazione di benzoil-fluoruri | |
ITMI20021134A0 (it) | Procedimento per la produzione di propilene | |
ITRM20010770A1 (it) | Procedimento per la produzione di piridinolcarbammato. | |
ITMI20012131A0 (it) | Procedimento per la preparazione di alo-benzonitrili | |
ITVA20020048A1 (it) | Procedimento per la realizzazione di componenti di | |
ITTO20030055A1 (it) | Procedimento per la fabbricazione di tappeti |