DE69131723T2 - Integrierte Schaltung mit verbesserter Speisespannungssteuerung - Google Patents

Integrierte Schaltung mit verbesserter Speisespannungssteuerung

Info

Publication number
DE69131723T2
DE69131723T2 DE69131723T DE69131723T DE69131723T2 DE 69131723 T2 DE69131723 T2 DE 69131723T2 DE 69131723 T DE69131723 T DE 69131723T DE 69131723 T DE69131723 T DE 69131723T DE 69131723 T2 DE69131723 T2 DE 69131723T2
Authority
DE
Germany
Prior art keywords
voltage
circuit
transistor
supply voltage
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131723T
Other languages
German (de)
English (en)
Other versions
DE69131723D1 (de
Inventor
Narasimhan Iyengar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69131723D1 publication Critical patent/DE69131723D1/de
Application granted granted Critical
Publication of DE69131723T2 publication Critical patent/DE69131723T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004Voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE69131723T 1990-04-27 1991-03-28 Integrierte Schaltung mit verbesserter Speisespannungssteuerung Expired - Fee Related DE69131723T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/515,977 US5063304A (en) 1990-04-27 1990-04-27 Integrated circuit with improved on-chip power supply control

Publications (2)

Publication Number Publication Date
DE69131723D1 DE69131723D1 (de) 1999-11-25
DE69131723T2 true DE69131723T2 (de) 2000-06-08

Family

ID=24053590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131723T Expired - Fee Related DE69131723T2 (de) 1990-04-27 1991-03-28 Integrierte Schaltung mit verbesserter Speisespannungssteuerung

Country Status (5)

Country Link
US (2) US5063304A (enExample)
EP (1) EP0453813B1 (enExample)
JP (1) JPH0644774A (enExample)
KR (1) KR100248846B1 (enExample)
DE (1) DE69131723T2 (enExample)

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KR100200926B1 (ko) * 1996-08-29 1999-06-15 윤종용 내부전원전압 발생회로
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US5912856A (en) * 1996-12-30 1999-06-15 Hyundai Electronics Industries Co., Ltd. Internal voltage generating circuit in semiconductor memory device
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US5847591A (en) * 1997-03-31 1998-12-08 Siemens Aktiengesellschaft Voltage detection circuit and internal voltage clamp circuit
KR100253282B1 (ko) * 1997-04-01 2000-05-01 김영환 메모리소자의소모전력자동감소회로
JP3972414B2 (ja) * 1997-06-20 2007-09-05 ソニー株式会社 データ判定回路およびデータ判定方法
US5925913A (en) * 1997-08-25 1999-07-20 Advanced Micro Devices, Inc. System for enhancing the performance of a circuit by reducing the channel length of one or more transistors
US5942932A (en) * 1997-08-26 1999-08-24 Nanoamp Solutions, Inc. Circuit and method for preventing latch-up in a CMOS semiconductor device
JP3047869B2 (ja) * 1997-09-26 2000-06-05 日本電気株式会社 出力振幅調整回路
US5894215A (en) * 1997-10-30 1999-04-13 Xerox Corporation Shunt voltage regulator utilizing a floating reference voltage
JP3620636B2 (ja) * 1998-11-25 2005-02-16 株式会社村田製作所 積層セラミックコンデンサの選別方法
US6469517B1 (en) * 1998-11-25 2002-10-22 Murata Manufacturing Co., Ltd. Sorting method of monolithic ceramic capacitors based on insulation resistance
FR2794867B1 (fr) * 1999-06-08 2001-08-10 St Microelectronics Sa Circuit de detection et de memorisation d'une surtension
JP3551858B2 (ja) 1999-09-14 2004-08-11 日本電気株式会社 半導体メモリ装置
IT1314090B1 (it) * 1999-11-26 2002-12-04 St Microelectronics Srl Generatore ad impulsi indipendente dalla tensione di alimentazione.
US6282130B1 (en) * 2000-06-09 2001-08-28 Sandisk Corporation EEPROM memory chip with multiple use pinouts
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US6968157B2 (en) * 2001-08-22 2005-11-22 University Of Maryland System and method for protecting devices from interference signals
KR100454118B1 (ko) * 2001-10-23 2004-10-26 삼성전자주식회사 반도체 메모리 장치 및 그것의 테스트 방법
US6731486B2 (en) 2001-12-19 2004-05-04 Fairchild Semiconductor Corporation Output-powered over-voltage protection circuit
JP3947044B2 (ja) 2002-05-31 2007-07-18 富士通株式会社 入出力バッファ
KR100555509B1 (ko) * 2003-07-23 2006-03-03 삼성전자주식회사 선택적 전압 레퍼런스로 소모 전력을 절감하는 내부 전압변환기, 이를 구비한 반도체 장치 및 그 방법
JP4549711B2 (ja) * 2004-03-29 2010-09-22 ルネサスエレクトロニクス株式会社 半導体回路装置
KR20070082230A (ko) * 2006-02-15 2007-08-21 삼성전자주식회사 액정 표시 장치용 테스트 장치 및 그 방법
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US10859610B2 (en) * 2016-04-27 2020-12-08 The University Of Bristol Voltage detector and voltage detector system

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Also Published As

Publication number Publication date
KR910019199A (ko) 1991-11-30
JPH0644774A (ja) 1994-02-18
DE69131723D1 (de) 1999-11-25
EP0453813B1 (en) 1999-10-20
US5063304B1 (enExample) 1993-02-23
US5300824A (en) 1994-04-05
EP0453813A2 (en) 1991-10-30
KR100248846B1 (ko) 2000-03-15
EP0453813A3 (en) 1992-08-19
US5063304A (en) 1991-11-05

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee