DE112017003172T5

DE112017003172T5 - Formation of an air gap spacer for nanoscale semiconductor devices

Info

Publication number: DE112017003172T5
Application number: DE112017003172.9T
Authority: DE
Inventors: Van Nguyen Son; Tenko Yamashita; Kangguo Cheng; Jasper Haigh Thomas Jr; Chanro Park; Eric Liniger; Juntao Li; Sanjay Mehta
Original assignee: International Business Machines Corp
Current assignee: Tessera Inc
Priority date: 2016-08-09
Filing date: 2017-07-21
Publication date: 2019-03-28
Also published as: WO2018029556A1; US20180047617A1; US20180261494A1; GB2567363B; US10115629B2; CN109478534A; US9892961B1; US20180047615A1; US20190267279A1; US10418277B2; GB2567363A; GB201901614D0; JP2019527933A

Abstract

Semiconductor devices having air gap spacers formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods of making such air gap spacers. For example, one method includes forming a first metal structure and a second metal structure on a substrate, wherein the first and second metal structures are disposed adjacent each other with insulating material disposed between the first and second metal structures. The insulating material is etched to form a recess between the first and second metal structures. A layer of dielectric material is deposited over the first and second metal structures by a pinch-off deposition process to form an air gap in the recess between the first and second metal structures, wherein a portion of the air gap overlies an upper surface of at least one of the first metal structure and the first second metal structure extends.

Description

Technical part
The art is generally related to semiconductor fabrication, and more particularly to methods of fabricating air gap spacers for semiconductor devices.
background
As semiconductor manufacturing technology evolves toward smaller design rules and higher integration densities, separation between adjacent integrated circuit structures is becoming increasingly smaller. This can lead to undesirable capacitive coupling between adjacent integrated circuit structures, such as e.g. adjacent metal lines in BEOL (back-end-of-line) interconnect structures, adjacent contacts (eg MOL (middle-of-the-line) device contacts) of FEOL (front-end-of-line) devices, etc. These structurally related parasitic capacitances can lead to a degradation of the performance of semiconductor devices. For example, capacitive coupling between transistor contacts may lead to increased parasitic capacitances between the gate and source or gate and drain which affect the operating speed of a transistor, increase the power consumption of an integrated circuit, etc. Moreover, undesirable capacitive coupling between adjacent metal lines of a BEOL device may Structure lead to increased resistance-capacitance delay (or latency), crosstalk, increased dynamic power dissipation in the interconnect stack, and so forth.
In an effort to reduce parasitic coupling between adjacent conductive structures, the semiconductor industry is in the use of low-k and ultra-low-k dielectric (ultra low-k, ULK) dielectrics (instead of conventional SiO 2 (k = 4.0)) as insulating materials for MOL and BEOL layers of ultra-large-scale integration (ULSI) integrated circuits. However, the advent of low-k dielectrics coupled with aggressive scaling has led to critical challenges in the long-term reliability of such low-k materials. For example, low-k TDDB (time-dependent dielectric breakdown) is generally considered a critical problem because low-k materials generally have a lower intrinsic breakdown strength than conventional SiO 2 dielectrics. In general, TDDB refers to the loss of insulating properties of a dielectric over time when exposed to stress / current and temperature stresses. TDDB causes an increase in the leakage current and thus affects the performance in nanoscale integrated circuits.
Summary
Embodiments of the invention include air gap spacer semiconductor devices formed as part of BEOL or MOL layers of the semiconductor devices, and methods of fabricating air gap spacers as part of BEOL and MOL layers of a semiconductor device.
For example, a method of fabricating a semiconductor device includes forming a first metal structure and a second metal structure on a substrate, wherein the first and second metal structures are disposed adjacent to one another with insulating material disposed between the first and second metal structures. The insulating material is etched to form a recess between the first and second metal structures. A layer of dielectric material is deposited over the first and second metal structures to form an air gap in the recess between the first and second metal structures, wherein a portion of the air gap extends over an upper surface of at least one of the first metal structure and the second metal structure.
In one embodiment, the first metal structure includes a first metal line formed in a dielectric interlayer of a BEOL interconnect structure, and the second metal structure includes a second metal line formed in the ILD layer of the BEOL interconnect structure.
In a further embodiment, the first metal structure has a component contact and the second metal structure has a gate structure of a transistor. In one embodiment, the device contact is higher than the gate structure, and the portion of the air gap extends beyond the gate structure and below an upper surface of the device contact.
Further embodiments are described in the following detailed description of embodiments, which is to be read in conjunction with the accompanying drawings.
list of figures

1A and 1B 13 are schematic views of a semiconductor device having air gap spacers integrally formed in a BEOL structure of the semiconductor device according to an embodiment of the invention.
The 2A and 2 B illustrate schematically improvements in TDDB reliability as well as reduced capacitive coupling between metal lines of a BEOL structure realized with air gap structures formed by a pinch-off deposition method according to embodiments of the invention compared to air gap structures formed by conventional methods.
3 FIG. 15 is a schematic side cross-sectional view of a semiconductor device having air gap spacers integrally formed in a BEOL structure of the semiconductor device according to another embodiment of the invention. FIG.
4 to 10 schematically illustrate a method of manufacturing the semiconductor device of 1A according to an embodiment of the invention, wherein:
4 Fig. 12 is a schematic side cross-sectional view of the semiconductor device in an intermediate stage of fabrication in which a pattern of openings is formed in an ILD layer (inter-layer dielectric);
5 a schematic side cross-section of the semiconductor device of 4 after depositing a uniform layer of lining material and depositing a layer of metallic material to fill the openings in the ILD layer;
6 a schematic side cross-section of the semiconductor device of 5 after planarizing the surface of the semiconductor structure down to the ILD layer to form a metal wiring layer;
7 a schematic side cross-section of the semiconductor device of 6 after forming protective caps on metal lines of the metal wiring layer;
8th a schematic side cross-section of the semiconductor device of 7 after the etching of the ILD layer, to form recesses between metal lines of the metal wiring layer;
9 a schematic side cross-section of the semiconductor device of 8th after depositing a uniform layer of insulating material, to form an insulating liner covering exposed surfaces of the metal wiring layer and the ILD layer; and
10 a schematic side cross-section of the semiconductor device of 9 which illustrates a process of depositing a dielectric material using a non-uniform deposition process to cause pinch regions to begin to form in the deposited dielectric material over the recesses between the metal lines of the metal wiring layer.
11 FIG. 12 is a schematic side cross-sectional view of a semiconductor device having air gap spacers integrally formed in a FEOL / MOL structure of the semiconductor device according to another embodiment of the invention.
12 to 19 schematically illustrate a method of manufacturing the semiconductor device of 11 according to an embodiment of the invention, wherein:
12 Fig. 12 is a schematic cross section of the semiconductor device in an intermediate stage of fabrication in which vertical transistor structures are formed on a semiconductor substrate;
13 a schematic side cross-section of the semiconductor device of 12 after patterning a dielectric pre-metal layer to form contact openings between gate structures of the vertical transistor structures;
14 a schematic side cross-section of the semiconductor device of 13 after forming a uniform liner layer over the surface of the semiconductor device, to line the contact openings with a liner material;
15 a schematic side cross-section of the semiconductor device of 14 after a layer of metallic material has been deposited to fill the contact openings with metallic material and the surface of the semiconductor device has been planarized to form MOL device contacts;
16 a side cross-section of the semiconductor device of 15 after recovering gate capping layers and sidewall spacers of the gate structures of the vertical transistor structures;
17 a schematic side cross-section of the semiconductor device of 16 after depositing a uniform layer of insulating material is an insulating lining which lines the exposed surfaces of the gate structures and the contacts of the MOL device;
18 a schematic side cross-section of the semiconductor device of 17 after depositing a dielectric material using a non-uniform deposition process, to form pinch regions, the air gaps form into recesses between the gate structures and MOL device contacts; and
19 a schematic side cross-section of the semiconductor device of 18 after the surface of the semiconductor device has been planarized down to the MOL device contacts and an ILD layer has been deposited as part of a first junction plane of a BEOL structure.

Detailed description
Embodiments will now be directed to semiconductor integrated circuit devices having air gap spacers formed as part of BEOL and / or MOL layers, and methods of fabricating air gap spacers as part of BEOL and / or MOL layers of a semiconductor integrated circuit device described in more detail. As discussed in more detail below, embodiments of the invention include methods of fabricating air gap spacers using "pinch-off" deposition techniques using certain dielectric materials and deposition techniques to control the size and shape of the formed air gap spacers, and thus the To optimize training of air gap spacers for a target application. The exemplary pinch-off deposition techniques for forming air gap spacers discussed herein provide improved TDDB reliability as well as optimal capacity reduction in BEOL and MOL layers of semiconductor integrated circuit devices.
It should be understood that the various layers, structures, and regions illustrated in the accompanying drawings are schematic representations that are not drawn to scale. Moreover, to simplify the explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly illustrated in a given drawing. This does not mean that layers, structures and regions not explicitly shown in the actual semiconductor structures are omitted.
Moreover, it should be understood that the embodiments described herein are not limited to the materials, features, and processing steps illustrated and described herein. In particular, with regard to the steps of semiconductor processing, it should be emphasized that the descriptions contained herein are not intended to cover all of the processing steps that may be required to form a functional semiconductor integrated circuit. Rather, certain processing steps commonly used in the fabrication of semiconductor devices, such as e.g. Wet cleaning and annealing steps, not described herein for reasons of economy of description.
In addition, the same or similar reference numbers are used throughout the drawings to refer to the same or similar features, elements or structures, so a detailed explanation of the same or similar features, elements or structures will not be repeated for each of the drawings. It should be understood that the terms "about," "about," or "substantially" as used herein in terms of thicknesses, widths, percentages, ranges, etc. are to be construed as being close or approximate, but not exact. For example, the terms "about," "about," or "substantially," as used herein, imply that there is a low error rate, such as 1% or less than the specified amount.
1A and 1B FIG. 12 are schematic views of a semiconductor device. FIG 100 with air gap spacers integrally formed in a BEOL structure of the semiconductor device according to an embodiment of the invention. 1A FIG. 12 is a schematic side cross-sectional view of the semiconductor device. FIG 100 along the line 1A - 1A in 1B , and 1B FIG. 12 is a schematic plan view of the semiconductor device. FIG 100 along a plane that is the line 1B - 1B includes, as in 1A shown. More precisely, that is 1A a schematic lateral cross section of the semiconductor device 100 in a XZ Level and 1B a plan view showing an arrangement of different elements within a XY Level shows how by the respective Cartesian XYZ Coordinates in the 1A and 1B clarified. It should be understood that the term "vertical" or "vertical direction" as used herein means a Z Direction of the Cartesian coordinates shown in the figures and the term "horizontal" or "horizontal direction" as used herein X Direction and / or Y Direction of the Cartesian coordinates shown in the figures.
In particular, illustrated 1A schematically the semiconductor device 100 , the A substratum 110 , a FEOL / MOL structure 120 and a BEOL structure 130 having. In one embodiment, the substrate 110 a semiconductor bulk substrate made of, for example, silicon or other types of semiconductor substrate materials such as germanium, a silicon germanium alloy, silicon carbide, a silicon germanium carbide alloy or compound semiconductor materials (eg III-V and II-VI ), which are often used in semiconductor mass production processes. Non-limiting examples of compound semiconductor materials are gallium arsenide, indium arsenide and indium phosphide. The thickness of the base substrate 100 varies depending on the application. In a further embodiment, the substrate 110 an SOI substrate (silicon on insulator) comprising an insulating layer (eg, an oxide layer) disposed between a semiconductor base substrate (eg, a silicon substrate) and an active semiconductor layer (eg, an active silicon layer) in which active circuit components (FIG. Eg field effect transistors) are formed as part of a FEOL layer.
In particular, the FEOL / MOL structure exhibits 120 one on the substrate 110 formed FEOL layer on. The FEOL layer includes various semiconductor devices and components disposed in or on the active surface of the semiconductor substrate 110 are designed to provide integrated circuits for a target application. For example, the FEOL layer includes FET devices (such as FinFET devices, planar MOSFET devices, etc.), bipolar transistors, diodes, capacitors, inductors, resistors, isolation devices, etc. that are in or on the active surface of the semiconductor substrate 110 are formed. In general, FEOL processes typically include preparing the substrate 110 (or wafers), forming isolation structures (eg, shallow trench isolation), forming device basins, patterning gate structures, forming spacers, forming source / drain regions (eg, by implantation), forming silicide contacts the source / drain regions, forming stress liners, etc.
The FEOL / MOL structure 120 also has a MOL layer formed on the FEOL layer. In general, the MOL layer consists of a PMD (pre-metal dielectric layer) and conductive contacts (eg, vias) formed in the PMD layer. The PMD layer is formed on the components and devices of the FEOL layer. A pattern of openings is formed in the PMD layer and the openings are filled with a conductive material, such as tungsten, to form conductive vias that are in electrical contact with device terminals (eg, source / drain areas, gate contacts, etc.). the integrated circuit of the FEOL layer. The conductive vias of the MOL layer provide electrical connections between the integrated circuit of the FEOL layer and a first metallization level of the BEOL structure 130 ago.
The BEOL structure 130 is on the FEOL / MOL structure 120 designed to connect the various components of the integrated circuit of the FEOL layer. As is known in the art, a BEOL structure has multiple dielectric layers and metallization levels embedded in the dielectric material. BEOL metallization includes horizontal wiring, interconnects, pads, etc., as well as vertical wiring in the form of conductive vias that form connections between different interconnect levels of the BEOL structure. A BEOL fabrication process includes successively depositing and patterning multiple layers of dielectric and metallic material to form a network of electrical connections between the FEOL devices and provide I / O connections to external components.
In the exemplary embodiment of 1A has the BEOL structure 130 a first connection level 140 and a second connection level 150 on. The first connection level 140 is generically illustrated and may include another low-k dielectric interlayer (ILD) as well as metal via and wiring planes (eg, copper damascene structures). Between the first connection level 140 and the second connection level 150 is a topcoat 148 educated. The cover layer 148 serves to insulate the metallization of the first interconnect level 140 of the dielectric material of the ILD layer 151 , For example, the topcoat serves 148 To improve the reliability of the connection and prevent the copper metallization in the ILD layer 151 the second connection level 150 penetrates. The cover layer 148 For example, any suitable insulating or dielectric material may include, but are not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), hydrogenated silicon carbide (SiCH), a multilayer stack with the same or different types of dielectrics, etc. The topcoat 148 can be deposited using standard deposition techniques such as chemical vapor deposition. The cover layer 148 can be formed to a thickness in a range of about 2 nm to about 60 nm.
The second connection level 150 has an ILD layer 151 and one in the ILD layer 151 formed metal wiring layer 152 on. The ILD layer 151 may be formed of any suitable dielectric material, including, but not limited to, silicon oxide (eg, SiO 2 ), SiN (eg, (Si 3 N 4), hydrogenated silicon carbon oxide (SiCOH), silicon-based low-k dielectrics, porous dielectrics, or other known ULK ( Ultra low k) dielectrics, the ILD layer 151 can be applied by known deposition techniques such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced CVD) or PVD (Physical Vapor Deposition). The thickness of the ILD layer 151 varies depending on the application and may, for example, have a thickness in a range from about 30 nm to about 200 nm.
The metal wiring layer 152 has a plurality of closely spaced metal lines 152 - 1 . 152 - 2 . 152 - 3 . 152 - 4 . 152 - 5 and 152 - 6 which are formed within trenches / openings in the ILD layer 151 structured and filled with metallic material to form the metal lines. The trenches / openings are with a uniform lining layer 153 which serves as a barrier diffusion layer to prevent migration of the metallic material (eg, Cu) into the ILD layer 151 and with an adhesive layer to ensure good adhesion to the metallic material (eg, Cu), to fill the trenches / openings in the ILD layer 151 and for forming the metal lines 152 - 1 , ..., 152 - 6 is used.
As in further 1A shown, the second connection level 150 also protective caps 154 on, which selectively on a top of the metal lines 152 - 1 . 152 - 2 . 152 - 3 . 152 - 4 . 152 - 5 and 152 - 6 are formed, a uniform insulating lining 155 containing the metal line layer 152 uniformly covers, and a dielectric cover layer 156 , which is deposited with a pinch-off deposition technique to air gap spacers 158 between the metal lines 152 - 1 . 152 - 2 . 152 - 3 . 152 - 4 . 152 - 5 and 152 - 6 to build. The protective caps 154 and the uniform insulation 155 serve to protect the metal wiring 152 against possible structural damage or contamination that may result from subsequent processing steps and environmental conditions. Example materials and methods for forming the protective caps 154 and the uniform insulation 155 will be described below on the basis of 7 ~ 9 explained in more detail.
The air gap spacers 158 are in recesses between the metal lines 152 - 1 . 152 - 2 . 152 - 3 . 152 - 3 . 152 - 4 . 152 - 5 and 152 - 6 the metal conductor layer 152 formed to the parasitic capacitive coupling between adjacent metal lines of the metal line layer 152 to reduce. As explained in more detail below, as part of the BEOL fabrication process, a dielectric air gap integration process is performed wherein portions of the dielectric material of the ILD layer 151 be etched away to recesses between the metal lines 152 - 1 . 152 - 2 . 152 - 3 , 152-4, 152-5 and 152-6 of the wiring layer 152 to build. The dielectric cover layer 156 is formed using a non-uniform deposition process (eg, chemical vapor deposition) to deposit a dielectric material that is above the top portions of the recesses between the metal lines of the conductive layer 152 "Constricted" areas 156 - 1 forms, causing the air gap spacers 158 be formed. As in 1A As shown, in one embodiment of the invention, the pinch-off areas 156 - 1 over the upper surfaces of the metal lines 152 - 1 , ...., 152-6 the metal conductor layer 152 formed as by the dashed line 1B - 1B displayed. In this context, extend between the metal lines 152 - 1 , ...., 152-6 formed air gap spacers 158 vertically into the dielectric capping layer 156 over the metal lines 152-1 , ...., 152-6 ,
In addition, they extend between the metal lines 152 - 1 , ...., 152-6 formed air gap spacers 158 in one embodiment of the invention as in 1B shown, horizontally (eg in the Y direction) beyond end portions of adjacent metal lines addition. In particular shows 1B an exemplary toothed comb-comb pattern arrangement of the metal wiring layer 152 , where the metal lines 152 - 1 . 152 - 3 and 152 - 5 usually at one end with an extended metal line 152 - 7 are connected, and wherein the metal lines 152 - 2 . 152 - 4 and 152 - 6 at one end with an extended metal line 152 - 8th are connected. As in 1B shown, extend the air gap spacers 158 horizontally across the open (unconnected) ends of the metal lines 152 - 1 , ...., 152-6 , Compared to conventional air gap structures, the size and shape of the offer in the 1A and 1B illustrated air gap spacers 158 improved TDDB reliability and reduced capacitive coupling between the metal lines for reasons now described with reference to FIGS 2A and 2 B be explained in more detail.
The 2A and 2 B illustrate schematically improvements in TDDB reliability and reduced capacitive coupling between metal lines of a BEOL structure achieved with air gap structures formed with pinch-off deposition methods according to embodiments of the invention compared to air gap structures formed by conventional methods. In particular, illustrated 2A schematically a section of Metal wiring layer 152 from 1A including the metal lines 152 - 1 and 152 - 2 and the air gap 158 between the metal lines by forming the dielectric capping layer 156 is formed using a pinch-off deposition method according to an embodiment of the invention. As in 2A shown are the metal lines 152 - 1 and 152 - 2 and the associated linings 153 are formed so that they have a width W and are spaced by a distance S from each other. Further illustrated 2 B schematically a semiconductor structure with an air gap 168 that is between the same two metal wires 152 - 1 and 152 - 2 with the same width W and the same distance S as in 2A is arranged, wherein the air gap 168 however, by forming a dielectric capping layer 166 is formed using a conventional pinch-off deposition method.
As in 2A is the "pinch-off" area 156-1 in the dielectric cover layer 156 designed so that the air gap 158 over the top of the metal lines 152 - 1 and 152 - 2 extends. In contrast, a conventional pinch-off deposition process, as in 2 B shown, to form a Abschnürungsbereichs 166 - 1 in the dielectric cover layer 166 below the top of the metal lines 152 - 1 and 152 - 2 , so that the resulting air gap 168 not over the metal lines 152 - 1 and 152 - 2 extends. In addition, as in the 2A and 2 B comparatively illustrates the amount of dielectric material on the sidewall and bottom surfaces in the recess between the metal lines 152 - 1 and 152 - 2 is deposited, as in 2 B illustrated using a conventional pinch-off deposition method, significantly greater than the amount of dielectric material deposited on the sidewall and bottom surfaces in the recess between the metal lines 152 - 1 and 152 - 2 is deposited, as in 2A using a pinch-off deposition method according to one embodiment of the invention. As a result, there is a volume V1 of the resulting air gap 158 in 2A significantly larger than a volume V2 of the resulting air gap 168 in 2 B ,
The structure in 2A has opposite the in 2 B illustrated conventional structure various advantages. For example, this leads to the larger volume V1 of the air gap 158 (with less dielectric material in the gap between the metal lines) to a smaller parasitic capacitance between the metal lines 152 - 1 and 152 - 2 (compared to the structure of 2 B) , In fact, there is a reduced effective dielectric constant in the gap between the metal lines 152 - 1 and 152 - 2 in 2A compared to 2 B because there is less dielectric material and a large volume of air V1 (k = 1) in the recess between the metal lines 152 - 1 and 152 - 2 in 2A gives.
In addition, the structure of 2A improved reliability of the TDDB compared to the structure of 2 B , In particular, as in 2A shown, there is, as the air gap 158 over the metal lines 152 - 1 and 152 - 2 extends, a long diffusion / conduction path P1 between the critical interfaces of the metal lines 152 - 1 and 152 - 2 (The critical interfaces are an interface between the dielectric capping layer 156 and the top surfaces of the metal lines 152 - 1 and 152 - 2 ). This is in contrast to a shorter diffusion / conduction path P2 in the dielectric cover layer 166 between the critical interfaces of the metal lines 152 - 1 and 152 - 2 in the in 2 B illustrated structure. A TDDB failure mechanism in the structure of 2A or 2 B would be due to the breakdown of the dielectric material and the formation of a conductive path through the dielectric material between the top surfaces of the metal lines 152 - 1 and 152 - 2 due to electron tunneling current. The longer diffusion path P1 in the in 2A illustrated structure coupled with the optional use of a dense dielectric lining material 155 With improved dielectric strength, improved TDDB reliability would increase the structure in 2A compared to the in 2 B show structure presented.
In addition, the horizontal extension of the air gap spacers would 158 beyond the end portions of the metal lines, as in 1B to contribute to further improving the reliability of the TDDB and a reduced capacitive coupling for the same reasons, in relation to 2A were discussed. In particular, as in 1B represented, would be the extension of the air gap 158 over the end of the metal pipe 152 - 1 for example, a long diffusion / conduction path between the critical interface at the open end of the metal line 152 - 1 and the adjacent metal line 152 - 2 enable. In an alternative embodiment of 1B could air gap spacers between the extended metal line 152 - 8th and the adjacent open ends of the metal lines 152 - 1 . 152 - 2 and 152 - 5 and air gap spacers between the extended metal conduit 152 - 7 and the adjacent open ends of the metal lines 152 - 2 . 152 - 4 and 152 - 6 thereby further optimizing the TDDB reliability and reducing the capacitive coupling between the toothed comb structures.
3 FIG. 15 is a schematic side cross-sectional view of a semiconductor device having air gap spacers integrally formed in a BEOL structure of the semiconductor device according to another embodiment of the invention. FIG. In particular, illustrated 3 schematically a semiconductor device 100 ' , which in their structure are in the 1A 1B is a semiconductor device 100 is similar, with the exception that in 3 illustrated air gap spacers 158 not over a bottom of the metal lines of the metallic wiring layer 152 extend beyond. In this structure, the ILD layer would 151 recessed to the lower level of the metal lines (compared to the recess under the bottom of the metal lines, as in 8th presented to the in 1A represented spacers for the extended air gap to form). In other embodiments of the invention, while the 1A and 3 the BEOL structure 130 with first and second connection levels 140 and 150 can show the BEOL structure 130 have one or more additional interconnect levels that cross the second interconnect level 150 are formed. Such additional interconnect levels may be formed with air gap spacers using the techniques and materials described herein.
Method of manufacturing the semiconductor device 100 out 1A (and 3 ) are now based on the 4 to 10 that the semiconductor device 100 schematically represent in different stages, explained in more detail. 4 For example, is a schematic cross section of the semiconductor device 100 in an intermediate stage of manufacture, in which a pattern of openings 151 - 1 (eg, damascene openings with trenches and vias) in the ILD layer 151 is formed according to an embodiment of the invention. In particular, illustrated 4 schematically the semiconductor device 100 from 1A in an intermediate stage of manufacture, after the FEOL / MOL structure 120 , the first connection level 140 , the topcoat 148 and the ILD layer 151 on the substrate 110 were formed sequentially, and after the ILD layer 151 was structured to the openings 151 - 1 in the ILD layer 151 to build. After the deposition of the ILD layer 151 For example, standard photolithography and etching processes can be performed around the openings 151 - 1 in the ILD layer 151 etched, which are then filled with metallic material around the metal wiring layer 152 out 1A to build. It should be noted that in the ILD layer 151 Although no vertical vias are shown, it should be understood that in the second interconnect level 150 vertical vias would be present to make vertical connections to the metallization in the underlying interconnect level 140 manufacture.
In 4 are the openings 151 - 1 shown with a width W and a distance S. In one embodiment of the invention, in forming air gap spacers between closely spaced metal lines by pinching deposition techniques, the width W of the openings (in which the metal lines are formed) may range from about 2 nm to about 25 nm with a preferred range from about 6 nm to about 10 nm. Moreover, in one embodiment, the distance S between the metal lines may be in a range of about 2 nm to about 25 nm with a preferred range of about 6 nm to about 10 nm.
A next process module in the exemplary manufacturing process includes forming the in 1A illustrated metal wiring layer 152 with a process flow, as in the 5 and 6 is shown schematically. In particular 5 a schematic cross section of the semiconductor device of 4 after depositing a uniform layer of lining material 153A and depositing a layer of metallic material 152A on the uniform layer of lining material 153A to the openings 151 - 1 in the ILD layer 151 to fill. In addition, it is 6 a schematic cross section of the semiconductor device of 5 after planarizing the surface of the semiconductor structure down to the ILD layer 151 for forming the metal wiring layer 152 , The metal wiring layer 152 can be formed with known materials and techniques.
For example, the uniform layer becomes the lining material 153A preferably deposited around the sidewall and bottom surfaces of the openings 151 - 1 in the ILD layer 151 to be provided with a thin lining layer. The thin liner layer may be formed by uniformly depositing one or more thin layers of material such as tantalum nitride (TaN), cobalt (Co) or ruthenium (Ru), manganese (Mn) or manganese nitride (MnN) or other lining materials (or combinations of lining materials such as Ta / TaN, TiN, CoWP, NiMoP, NiMoB) which are suitable for the respective application. The thin lining layer fulfills several functions. For example, the thin liner layer serves as a barrier diffusion layer to facilitate migration / diffusion of the metallic material (eg, Cu) into the ILD layer 151 to prevent. In addition, the thin liner layer serves as an adhesive layer to provide good adhesion to the metallic material layer 152A (Eg Cu) to ensure that to fill the openings 151 - 1 in the ILD layer 151 is used.
In one embodiment, the layer of metallic material 152A a metallic material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co) or ruthenium (Ru) deposited by known techniques such as electroplating, electroless plating, CVD, PVD or a combination of methods becomes. Before filling the openings 151 - 1 in the ILD layer 151 Optionally, a thin seed layer (eg, Cu seed layer) may be deposited with the conductive material by a suitable deposition technique such as ALD, CVD, or PVD (on the uniform liner layer 153A) , The seed layer may be formed of a material which improves the adhesion of the metallic material to the base material and which serves as a catalytic material in a subsequent coating process. For example, a thin uniform Cu seed layer may be applied to the surface of the substrate by PVD, followed by Cu plating to fill in the ILD layer 151 - 1 formed openings (eg trenches and vias) and thus forming a Cu metallization 152 , The overcoat, seed and metallization materials are then removed by a chemical mechanical polishing (CMP) process, around the surface of the semiconductor structure to the ILD layer 151 to planarize, leading to the in 6 leads shown intermediate structure.
In one embodiment of the invention, after performing the CMP process, a protective layer may be formed on the exposed surfaces of the metal lines 152 - 1 , ...., 152-6 to protect the metallization from potential damage from subsequent processing conditions and environments. Such is for example 7 a schematic cross section of the semiconductor device of 6 after making caps 154 on the metal lines 152 - 1 , ...., 152-6 according to an embodiment of the invention. In one embodiment, the protective caps 154 for copper metallization using a selective co-deposition process to selectively form a thin coating of Co on the exposed surfaces of the metal lines 152 - 1 , ...., 152-6 deposit. In further embodiments of the invention, the protective caps 154 made of other materials such as tantalum (Ta) or ruthenium (Ru). The protective caps 154 on the metal lines 152 - 1 , ...., 152-6 are optional features that can be used if desired to allow for more aggressive etching conditions, etc., in forming air gap spacers and other structures with the techniques described below.
A next step in the manufacturing process includes forming air gap spacers in the second interconnect level 150 using a process flow as described in the 8th . 9 and 10 is shown schematically. In particular 8th a schematic cross section of the semiconductor device of 7 after etching exposed portions of the ILD layer 151 to recesses 151 - 2 between the metal lines 152 - 1 , ...., 152-6 to form according to an embodiment of the invention. In one embodiment, any suitable masking (eg, photoresist mask) and etching technique (eg, RIE (reactive ion etching, reactive ion etch)) may be used to form portions of the ILD layer 151 to deepen and the recesses 151 - 2 to form, as in 8th shown. For example, in one embodiment using a dry etching technique using a fluorine-based etchant, the dielectric material of the ILD layer 151 be etched away to the recesses 151 - 2 to build. In one embodiment, the recesses are 151 - 2 designed so that the recessed surface of the ILD layer 151 below the bottom surfaces of the metal pipes 152 - 1 , ...., 152-6 lies, as in 8th shown. In a further embodiment, the etching process may be performed such that the recesses 151 - 2 down to a level of the bottom surfaces of the metal wiring 152 be deepened (see 3 ). In areas of metal wiring 152 in which the metal lines are relatively far apart, the ILD layer becomes 151 not removed because the capacitance between the widely spaced metal lines is considered negligible.
A next step in the process is to form a uniform layer of insulating material over the semiconductor structure of FIG 8th deposit to the uniform insulation 155 to form, as in 9 shown. The uniform insulation 155 is an optional protective function that can be formed prior to the pinch-off deposition process around the exposed surfaces of the ILD layer 151 and the metal wiring layer 152 in addition to protect. For example, in the exemplary embodiment of FIG 9 while the uniform lining layers 153 the side walls of the metal pipes 152 - 1 , ...., 152-6 to some extent protect the uniform insulating lining 155 an additional protection against oxidation of the metal lines 152 - 1 , ...., 152-6 provide when the metal lines are formed of copper and the lining layers 153 not sufficient to prevent the diffusion of oxygen into the metal lines from the later formed air gap spacers 158 to prevent. Although the air gap spacers 158 namely, as they are formed later, have a vacuum-like environment, namely, there is still some oxygen content in the air gap spacers 158 that in cases where the lining layers 153 the residual oxygen in the air gap spacers 158 through the lining layers 153 to the metal lines can diffuse, can lead to oxidation of the copper-metal lines.
Furthermore, the uniform insulation 155 are formed with one or more rugged, ultrathin layers of dielectric material that have the desired electrical and mechanical properties such as low leakage current, high electrical breakdown, hydrophobicity, etc., and that can minimize damage by subsequent semiconductor processing steps. For example, the uniform insulation 155 of a dielectric material such as SiN, SiCN, SiNO, SiCNO, SiBN, SiCBN, SiC or other dielectric materials having the desired electrical / mechanical properties as mentioned above. In one embodiment, the uniform insulation 155 formed with a thickness in a range of about 0.5 nm to about 5 nm. The uniform insulation 155 may be formed of a plurality of uniform layers of the same or different dielectric materials deposited by a cyclic deposition process. For example, in one embodiment, the uniform insulation 155 are formed of a plurality of thin uniform SiN layers (eg, 0.1 nm - 0.2 nm thick SiN layers) which are sequentially deposited to form a SiN layer having an overall desired thickness.
As in 9 shown after the formation of uniform insulation 155 the recesses 151 - 2 between the metal lines of the metal wiring layer 152 with an initial volume vi shown. In particular, in an embodiment in which the uniform insulation 155 is formed, the volume becomes vi through the sidewall and bottom surfaces of the uniform insulation 155 and a dashed line L that defines a top of uniform insulation 155 on the metal wiring layer 152 designated. In a further embodiment of the invention, when the uniform insulation liner 155 not formed, would the initial volume vi through the exposed surfaces of the lining layers 153 , the recessed surface of the ILD layer 151 and an upper surface of the metal lines of the metal wiring layer 152 Are defined. As explained below, a significant portion of the initial volume remains vi in the recesses 151 - 2 between the metal lines after the air gap spacers 158 were formed by means of a pinch-off deposition process according to an embodiment of the invention.
A next step in the manufacturing process includes depositing dielectric material over the semiconductor structure of FIG 9 using a pinch-off deposition process, around the air gap spacers 158 in the recess 151 - 2 between the metal lines of the metal conductor layer 152 to build. 10 For example, schematically illustrates a deposition process of a layer of dielectric material 156A using a non-uniform deposition process (eg, PECVD or PVD) to cause the deposition in the deposited dielectric material 156A over the recesses 151 - 2 between the metal lines of the metal wiring layer 152 form Abschnürungsbereiche according to an embodiment of the invention. 1A illustrates the semiconductor device 100 upon completion of the constrictive deposition process, wherein the dielectric overcoat 156 with constriction areas 156 - 1 in the dielectric capping layer and air gap spacers 158 in the rooms 151 - 2 between the metal lines of the metal wiring layer 152 be formed.
According to embodiments of the invention, the structural properties (eg, size, shape, volume, etc.) of the air gap spacers formed by pinch-off deposition may be controlled, eg based on (i) the nature of the one or more dielectric materials to form the dielectric capping layer 156 and / or (ii) the deposition process and associated deposition parameters (eg, gas flow rate, RF power, pressure, deposition rate, etc.) used to perform the pinch-off deposition. For example, in one embodiment of the invention, the cover layer becomes 158 formed by PECVD deposition of a low-k dielectric material (eg, k in a range of about 2.0 to about 5.0). This low-k dielectric material includes, without limitation, SiCOH, porous p-SiCOH, SiCN, carbon-rich SiCNH, p-SiCNH, SiN, SiC, etc. A SiCOH dielectric has a dielectric constant k = 2.7, and a porous SiCOH material has a dielectric constant of about 2.3-2.4. In an exemplary embodiment of the invention, a pinch-off deposition process is implemented in which a SiCN dielectric film is deposited via a plasma CVD deposition process using a 300 mm parallelepiped industrial single-wafer CVD reactor with the following deposition parameters: Trimethylsilane (200-500 standard cubic centimeters per minute (sccm)) and ammonia (300-800 sccm)]; RF power [300 - 600 watts]; Pressure [2-6 torr]; and deposition rate [0.5-5 nm / sec].
In addition, the degree of uniformity of the PECVD deposited dielectric material can be controlled to "pinch off" the dielectric cap layer either above the surface of adjacent metal lines or to reach below the surface of adjacent metal lines. The term "degree of uniformity" of an insulating / dielectric film deposited over a trench having an aspect ratio R of 2 (where R = trench depth / trench opening) is defined herein as a ratio of the thickness of the insulating / dielectric film deposited on a sidewall in the middle of the trench location divided by the thickness of the insulating / dielectric film at the top of the trench location. For example, a 33% degree of uniformity of 3 nm thick insulating / dielectric film over a trench structure having an aperture of 12 nm and a depth of 24 nm (aspect ratio 2 have about 1 nm thickness at the sidewall in the middle of the trench and 3 nm above the trench (uniformity degree = 1 nm / 3 nm ~ 33%).
For example, at a uniformity level of about 40% and less, the in 1A illustrated "constriction" areas 156-1 in the dielectric cover layer 156 above the metal lines of the metal wiring layer 152 educated. This leads to the formation of the air gap spacers 158 extending over the metal lines of the metal wiring layer 152 extend. On the other hand, with a degree of uniformity greater than about 40%, the "pinch-off" areas in the dielectric cap layer would be below the top of the metal lines of the metal line layer 152 educated. This would result in the formation of air gap spacers that do not extend over the metal lines of the metal wiring layer 152 extend.
Depending on the particular application and the dimensions of the air gap / air spacer structures, by adjusting the process parameters of the deposition, a desired degree of uniformity of the PECVD deposited dielectric material can be achieved. For example, for dielectric PECVD materials such as SiN, SiCN, SiCOH, porous p-SiCOH, and other ULK dielectric materials, a lower degree of uniformity can be achieved by increasing RF power, increasing pressure, and / or increasing the deposition rate (eg Increase the flow rate of precursor materials). With decreasing uniformity, the "pinch-off" regions above the metal lines form with minimal deposition of the dielectric material on the exposed sidewall and bottom surfaces within the recesses 151 - 2 leading to the formation of large, voluminous air gap spacers 158 leads, extending over the metal lines of the metal wiring layer 152 extend, as in the 1A and 3 for example.
It should be noted that experimental BEOL test structures as described in the 1A and 3 in which non-uniform cover layers (uniformity less than 40%) of ULK materials (eg, SiCOH, porous p-SiCOH) were formed using "pinch-off" deposition techniques discussed herein to produce large, voluminous air gap To obtain spacers between closely spaced metal lines, wherein the air gap spacers extend over the metal lines, as in the 1A and 3 shown. In addition, experimental results have shown that the pinch-off deposition of such non-uniform cover layers results in very little deposition of dielectric material on the sidewalls and bottom surfaces of the air spaces between the metal lines. Assuming that the recesses 151 - 2 between the metal lines before the formation of the cover layer (as in 9 shown) an initial volume vi The experimental BEOL test structures were made in which a resulting volume of about nVi (where n is in a range of about 0.70 to about 1.0) after forming the air gap spacers using a non-uniform pinch-off Separation method, as described herein, has been achieved.
The dielectric constant of air is about one, which is much smaller than the dielectric constant of the dielectric materials used to form the uniform insulation 155 and the dielectric capping layer 156 be used. In this context, the ability to strictly control and minimize the amount of dielectric material that allows in the recesses 151 - 2 between adjacent metal lines of the metal wiring layer 152 using the techniques described herein, optimizing the electrical performance of BEOL structures by reducing the effective dielectric constant (and hence the parasitic capacitance) between adjacent metal lines of the metal wiring layer 152 , In addition, the ability to perform pinch-off deposition with ULK dielectrics results in a dielectric capping layer 156 with low k value and large volume air gap spacers 158 to generally reduce the effective dielectric constant (and thus reduced parasitic capacitance) of the BEOL structure.
While exemplary embodiments of the above invention illustrate the formation of air gap spacers as part of BEOL structures, similar techniques for forming air gap spacers as part of FEOL / MOL structures may be used to eliminate parasitic couplings between adjacent FEOLs. Reduce MOL structures. For example, air gap spacers may be formed between MOL device contacts and metal gate structures of vertical transistor devices in a FEOL / MOL structure using techniques as described with reference to FIGS 11 - 19 is explained in more detail.
11 FIG. 12 is a schematic side cross-sectional view of a semiconductor device having air gap spacers integrally formed in a FEOL / MOL structure of the semiconductor device according to another embodiment of the invention. In particular, illustrated 11 schematically a semiconductor device 200 that is a substrate 210 / 215 having a bulk substrate layer 210 and an insulation layer 215 (eg, a buried oxide layer of an SOI substrate) and a plurality of vertical transistor structures M1 . M2 . M3 (please refer 12 ) on the substrate 210 / 215 are formed. The vertical transistor structures M1 . M2 . M3 have a standard structural frame that has a semiconductor fin 220 (which extends along the substrate in the X direction), epitaxially grown source (S) / drain (D) regions 225 and corresponding metallic gate structures 230 - 1 . 230 - 2 and 230 - 3 having. The semiconductor rib 220 serves as a vertical channel for the vertical transistor structures M1 . M2 . M3 in areas of the semiconductor rib 220 that of the respective metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 are surrounded. The semiconductor rib 220 can be formed by etching / patterning an active silicon layer deposited on the insulating layer 215 is formed (for example, an SOI layer of an SOI substrate). The semiconductor rib 220 is in 11 not specifically shown, but a top of the semiconductor rib 220 is indicated by the dashed line in 11 (ie channel sections of the semiconductor rib 220 be from the gate structures 230 - 1 . 230 - 2 and 230 - 3 covered, and of the gate structures outgoing portions of the semiconductor rib 220 are encapsulated in epitaxial material on the exposed surfaces of the semiconductor fin 220 has grown).
In an embodiment, the metallic gate structures comprise 230 - 1 . 230 - 2 and 230 - 3 each have a uniform high-k metal gate stack structure attached to a vertical sidewall and top of the semiconductor fin 220 and a gate electrode formed over the high-k metal gate stack structure. Each uniform high-k metal gate stack structure has a uniform layer of gate dielectric material (eg, high-k dielectric such as HfO 2 , Al 2 O 3 , etc.) attached to the sidewall and top of the semiconductor fin 220 and a uniform layer of metal material (eg, Zr, W, Ta, Hf, Ti, Al, Ru, Pa, TaN, TiN, etc.) formed on the uniform gate dielectric material layer. The gate electrode material formed on the high-k metal gate stack structure comprises a low-resistance conductive material including but not limited to tungsten, aluminum, or any metallic or conductive material commonly used to form gate electrodes. Electrode structures is used.
The epitaxial source (S) / drain (D) regions 225 have epitaxial semiconductor material (eg, SiGe, III-V compound semiconductor material, etc.) epitaxially exposed on the semiconductor fin structures 220 grew up, different from the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 extending outgoing. A variety of MOL component contacts 240 / 245 are as part of a MOL layer of the semiconductor device 200 designed to make vertical contacts to the source / drain regions 225 manufacture. Every MOL component contact 240 / 245 has a lining / barrier layer 240 and a conductive via 245 on.
As in further 11 shown are the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 from the MOL contacts 240 / 245 and other surrounding structures through insulating material layers 234 . 250 . 260 and air gap spacers 262 electrically isolated. The layers of insulating material include the lower sidewall spacers 234 , the uniform insulating linings 250 and dielectric capping layers 260 , The lower sidewall spacers 234 isolate the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 electrically from the adjacent source / drain regions 223 , The uniform insulating linings 250 (which are similar in composition and function to the uniform insulating liners 155 the BEOL structure, 1A) uniformly cover the sidewall surfaces of the MOL device contacts 240 / 245 and the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 , The uniform insulating linings 250 are optional features that can be formed to the MOL device contacts 240 / 245 and the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 to protect against possible structural damage or contamination that may result from subsequent processing steps and environmental conditions.
According to embodiments of the invention, the dielectric cover layers 260 by depositing a low-k dielectric material using a pinch-off deposition process around the top portions of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 to encapsulate with low-k dielectric material and the air-gap spacers 262 between the metallic gate structures and the MOL device contacts. A process flow for producing the air gap spacers 262 will be explained in more detail below. As in 11 shown are the air gap spacers 262 relatively large and voluminous and extend vertically over the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 , For reasons similar to those described above in relation to 2A illustrated BEOL air gap spacers 158 Provide the size and shape of the 11 FEOL / MOL air gap spacers shown 262 improved TDDB reliability and reduced capacitive coupling between the MOL device contacts and metallic gate structures.
For example, the large-volume air gap spacers reduce this 262 the effective dielectric constant in the gap between the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 and the MOL component contacts 240 / 245 , Because the air gap spacers 262 , as in 11 represented over the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 In addition, there is a relatively long diffusion / conduction path P between the critical interfaces of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 (The critical interfaces are an interface between the dielectric capping layers 260 and the upper surfaces of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 ) and the adjacent MOL component contacts 240 / 245 , Thus, the air gap spacers serve 262 in 11 to increase the TDDB reliability of the FEOL / MOL semiconductor structure.
11 further illustrates a first interconnect level of a BEOL structure formed over the FEOL / MOL layers, wherein the first interconnect level is an ILD layer 270 and a variety of metal lines 272 / 274 that in the ILD layer 270 in electrical contact with corresponding MOL component contacts 240 / 245 are formed. The metal pipes 272 / 274 are made by etching openings (eg trenches or vias) in the ILD layer 270 , Lining the openings with barrier lining layers 272 and filling the openings with metallic material 274 like copper formed with known techniques.
A process flow for manufacturing the semiconductor device 200 out 11 will now be based on the 12 to 19 that the semiconductor device 200 schematically represent in different stages, explained in more detail. 12 First, a schematic cross section of the semiconductor device 200 in an intermediate stage of manufacturing, in the vertical transistor structures M1 . M2 and M3 on the semiconductor substrate 210 / 215 be formed. In one embodiment, the substrate 210 / 215 an SOI substrate (silicon on insulator), wherein the base substrate 210 silicon or other types of semiconductor substrate materials such as germanium, a silicon germanium alloy, silicon carbide, a silicon germanium carbide alloy, or compound semiconductor materials (eg, III-V and II-VI) that are commonly used in semiconductor mass production processes , Non-limiting examples of compound semiconductor materials are gallium arsenide, indium arsenide and indium phosphide. The insulation layer 215 (Eg oxide layer) is between the base semiconductor substrate 210 and an active semiconductor layer (eg, an active silicon layer), wherein the active semiconductor layer is formed by known methods of fabricating the semiconductor ridge structure 220 is structured. In addition, the epitaxial source / drain regions 225 epitaxially exposed portions of the semiconductor fin structure 220 be raised with known methods.
As in further 12 shown are the metallic gate structures 230 - 1 . 230 - 2 and 230 -3 in insulating / dielectric material structures including insulating cover layers 232 and sidewall spacers 234 capsuled. The cover layers 232 and the sidewall spacers 234 are made with known techniques and insulating materials (eg SiN). The metallic gate structures 230 - 1 . 230 - 2 and 230 - 3 may be formed, for example, by a replacement metal gate (RMG) process in which first dummy gate structures are formed and then after formation of the epitaxial source / drain regions 225 but before formation of the MOL device contacts, through the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 be replaced. In the embodiment of 12 It is assumed that an RMG process was completed, leading to the formation of metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 has led, and that a PMD layer 236 (pre-metal dielectric, pre-metal dielectric) was deposited and planarized, resulting in the in 12 structure shown leads.
The PMD layer 236 is formed by depositing a layer of dielectric material on the surface of the semiconductor device and then depositing the dielectric material down to the top of the cap layers 232 is planarized. The PMD layer 236 can be formed with any suitable insulating / dielectric materials such as silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, porous dielectrics or organic dielectrics including porous organic dielectrics, etc. The PMD layer 236 can be formed by known deposition techniques such as ALD, CVD, PECVD, spin coating or PVD followed by a standard planarization process (eg CMP).
Another process module includes forming the MOL device contacts using a process flow, as in FIGS 13 . 14 and 15 shown schematically. In particular 13 a schematic side cross-section of the semiconductor device of 12 after structuring the PMD layer 236 to contact openings 236 - 1 between the gate structures 230 - 1 . 230 - 2 . 230 - 3 the vertical transistor structures M1 . M2 . M3 down to the source / drain regions 225 to build. The contact openings 236 - 1 can be formed with known etching techniques and etching chemicals to the material of the PMD layer 236 selective to the insulating material of the cover layers 232 and the sidewall spacer 234 to etch.
Next is 14 a schematic side cross-section of the semiconductor device of 13 after depositing a uniform lining layer 240A over the surface of the semiconductor device. The uniform lining layer 240A may comprise a material such as TaN, etc. serving as a barrier diffusion layer and / or adhesive layer for the metallic material used to fill the openings 236 - 1 and used to form the MOL device contacts. Next is 15 a schematic side cross-section of the semiconductor device of 14 After a layer of metallic material has been deposited, around the contact openings 236 - 1 between the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 with conductive material 245 to fill and the surface of the semiconductor device to the gate cladding layers 232 planarize to remove the capping layer and the conductive materials and thereby the MOL contacts 240 / 245 to build. The conductive material 245 may include copper, tungsten, cobalt, aluminum or other conductive materials suitable for use in forming vertical MOL device contacts to the source / drain regions and gate electrodes.
Although in 15 not explicitly shown, MOL gate contacts can be formed in openings passing through the PMD layer 236 and the cover layers 232 down to a top of the metallic gate structures 230 - 1 . 230 - 2 and 230 - 3 be formed. It is understood that the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 in YY Direction (into the drawing plane and out of the drawing plane, based on the in 11 shown Cartesian coordinate system) and thus extend the MOL gate contacts in the PMD layer 236 in alignment with the extended end portions of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 can be formed as understood by a person of ordinary technical skill.
After the formation of the MOL device contacts, another process module includes forming air gap spacers between the metallic gate structures and the MOL device contacts using a process flow as shown in FIGS 16-19 shown schematically. A first step in this process involves etching the gate cap layers 232 and the sidewall spacer 234 , In particular 16 a side cross-section of the semiconductor device of 15 after etching away the gate cladding layers 232 and the recessing of the sidewall spacers 234 down to a top of the semiconductor fin structure 220 , whereby narrow recesses S between the side walls of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 and adjacent MOL device contacts 240 / 245 be formed. While the exemplary embodiment of 16 shows that the gate capping layers 232 are completely etched away, in an alternative embodiment, the etching process can be implemented so that a thin layer of the etched gate cladding layers 232 on the upper surfaces of the metallic gate constructions 230 - 1 . 230 - 2 . 230 - 3 remains.
Next is 17 a schematic side cross-section of the semiconductor device of 16 after depositing a uniform layer of insulating material 250A to provide insulation on the exposed surfaces of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 and the MOL component contacts 240 / 245 to build. The uniform insulating lining layer 250A is an optional protective function that can be formed before the pinch-off deposition process around the exposed surfaces of the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 and the MOL component contacts 240 / 245 for the same or similar reasons as described above.
Furthermore, the uniform insulating lining layer 250A can be formed of one or more rugged, ultrathin layers of dielectric material that have the desired electrical and mechanical properties such as low leakage current, high electrical breakdown, hydrophobicity, etc., and that can minimize damage from subsequent semiconductor processing steps. For example, the uniform insulating lining layer 250A may be formed of a dielectric material such as SiN, SiCN, SiNO, SiCNO, SiC or other dielectric materials having the desired electrical / mechanical properties as mentioned above. In one embodiment, when the distance S ( 16 ) is in a range of about 4 nm to about 15 nm, becomes the uniform insulating liner layer 250A formed with a thickness in a range of about 1.0 nm to about 2 nm, whereby the distance S is reduced by about 2 nm to about 4 nm, through the lining layer 250A on the sidewalls of the adjacent structures.
Similar to the BEOL embodiments discussed above, the uniform insulating liner layer 250A are formed of a plurality of uniform layers of the same or different dielectric materials, which are deposited by means of a cyclic deposition process. For example, in one embodiment, the uniform insulating liner layer 250A are formed of a plurality of thin uniform SiN layers sequentially deposited to form a SiN lining layer having a desired total thickness (eg, using a plasma CVD or CVD method with silane and NH 3 for cyclic deposition of 0, 1 nm - 0.2 nm thick SiN layers).
A next step in the manufacturing process includes depositing dielectric material over the semiconductor structure of FIG 17 using a pinch-off deposition process to form air gap spacers between the metal gate structures and the contacts of the MOL device. 18 For example, FIG. 12 is a schematic side cross-sectional view of the semiconductor device of FIG 17 after depositing a layer of dielectric material 260A using a non-uniform deposition process to create pinch regions comprising the air gap spacers 262 in the narrow spaces between the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 and adjacent MOL device contacts 240 / 245 form. As explained above, according to the embodiments of the invention, the structural characteristics (eg, size, shape, volume, etc.) of the air gap spacers 262 , which are formed by pinch-off deposition, for example, based on (i) the nature of the one or more dielectric materials used to form the dielectric layer 260A and / or (ii) the deposition process and associated deposition parameters (eg, gas flow, RF power, pressure, deposition rate, etc.) used to perform the pinch-off deposition.
For example, in one embodiment of the invention, the layer of dielectric material 260A formed by PECVD deposition of a low-k dielectric material (eg, k in a range of about 2.0 to about 5.0). This low-k dielectric material includes, without limitation, SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, p-SiCNH, SiN, SiC, SiC, etc. A SiCOH dielectric has a dielectric constant k = 2.7 and a porous SiCOH material has a dielectric constant of about 2.3-2.4. In an exemplary embodiment of the invention, a constraining deposition process is realized by depositing a SiN dielectric film via a plasma CVD deposition process using a 300mm parallel plate single wafer industrial CVD reactor with the following deposition parameters: gas [silane (100) 500 sccm) and ammonia ( 200 - 1000 sccm)]; RF power [200 - 600 watts]; Pressure [1-8 torr]; and deposition rates [0.5-8 nm / sec].
19 FIG. 12 is a schematic side cross-sectional view of the semiconductor device of FIG 18 after the surface of the semiconductor device is planarized down to the MOL device contacts and an ILD layer 270 was deposited as part of a first level of connection of a BEOL structure. The semiconductor structure of 18 can be planarized with a standard CMP process, where the CMP process is performed to the dielectric spacer material 260A and parts of the insulating lining layer 250A which are located on the contacts of the MOL device to remove, resulting in the in 19 structure shown leads. As in 19 As shown, the remaining portions of the pinch-off deposited dielectric material form 260A separate dielectric cover structures 260 over the metallic gate structures 230 - 1 . 230 - 2 . 230 - 3 and separate insulation linings 250 , Although not explicitly in the 11 and 19 can be shown before the formation of the ILD layer 270 an additional capping layer may be formed on the planarized FEOL / MOL surface to form the conductive material 245 the MOL device contacts of the dielectric material of the ILD layer 270 to isolate.
Experimental test structures were based on the in 11 schematically illustrated semiconductor structure, wherein the uniform insulating liners 250 were formed with cyclic SiN layers with thicknesses of 1 nm, 1.5 nm, 2 nm and 3 nm and wherein the pinch-off deposition with PECVD-SiCN fillings and PECVD-ULK layers with k = 2.7 and 2.4 was carried out. The experimental results showed that large-volume air gap spacers (air gap spacers 262 , shown schematically in FIG 11 ) extending above the metallic gate structures. In addition, experimental results have shown that size, shape, volume, etc. of air gap spacers can be optimized for different applications by varying the deposition process parameters or the materials used for the pinch-off deposition.
It is to be understood that the methods described herein for making air gap spacers in FEOL / MOL or BEOL layers can be integrated into semiconductor machining operations for fabricating semiconductor devices and integrated circuits having various analog and digital circuits or mixed signal circuits. In particular, integrated circuit chips can be fabricated with various devices such as field effect transistors, bipolar transistors, metal oxide semiconductor transistors, diodes, capacitors, inductors, and so on. An integrated circuit according to the present invention may be used in applications, hardware and / or electronic systems. Suitable hardware and systems for practicing the invention may include, but are not limited to, personal computers, communications networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid state storage devices, functional circuits, and so on. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention contained herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Although exemplary embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to these precise embodiments and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the appended claims.

Claims

Method, comprising Forming a first metal structure and a second metal structure on a substrate, wherein the first and second metal structures are disposed adjacent to each other, with insulating material disposed between the first and second metal structures; Etching the insulating material to form a recess between the first and second metal structures; and Depositing a layer of dielectric material over the first and second metal structures to form an air gap in the recess between the first and second metal structures; wherein a portion of the air gap extends beyond an upper surface of at least one of the first metal structure and the second metal structure.
Method according to Claim 1 wherein the first metal structure comprises a first metal line formed in a dielectric interlayer (ILD) layer of a back-end-of-line (BEOL) interconnect structure, and wherein the second metal structure comprises a second metal line disposed in the ILD layer of the BEOL connection structure is formed.
Method according to Claim 2 wherein the portion of the air gap extends beyond the first metal line and beyond the second metal line.
Method according to Claim 1 wherein the first metal structure has a component contact, and wherein the second metal structure has a gate structure of a transistor.
Method according to Claim 4 wherein the device contact is higher than the gate structure, and wherein the portion of the air gap extends beyond the gate structure and below an upper surface of the device contact.
Method according to Claim 1 wherein depositing a layer of dielectric material over the first and second metal structures comprises depositing a non-uniform layer of dielectric material to form a dielectric capping layer having a pinch-off region disposed flush with the recess between the first and second metal structures ; wherein the pinch-off region in the dielectric cover layer is formed above the top of the at least one first metal structure and the second metal structure.
Method according to Claim 6 wherein depositing the non-uniform layer of dielectric material comprises adjusting deposition parameters of a plasma-enhanced chemical vapor deposition process to obtain a degree of uniformity of about 40% or less.
Method according to Claim 1 wherein the dielectric material comprises a low-k dielectric having a dielectric constant of about 5.0 or less.
Method according to Claim 1 wherein the dielectric material comprises at least one of SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, SiC, p-SiCNH and SiN.
Method according to Claim 1 further comprising forming a uniform liner layer within the recess between the first and second metal structures before depositing the dielectric material over the first and second metal structures to form the air gap in the recess between the first and second metal structures.
A semiconductor device comprising: a first metal structure and a second metal structure adjacent to each other on a substrate a space between the first and second metal structure are arranged; and a dielectric cap layer formed over the first and second metal structures to form an air gap in the recess between the first and second metal structures; wherein a portion of the air gap extends beyond an upper surface of at least one of the first metal structure and the second metal structure.
Device after Claim 11 wherein the first metal structure comprises a first metal line formed in a dielectric interlayer (ILD) layer of a back-end-of-line (BEOL) interconnect structure, and wherein the second metal structure comprises a second metal line disposed in the ILD layer of the BEOL connection structure is formed.
Device after Claim 12 wherein the portion of the air gap extends beyond the first metal line and beyond the second metal line.
Device after Claim 11 wherein the first metal structure has a component contact, and wherein the second metal structure has a gate structure of a transistor.
Device after Claim 14 wherein the device contact is higher than the gate structure, and wherein the portion of the air gap extends beyond the gate structure and below an upper surface of the device contact.
Device after Claim 11 wherein the dielectric cap layer comprises a non-uniform layer of dielectric material having a pinch-off region disposed flush with the recess between the first and second metal structures; wherein the pinch-off region in the dielectric cover layer is arranged above the upper side of the at least one first metal structure and the second metal structure.
Device after Claim 16 wherein a degree of uniformity of the non-uniform dielectric material layer is about 40% or less.
Device after Claim 11 wherein the dielectric cap layer comprises a low-k dielectric having a dielectric constant of about 5.0 or less.
Device after Claim 11 wherein the dielectric capping layer comprises at least one of SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, SiC, p-SiCNH and SiN.
Device after Claim 11 , further comprising a uniform liner layer formed on surfaces in the recess between the first and second metal structures.